[RISCV] Add vector instructions for FPR64.

[HsiangKai]

Summary

For ".vf" instructions, there is a floating point scalar argument for the operations. If the scalar type of the argument is f64, we need to assign FPR64 for it.

In this patch, I add "CodeGenOnly" instructions for the FPR64 version of the instructions. For example, there are two instructions for vfadd.vf. One is VFADD_VF for FPR32 and the other is VFADD_VD for FPR64.

[HsiangKai]

This comment was removed by HsiangKai.

[HsiangKai]

FPR32 version V instructions should be enough for CodeGen.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
     : RVInstIVI<funct6, (outs VRegOp:$vd),
                 (ins VRegOp:$vs2, optype:$imm),
                 opcodestr, "$vd, $vs2, $imm"> {
   let vm = 1;
 }
 
 // op vd, vs2, rs1, vm (Float)
-class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+             RegisterClass ScalarOp = FPR32>
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
+                (ins VRegOp:$vs2, ScalarOp:$rs1, VMaskOp:$vm),
                 opcodestr, "$vd, $vs2, $rs1$vm">;
 
 // op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
-class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              RegisterClass ScalarOp = FPR32>
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                (ins ScalarOp:$rs1, VRegOp:$vs2, VMaskOp:$vm),
                 opcodestr, "$vd, $rs1, $vs2$vm">;
 
 // op vd, vs2, vm (use vs1 as instruction encoding)
 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
     : RVInstV<funct6, vs1, opv, (outs VRegOp:$vd),
                (ins VRegOp:$vs2, VMaskOp:$vm),
                opcodestr, "$vd, $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0

 multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
   def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">;
   def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">;
 }
 
 multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
   def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">;
 }
 
 multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;

 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // Vector Floating-Point Merge Instruction
 def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
                            (ins VRegOp:$vs2, FPR32:$rs1, VMV0:$v0),
                            "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
   let vm = 0;
 }
+let isCodeGenOnly = 1 in {
+def VFMERGE_VDM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+                           (ins VRegOp:$vs2, FPR64:$rs1, VMV0:$v0),
+                           "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
+  let vm = 0;
+}
+}
 
 // Vector Floating-Point Move Instruction
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
                        (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
   let vs2 = 0;
   let vm = 1;
 }
+let isCodeGenOnly = 1 in {
+def VFMV_V_D : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+                       (ins FPR64:$rs1), "vfmv.v.f", "$vd, $rs1"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
 defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
 defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
 defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
 defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
 defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;

 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in {
 // Floating-Point Scalar Move Instructions
 def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
                       (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
 def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
                       (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
-
+let isCodeGenOnly = 1 in {
+def VFMV_D_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR64:$vd),
+                      (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
+def VFMV_S_D : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
+                      (ins FPR64:$rs1), "vfmv.s.f", "$vd, $rs1">;
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
 
 // Vector Slide Instructions
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
 defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;