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[ARM] Generate [SU]HADD from ((a + b) >> 1)
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Authored by PetreTudor on Tue, Jul 14, 7:59 AM.

Details

Summary

Teach LLVM to recognize the above pattern, where the operands are
either signed or unsigned types.

Diff Detail

Event Timeline

PetreTudor created this revision.Tue, Jul 14, 7:59 AM
efriedma added inline comments.Tue, Jul 14, 12:18 PM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
8904

While you're in the area, can you convert this to a TargetDAGCombine? All the types and operations involved here are legal, so there's no need to mix it up with legalization.

Converted tryLowerToHalvingAdd to a TargetDAGCombine.

PetreTudor marked an inline comment as done.Thu, Jul 16, 2:46 AM
efriedma added inline comments.Thu, Jul 16, 12:40 PM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
8891

This should return SDValue();.

8896

This should return SDValue();.

11152

It's a little confusing to have an ADD called "Sub".

Addressed review comments.

PetreTudor marked 3 inline comments as done.Fri, Jul 17, 6:37 AM
This revision is now accepted and ready to land.Mon, Jul 20, 2:57 PM
This revision was automatically updated to reflect the committed changes.