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PetreTudor (Petre Tudor)
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User Since
Apr 3 2020, 3:54 AM (34 w, 3 d)

Recent Activity

Jul 21 2020

PetreTudor committed rG1af9fc82132d: [ARM] Generate [SU]HADD from ((a + b) >> 1) (authored by PetreTudor).
[ARM] Generate [SU]HADD from ((a + b) >> 1)
Jul 21 2020, 5:22 AM
PetreTudor closed D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1).
Jul 21 2020, 5:22 AM · Restricted Project

Jul 17 2020

PetreTudor updated the diff for D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1).

Addressed review comments.

Jul 17 2020, 6:36 AM · Restricted Project

Jul 15 2020

PetreTudor updated the diff for D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1).

Converted tryLowerToHalvingAdd to a TargetDAGCombine.

Jul 15 2020, 6:56 AM · Restricted Project

Jul 14 2020

PetreTudor added reviewers for D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1): dmgreen, SjoerdMeijer, sdesmalen, efriedma.
Jul 14 2020, 8:02 AM · Restricted Project
Herald added a project to D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1): Restricted Project.
Jul 14 2020, 7:59 AM · Restricted Project

Jul 3 2020

PetreTudor committed rGaf80a4353e14: [ARM] Generate [SU]RHADD from (b - (~a)) >> 1 (authored by PetreTudor).
[ARM] Generate [SU]RHADD from (b - (~a)) >> 1
Jul 3 2020, 8:03 AM
PetreTudor closed D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.
Jul 3 2020, 8:03 AM · Restricted Project
PetreTudor updated the diff for D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.

Added comments explaining why we are always looking for AArch64ISD::VLSHR

Jul 3 2020, 3:12 AM · Restricted Project

Jul 2 2020

PetreTudor updated the diff for D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.

Fixed some comments and simplified the extract index checks
to just look for indexes of 0 and N00VT.getVectorNumElements()

Jul 2 2020, 3:10 AM · Restricted Project

Jun 30 2020

PetreTudor added inline comments to D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.
Jun 30 2020, 10:51 AM · Restricted Project
PetreTudor updated the diff for D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.

Addressed review comments:

  • Added extra checks
  • Added SRHADD generation from very similar pattern
  • Added tests for 64-bit vectors
Jun 30 2020, 10:50 AM · Restricted Project

Jun 26 2020

PetreTudor added a reviewer for D82669: [ARM] Generate URHADD from (b - (~a)) >> 1: dmgreen.
Jun 26 2020, 10:55 AM · Restricted Project
PetreTudor created D82669: [ARM] Generate URHADD from (b - (~a)) >> 1.
Jun 26 2020, 10:55 AM · Restricted Project

May 12 2020

PetreTudor committed rG9682d0d5dcc5: [ARM] Refactor lower to S[LR]I optimization (authored by PetreTudor).
[ARM] Refactor lower to S[LR]I optimization
May 12 2020, 3:11 AM
PetreTudor closed D79233: [ARM] Refactor lower to S[LR]I optimization.
May 12 2020, 3:11 AM · Restricted Project

May 11 2020

PetreTudor updated the diff for D79233: [ARM] Refactor lower to S[LR]I optimization.

Added a test for the isAllConstantBuildVector case. The BICi case happens
when the constant values' sizes are greater than 8 bits.

May 11 2020, 9:39 AM · Restricted Project

May 4 2020

PetreTudor updated the diff for D79233: [ARM] Refactor lower to S[LR]I optimization.

Addressed reviewers' comments.

May 4 2020, 7:27 AM · Restricted Project

May 1 2020

PetreTudor added a comment to D79233: [ARM] Refactor lower to S[LR]I optimization.

The problem with the original patch was that ElemMask would overflow, since it was only 32-bit wide. The patch now makes use of APInt to avoid this type of situation.

May 1 2020, 4:53 AM · Restricted Project
PetreTudor added reviewers for D79233: [ARM] Refactor lower to S[LR]I optimization: dmgreen, SjoerdMeijer, mstorsjo, efriedma.
May 1 2020, 4:51 AM · Restricted Project
PetreTudor created D79233: [ARM] Refactor lower to S[LR]I optimization.
May 1 2020, 4:48 AM · Restricted Project

Apr 20 2020

PetreTudor committed rG52474992b134: Revert "[ARM] Fix conditions for lowering to S[LR]I" (authored by PetreTudor).
Revert "[ARM] Fix conditions for lowering to S[LR]I"
Apr 20 2020, 8:38 AM
PetreTudor added a reverting change for rGcabfcf840a9d: [ARM] Fix conditions for lowering to S[LR]I: rG52474992b134: Revert "[ARM] Fix conditions for lowering to S[LR]I".
Apr 20 2020, 8:38 AM
PetreTudor added a comment to D77387: [ARM] Fix conditions for lowering to S[LR]I.

It appears that there were probably more things wrong with this optimization than just the condition.
I have reverted the patch for now so that I can take more time to make sure that I get this fix right.

Apr 20 2020, 8:37 AM · Restricted Project

Apr 17 2020

PetreTudor committed rGcabfcf840a9d: [ARM] Fix conditions for lowering to S[LR]I (authored by PetreTudor).
[ARM] Fix conditions for lowering to S[LR]I
Apr 17 2020, 9:43 AM
PetreTudor closed D77387: [ARM] Fix conditions for lowering to S[LR]I.
Apr 17 2020, 9:43 AM · Restricted Project

Apr 15 2020

PetreTudor updated the diff for D77387: [ARM] Fix conditions for lowering to S[LR]I.

Simplified logic for converting intrinsics to AArch64ISD::VS[LR]I.

Apr 15 2020, 5:59 AM · Restricted Project

Apr 14 2020

PetreTudor updated the diff for D77387: [ARM] Fix conditions for lowering to S[LR]I.

Fix styling problem caused by linter (inconsistent with local style).

Apr 14 2020, 8:00 AM · Restricted Project
PetreTudor updated the diff for D77387: [ARM] Fix conditions for lowering to S[LR]I.

Now lowering to S[LR]I via TableGen + ISel nodes.

Apr 14 2020, 7:27 AM · Restricted Project

Apr 3 2020

PetreTudor added inline comments to D77387: [ARM] Fix conditions for lowering to S[LR]I.
Apr 3 2020, 7:30 AM · Restricted Project
PetreTudor added reviewers for D77387: [ARM] Fix conditions for lowering to S[LR]I: dmgreen, SjoerdMeijer.
Apr 3 2020, 6:56 AM · Restricted Project
PetreTudor created D77387: [ARM] Fix conditions for lowering to S[LR]I.
Apr 3 2020, 6:24 AM · Restricted Project