- User Since
- Apr 3 2020, 3:54 AM (34 w, 3 d)
Jul 21 2020
Jul 17 2020
Addressed review comments.
Jul 15 2020
Converted tryLowerToHalvingAdd to a TargetDAGCombine.
Jul 14 2020
Jul 3 2020
Added comments explaining why we are always looking for AArch64ISD::VLSHR
Jul 2 2020
Fixed some comments and simplified the extract index checks
to just look for indexes of 0 and N00VT.getVectorNumElements()
Jun 30 2020
Addressed review comments:
- Added extra checks
- Added SRHADD generation from very similar pattern
- Added tests for 64-bit vectors
Jun 26 2020
May 12 2020
May 11 2020
Added a test for the isAllConstantBuildVector case. The BICi case happens
when the constant values' sizes are greater than 8 bits.
May 4 2020
Addressed reviewers' comments.
May 1 2020
The problem with the original patch was that ElemMask would overflow, since it was only 32-bit wide. The patch now makes use of APInt to avoid this type of situation.
Apr 20 2020
It appears that there were probably more things wrong with this optimization than just the condition.
I have reverted the patch for now so that I can take more time to make sure that I get this fix right.
Apr 17 2020
Apr 15 2020
Simplified logic for converting intrinsics to AArch64ISD::VS[LR]I.
Apr 14 2020
Fix styling problem caused by linter (inconsistent with local style).
Now lowering to S[LR]I via TableGen + ISel nodes.