[X86-64] Support Intel AMX instructions

[craig.topper]

Summary

INTEL ADVANCED MATRIX EXTENSIONS (AMX).
AMX is a new programming paradigm, it has a set of 2-dimensional registers
(TILES) representing sub-arrays from a larger 2-dimensional memory image and
operate on TILES.

Spec can be found in Chapter 3 here https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

[craig.topper]

llvm/lib/Target/X86/X86RegisterInfo.td

268

Drop the "These aren't really registers. Or are they?"

llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll

1 ↗

(On Diff #273902)

The intrinsics aren't in this patch so you can't test them.

llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll

1 ↗

(On Diff #273902)

Same here

llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll

1 ↗

(On Diff #273902)

And here

llvm/utils/TableGen/X86RecognizableInstr.cpp

651

It shouldn't be optional.

llvm/utils/TableGen/X86RecognizableInstr.h

105

This needs to be rebased. The existing MRMDestMem is encoding 24 as of some recent changes.

[xiangzhangllvm]

Done, but I find the last llvm code can not pass "make check-all", no relation with this patch.

[craig.topper]

llvm/lib/Target/X86/X86RegisterInfo.td

637

I think this should be just TILE. The V seems unnecessary and in every other case means Vector. This is more like a matrix so vector doesn't make sense

[xiangzhangllvm]

Change VTILE to TILE

[craig.topper]

LGTM

[xiangzhangllvm]

3 case failed

LLVM :: MC/Disassembler/X86/simple-tests.txt
LLVM :: MC/Disassembler/X86/x86-16.txt
LLVM :: MC/Disassembler/X86/x86-32.txt

echo "0x0f 0xae 0xe8" | llvm-mc --disassemble -triple=i686-apple-darwin9
should print "lfence"
but print "warning: invalid instruction encoding"

something changed the "modRMTable" in TD file "X86GenDisassemblerTables.inc"
I am trying to find the reason.

[pengfei]

llvm/utils/TableGen/X86RecognizableInstr.cpp

804

You missed break here. That's the reason it failed.

[craig.topper]

Commandeering to fix a disassembler issue where we would crash if the VEX.vvvv field is set to 0x8-0xf(after inverting). Now we report it as an invalid encoding.

[craig.topper]

-Fix the previously noted missing break
-Prevent trying to create a register encoding past tmm7

[xiangzhangllvm]

In D82705#2124135, @craig.topper wrote:

-Fix the previously noted missing break
-Prevent trying to create a register encoding past tmm7

OK

llvm/utils/TableGen/X86RecognizableInstr.cpp

804

Thank you very much!!

[LuoYuanke]

llvm/test/MC/X86/AMX/x86-64-amx-error.s

9

Do we have an error case that test the register number should be constrained to tmm0 ~ tmm7? Both for assembly and disassembly?

[xiangzhangllvm]

check-llvm passed.
LGTM

[craig.topper]

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

783

Here's the range check for tmm0-tmm7 I added

llvm/test/MC/X86/AMX/x86-64-amx-error.s

9

The assembler can’t parse a register that doesnt have a name. Only tmm0-7 are defined.

I fixed the disassembler earlier today.

[xiangzhangllvm]

Hello, Craig, can I commit it now?

[craig.topper]

In D82705#2124660, @xiangzhangllvm wrote:

Hello, Craig, can I commit it now?

Yes

[MaskRay]

@xiangzhangllvm

Hi, your git commit contains extra Phabricator tags. You can drop Reviewers: Subscribers: Tags: and the text Summary: from the git commit with the following script:

arcfilter () {
        arc amend
        git log -1 --pretty=%B | awk '/Reviewers:|Subscribers:/{p=1} /Reviewed By:|Differential Revision:/{p=0} !p && !/^Summary:$/ {sub(/^Summary: /,"");print}' | git commit --amend --date=now -F -
}

Reviewed By: is considered important by some people. Please keep the tag. (--date=now is my personal preference (author dates are usually not useful. Using committer dates can make log almost monotonic in time))

llvm/utils/git/pre-push.py can validate the message does not include unneeded tags.

[xiangzhangllvm]

I tried it, it just remove tags, not tags with their info, I miss-understand at first, thank you!

llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h

 //                  corresponds to instructions that use reg field as opcode
 // MODRM_FULL     - Potentially, each value of the ModR/M byte could correspond
 //                  to a different instruction.
 #define MODRMTYPES            \
   ENUM_ENTRY(MODRM_ONEENTRY)  \
   ENUM_ENTRY(MODRM_SPLITRM)   \
   ENUM_ENTRY(MODRM_SPLITMISC)  \
   ENUM_ENTRY(MODRM_SPLITREG)  \
+  ENUM_ENTRY(MODRM_SPLITREGM) \
   ENUM_ENTRY(MODRM_FULL)
 
 #define ENUM_ENTRY(n) n,
 enum ModRMDecisionType {
   MODRMTYPES
   MODRM_max
 };
 #undef ENUM_ENTRY
#define ENCODINGS                                                              \
   ENUM_ENTRY(ENCODING_REG,    "Register operand in ModR/M byte.")              \
   ENUM_ENTRY(ENCODING_RM,     "R/M operand in ModR/M byte.")                   \
   ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2")           \
   ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4")           \
   ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8")           \
   ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16")          \
   ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32")          \
   ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64")          \
+  ENUM_ENTRY(ENCODING_SIB,      "Force SIB operand in ModR/M byte.")           \
   ENUM_ENTRY(ENCODING_VSIB,     "VSIB operand in ModR/M byte.")                \
   ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2")        \
   ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4")        \
   ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8")        \
   ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16")       \
   ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32")       \
   ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64")       \
   ENUM_ENTRY(ENCODING_VVVV,   "Register operand in VEX.vvvv byte.")            \
#define TYPES                                                                  \
   ENUM_ENTRY(TYPE_REL,        "immediate address")                             \
   ENUM_ENTRY(TYPE_R8,         "1-byte register operand")                       \
   ENUM_ENTRY(TYPE_R16,        "2-byte")                                        \
   ENUM_ENTRY(TYPE_R32,        "4-byte")                                        \
   ENUM_ENTRY(TYPE_R64,        "8-byte")                                        \
   ENUM_ENTRY(TYPE_IMM,        "immediate operand")                             \
   ENUM_ENTRY(TYPE_UIMM8,      "1-byte unsigned immediate operand")             \
   ENUM_ENTRY(TYPE_M,          "Memory operand")                                \
+  ENUM_ENTRY(TYPE_MSIB,       "Memory operand force sib encoding")             \
   ENUM_ENTRY(TYPE_MVSIBX,     "Memory operand using XMM index")                \
   ENUM_ENTRY(TYPE_MVSIBY,     "Memory operand using YMM index")                \
   ENUM_ENTRY(TYPE_MVSIBZ,     "Memory operand using ZMM index")                \
   ENUM_ENTRY(TYPE_SRCIDX,     "memory at source index")                        \
   ENUM_ENTRY(TYPE_DSTIDX,     "memory at destination index")                   \
   ENUM_ENTRY(TYPE_MOFFS,      "memory offset (relative to segment base)")      \
   ENUM_ENTRY(TYPE_ST,         "Position on the floating-point stack")          \
   ENUM_ENTRY(TYPE_MM64,       "8-byte MMX register")                           \
   ENUM_ENTRY(TYPE_XMM,        "16-byte")                                       \
   ENUM_ENTRY(TYPE_YMM,        "32-byte")                                       \
   ENUM_ENTRY(TYPE_ZMM,        "64-byte")                                       \
   ENUM_ENTRY(TYPE_VK,         "mask register")                                 \
   ENUM_ENTRY(TYPE_VK_PAIR,    "mask register pair")                            \
+  ENUM_ENTRY(TYPE_TMM,        "tile")                                          \
   ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand")                      \
   ENUM_ENTRY(TYPE_DEBUGREG,   "Debug register operand")                        \
   ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand")                      \
   ENUM_ENTRY(TYPE_BNDR,       "MPX bounds register")                           \
                                                                                \
   ENUM_ENTRY(TYPE_Rv,         "Register operand of operand size")              \
   ENUM_ENTRY(TYPE_RELv,       "Immediate address of operand size")             \
   ENUM_ENTRY(TYPE_DUP0,       "Duplicate of operand 0")                        \

llvm/lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["movbe"]  = (ECX >> 22) & 1;
   Features["popcnt"] = (ECX >> 23) & 1;
   Features["aes"]    = (ECX >> 25) & 1;
   Features["rdrnd"]  = (ECX >> 30) & 1;
 
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
   // indicates that the AVX registers will be saved and restored on context
   // switch, then we have full AVX support.
-  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
-                    !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
+  bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
+  bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
 #if defined(__APPLE__)
   // Darwin lazily saves the AVX512 context on first use: trust that the OS will
   // save the AVX512 context if we use AVX512 instructions, even the bit is not
   // set right now.
   bool HasAVX512Save = true;
 #else
   // AVX512 requires additional context to be saved by the OS.
   bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
 #endif
+  // AMX requires additional context to be saved by the OS.
+  const unsigned AMXBits = (1 << 17) | (1 << 18);
+  bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
 
   Features["avx"]   = HasAVXSave;
   Features["fma"]   = ((ECX >> 12) & 1) && HasAVXSave;
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
   Features["f16c"]  = ((ECX >> 29) & 1) && HasAVXSave;
 
   unsigned MaxExtLevel;
#endif
   // bit of EDX), while the EAX=0x1b leaf returns information on the
   // availability of specific pconfig leafs.
   // The target feature here only refers to the the first of these two.
   // Users might need to check for the availability of specific pconfig
   // leaves using cpuid, since that information is ignored while
   // detecting features using the "-march=native" flag.
   // For more info, see X86 ISA docs.
   Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
+  Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
+  Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
+  Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
   bool HasLeaf7Subleaf1 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
 
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.

llvm/lib/Target/X86/AsmParser/X86Operand.h

bool isMem128() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 128);
   }
   bool isMem256() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 256);
   }
   bool isMem512() const {
     return Kind == Memory && (!Mem.Size || Mem.Size == 512);
   }
+
+  bool isSibMem() const {
+    return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
+  }
+
   bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
     assert(Kind == Memory && "Invalid access!");
     return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
   }
 
   bool isMem64_RC128() const {
     return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
   }

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

static InstrUID decode(OpcodeType type, InstructionContext insnContext,
   case MODRM_SPLITRM:
     if (modFromModRM(modRM) == 0x3)
       return modRMTable[dec->instructionIDs + 1];
     return modRMTable[dec->instructionIDs];
   case MODRM_SPLITREG:
     if (modFromModRM(modRM) == 0x3)
       return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
     return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
+  case MODRM_SPLITREGM:
+    assert(modFromModRM(modRM) == 0x3);
+    return modRMTable[dec->instructionIDs+(modRM & 0x7)];
   case MODRM_SPLITMISC:
     if (modFromModRM(modRM) == 0x3)
       return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
     return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
   case MODRM_FULL:
     return modRMTable[dec->instructionIDs + modRM];
   }
 }
case TYPE_R64:                                                             \
         *valid = 0;                                                            \
       return prefix##_RAX + index;                                             \
     case TYPE_ZMM:                                                             \
       return prefix##_ZMM0 + index;                                            \
     case TYPE_YMM:                                                             \
       return prefix##_YMM0 + index;                                            \
     case TYPE_XMM:                                                             \
       return prefix##_XMM0 + index;                                            \
+    case TYPE_TMM:                                                             \
+      if (index > 7)                                                           \
+        *valid = 0;                                                            \
+      return prefix##_TMM0 + index;                                            \
     case TYPE_VK:                                                              \
       index &= 0xf;                                                            \
       if (index > 7)                                                           \
         *valid = 0;                                                            \
       return prefix##_K0 + index;                                              \
     case TYPE_VK_PAIR:                                                         \
       if (index > 7)                                                           \
         *valid = 0;                                                            \
if (!valid)
       return -1;
     break;
   case ENCODING_REG:
     insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type,
                                    insn->reg - insn->regBase, &valid);
     if (!valid)
       return -1;
     break;
+  case ENCODING_SIB:
   CASE_ENCODING_RM:
     if (insn->eaBase >= insn->eaRegBase) {
       insn->eaBase = (EABase)fixupRMValue(
           insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid);
       if (!valid)
         return -1;
     }
     break;
CASE_ENCODING_VSIB:
             (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase));
         break;
       }
 
       // Apply the AVX512 compressed displacement scaling factor.
       if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
         insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
       break;
+    case ENCODING_SIB:
+      // Reject if SIB wasn't used.
+      if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
+        return -1;
+      if (readModRM(insn))
+        return -1;
+      if (fixupReg(insn, &Op))
+        return -1;
+      break;
     case ENCODING_REG:
     CASE_ENCODING_RM:
       if (readModRM(insn))
         return -1;
       if (fixupReg(insn, &Op))
         return -1;
       // Apply the AVX512 compressed displacement scaling factor.
       if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)

 
 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
 ///   fields of an internal instruction (and possibly its SIB byte) to a memory
 ///   operand in LLVM's format, and appends it to an MCInst.
 ///
 /// @param mcInst       - The MCInst to append to.
 /// @param insn         - The instruction to extract Mod, R/M, and SIB fields
 ///                       from.
+/// @param ForceSIB     - The instruction must use SIB.
 /// @return             - 0 on success; nonzero otherwise
 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
-                              const MCDisassembler *Dis) {
+                              const MCDisassembler *Dis,
+                              bool ForceSIB = false) {
   // Addresses in an MCInst are represented as five operands:
   //   1. basereg       (register)  The R/M base, or (if there is a SIB) the
   //                                SIB base
   //   2. scaleamount   (immediate) 1, or (if there is a SIB) the specified
   //                                scale amount
   //   3. indexreg      (register)  x86_registerNONE, or (if there is a SIB)
   //                                the index (which is multiplied by the
   //                                scale amount)
#undef ENTRY
     } else {
       // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
       // but no index is used and modrm alone should have been enough.
       // -No base register in 32-bit mode. In 64-bit mode this is used to
       //  avoid rip-relative addressing.
       // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
       //  base always requires a SIB byte.
       // -A scale other than 1 is used.
-      if (insn.sibScale != 1 ||
+      if (!ForceSIB &&
+          (insn.sibScale != 1 ||
            (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
            (insn.sibBase != SIB_BASE_NONE &&
             insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
-           insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12)) {
+            insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) {
         indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
                                                                 X86::RIZ);
       } else
         indexReg = MCOperand::createReg(X86::NoRegister);
     }
 
     scaleAmount = MCOperand::createImm(insn.sibScale);
   } else {
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
   case TYPE_R16:
   case TYPE_R32:
   case TYPE_R64:
   case TYPE_Rv:
   case TYPE_MM64:
   case TYPE_XMM:
   case TYPE_YMM:
   case TYPE_ZMM:
+  case TYPE_TMM:
   case TYPE_VK_PAIR:
   case TYPE_VK:
   case TYPE_DEBUGREG:
   case TYPE_CONTROLREG:
   case TYPE_BNDR:
     return translateRMRegister(mcInst, insn);
   case TYPE_M:
   case TYPE_MVSIBX:
   case TYPE_MVSIBY:
   case TYPE_MVSIBZ:
     return translateRMMemory(mcInst, insn, Dis);
+  case TYPE_MSIB:
+    return translateRMMemory(mcInst, insn, Dis, true);
   }
 }
 
 /// translateFPRegister - Translates a stack position on the FPU stack to its
 ///   LLVM form, and appends it to an MCInst.
 ///
 /// @param mcInst       - The MCInst to append to.
 /// @param stackPos     - The stack position to translate.
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
   default:
     debug("Unhandled operand encoding during translation");
     return true;
   case ENCODING_REG:
     translateRegister(mcInst, insn.reg);
     return false;
   case ENCODING_WRITEMASK:
     return translateMaskRegister(mcInst, insn.writemask);
+  case ENCODING_SIB:
   CASE_ENCODING_RM:
   CASE_ENCODING_VSIB:
     return translateRM(mcInst, operand, insn, Dis);
   case ENCODING_IB:
   case ENCODING_IW:
   case ENCODING_ID:
   case ENCODING_IO:
   case ENCODING_Iv:

llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h

#define REGS_CONTROL  \
   ENTRY(CR15)
 
 #define REGS_BOUND    \
   ENTRY(BND0)         \
   ENTRY(BND1)         \
   ENTRY(BND2)         \
   ENTRY(BND3)
 
+#undef  REGS_TMM
+#define REGS_TMM  \
+  ENTRY(TMM0)     \
+  ENTRY(TMM1)     \
+  ENTRY(TMM2)     \
+  ENTRY(TMM3)     \
+  ENTRY(TMM4)     \
+  ENTRY(TMM5)     \
+  ENTRY(TMM6)     \
+  ENTRY(TMM7)
+
 #define ALL_EA_BASES  \
   EA_BASES_16BIT      \
   EA_BASES_32BIT      \
   EA_BASES_64BIT
 
 #define ALL_SIB_BASES \
   REGS_32BIT          \
   REGS_64BIT
 
 #define ALL_REGS      \
   REGS_8BIT           \
   REGS_16BIT          \
   REGS_32BIT          \
   REGS_64BIT          \
   REGS_MMX            \
   REGS_XMM            \
   REGS_YMM            \
   REGS_ZMM            \
   REGS_MASKS          \
   REGS_MASK_PAIRS     \
   REGS_SEGMENT        \
   REGS_DEBUG          \
   REGS_CONTROL        \
   REGS_BOUND          \
+  REGS_TMM            \
   ENTRY(RIP)
 
 /// All possible values of the base field for effective-address
 /// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
 /// We distinguish between bases (EA_BASE_*) and registers that just happen
 /// to be referred to when Mod == 0b11 (EA_REG_*).
 enum EABase {
   EA_BASE_NONE,

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

enum : uint64_t {
     /// byte like data16 or rep.
     PrefixByte = 10,
 
     /// MRM[0-7][rm] - These forms are used to represent instructions that use
     /// a Mod/RM byte, and use the middle field to hold extended opcode
     /// information.  In the intel manual these are represented as /0, /1, ...
     ///
 
+    // Instructions operate on a register Reg/Opcode operand not the r/m field.
+    MRMr0 = 21,
+
+    /// MRMSrcMem - But force to use the SIB field.
+    MRMSrcMemFSIB  = 22,
+
+    /// MRMDestMem - But force to use the SIB field.
+    MRMDestMemFSIB = 23,
+
     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
     /// to specify a destination, which in this case is memory.
     ///
     MRMDestMem     = 24,
 
     /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
     /// to specify a source, which in this case is memory.
     ///
inline int getMemoryOperandNo(uint64_t TSFlags) {
     case X86II::RawFrmMemOffs:
     case X86II::RawFrmSrc:
     case X86II::RawFrmDst:
     case X86II::RawFrmDstSrc:
     case X86II::AddCCFrm:
     case X86II::PrefixByte:
       return -1;
     case X86II::MRMDestMem:
+    case X86II::MRMDestMemFSIB:
       return 0;
     case X86II::MRMSrcMem:
+    case X86II::MRMSrcMemFSIB:
       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
       // mask register.
       return 1 + HasVEX_4V + HasEVEX_K;
     case X86II::MRMSrcMem4VOp3:
       // Skip registers encoded in reg.
       return 1 + HasEVEX_K;
     case X86II::MRMSrcMemOp4:
       // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
       return 3;
     case X86II::MRMSrcMemCC:
       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
       // mask register.
       return 1;
     case X86II::MRMDestReg:
     case X86II::MRMSrcReg:
     case X86II::MRMSrcReg4VOp3:
     case X86II::MRMSrcRegOp4:
     case X86II::MRMSrcRegCC:
     case X86II::MRMXrCC:
+    case X86II::MRMr0:
     case X86II::MRMXr:
     case X86II::MRM0r: case X86II::MRM1r:
     case X86II::MRM2r: case X86II::MRM3r:
     case X86II::MRM4r: case X86II::MRM5r:
     case X86II::MRM6r: case X86II::MRM7r:
       return -1;
     case X86II::MRM0X: case X86II::MRM1X:
     case X86II::MRM2X: case X86II::MRM3X:

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
                         raw_ostream &OS) const;
 
   void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
                    raw_ostream &OS) const;
 
   void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
                         uint64_t TSFlags, bool HasREX, uint64_t StartByte,
                         raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
-                        const MCSubtargetInfo &STI) const;
+                        const MCSubtargetInfo &STI,
+                        bool ForceSIB = false) const;
 
   bool emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
                       const MCSubtargetInfo &STI, raw_ostream &OS) const;
 
   void emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
                            raw_ostream &OS) const;
 
   void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
   emitByte(modRMByte(SS, Index, Base), OS);
 }
 
 void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
                                         unsigned RegOpcodeField,
                                         uint64_t TSFlags, bool HasREX,
                                         uint64_t StartByte, raw_ostream &OS,
                                         SmallVectorImpl<MCFixup> &Fixups,
-                                        const MCSubtargetInfo &STI) const {
+                                        const MCSubtargetInfo &STI,
+                                        bool ForceSIB) const {
   const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
   const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
   const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
   const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
   unsigned BaseReg = Base.getReg();
   bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
 
   // Handle %rip relative addressing.
   if (BaseReg == X86::RIP ||
       BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
     assert(STI.hasFeature(X86::Mode64Bit) &&
            "Rip-relative addressing requires 64-bit mode");
-    assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
+    assert(IndexReg.getReg() == 0 && !ForceSIB &&
+           "Invalid rip-relative address");
     emitByte(modRMByte(0, RegOpcodeField, 5), OS);
 
     unsigned Opcode = MI.getOpcode();
     // movq loads are handled with a special relocation form which allows the
     // linker to eliminate some loads for GOT references which end up in the
     // same linkage unit.
     unsigned FixupKind = [=]() {
       switch (Opcode) {
void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
   }
 
   // Determine whether a SIB byte is needed.
   // If no BaseReg, issue a RIP relative instruction only if the MCE can
   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
   // 2-7) and absolute references.
 
   if ( // The SIB byte must be used if there is an index register.
-      IndexReg.getReg() == 0 &&
+      !ForceSIB && IndexReg.getReg() == 0 &&
       // The SIB byte must be used if the base is ESP/RSP/R12, all of which
       // encode to an R/M value of 4, which indicates that a SIB byte is
       // present.
       BaseRegNo != N86::ESP &&
       // If there is no base register and we're in 64-bit mode, we need a SIB
       // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
       (!STI.hasFeature(X86::Mode64Bit) || BaseReg != 0)) {
 
void X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
 
   // Classify VEX_B, VEX_4V, VEX_R, VEX_X
   unsigned NumOps = Desc.getNumOperands();
   unsigned CurOp = X86II::getOperandBias(Desc);
 
   switch (TSFlags & X86II::FormMask) {
   default:
     llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
+  case X86II::MRM_C0:
   case X86II::RawFrm:
   case X86II::PrefixByte:
     break;
+  case X86II::MRMDestMemFSIB:
   case X86II::MRMDestMem: {
     // MRMDestMem instructions forms:
     //  MemAddr, src1(ModR/M)
     //  MemAddr, src1(VEX_4V), src2(ModR/M)
     //  MemAddr, src1(ModR/M), imm8
     //
     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
     VEX_B = ~(BaseRegEnc >> 3) & 1;
if (HasVEX_4V) {
       EVEX_V2 = ~(VRegEnc >> 4) & 1;
     }
 
     unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
     VEX_R = ~(RegEnc >> 3) & 1;
     EVEX_R2 = ~(RegEnc >> 4) & 1;
     break;
   }
+  case X86II::MRMSrcMemFSIB:
   case X86II::MRMSrcMem: {
     // MRMSrcMem instructions forms:
     //  src1(ModR/M), MemAddr
     //  src1(ModR/M), src2(VEX_4V), MemAddr
     //  src1(ModR/M), MemAddr, imm8
     //  src1(ModR/M), MemAddr, src2(Imm[7:4])
     //
     //  FMA4:
case X86II::MRMDestReg: {
 
     RegEnc = getX86RegEncoding(MI, CurOp++);
     VEX_R = ~(RegEnc >> 3) & 1;
     EVEX_R2 = ~(RegEnc >> 4) & 1;
     if (EVEX_b)
       EncodeRC = true;
     break;
   }
+  case X86II::MRMr0: {
+    // MRMr0 instructions forms:
+    //  11:rrr:000
+    //  dst(ModR/M)
+    unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
+    VEX_R = ~(RegEnc >> 3) & 1;
+    EVEX_R2 = ~(RegEnc >> 4) & 1;
+    break;
+  }
   case X86II::MRM0r:
   case X86II::MRM1r:
   case X86II::MRM2r:
   case X86II::MRM3r:
   case X86II::MRM4r:
   case X86II::MRM5r:
   case X86II::MRM6r:
   case X86II::MRM7r: {
uint8_t REX = [&, MemOperand]() {
     case X86II::MRM2r:
     case X86II::MRM3r:
     case X86II::MRM4r:
     case X86II::MRM5r:
     case X86II::MRM6r:
     case X86II::MRM7r:
       REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
       break;
+    case X86II::MRMr0:
+      REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
+      break;
+    case X86II::MRMDestMemFSIB:
+      llvm_unreachable("FSIB format never need REX prefix!");
     }
     if (REX && UsesHighByteReg)
       report_fatal_error(
           "Cannot encode high byte register in REX-prefixed instruction");
     return REX;
   }();
 
   if (!REX)
case X86II::MRMDestReg: {
     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
       ++SrcRegNum;
 
     emitRegModRMByte(MI.getOperand(CurOp),
                      getX86RegNum(MI.getOperand(SrcRegNum)), OS);
     CurOp = SrcRegNum + 1;
     break;
   }
+  case X86II::MRMDestMemFSIB:
   case X86II::MRMDestMem: {
     emitByte(BaseOpcode, OS);
     unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
 
     if (HasEVEX_K) // Skip writemask
       ++SrcRegNum;
 
     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
       ++SrcRegNum;
 
+    bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
     emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
-                     HasREX, StartByte, OS, Fixups, STI);
+                     HasREX, StartByte, OS, Fixups, STI, ForceSIB);
     CurOp = SrcRegNum + 1;
     break;
   }
   case X86II::MRMSrcReg: {
     emitByte(BaseOpcode, OS);
     unsigned SrcRegNum = CurOp + 1;
 
     if (HasEVEX_K) // Skip writemask
case X86II::MRMSrcRegCC: {
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
     emitByte(BaseOpcode + CC, OS);
 
     emitRegModRMByte(MI.getOperand(SecondOp),
                      getX86RegNum(MI.getOperand(FirstOp)), OS);
     break;
   }
+  case X86II::MRMSrcMemFSIB:
   case X86II::MRMSrcMem: {
     unsigned FirstMemOp = CurOp + 1;
 
     if (HasEVEX_K) // Skip writemask
       ++FirstMemOp;
 
     if (HasVEX_4V)
       ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
 
     emitByte(BaseOpcode, OS);
 
+    bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
-                     TSFlags, HasREX, StartByte, OS, Fixups, STI);
+                     TSFlags, HasREX, StartByte, OS, Fixups, STI, ForceSIB);
     CurOp = FirstMemOp + X86::AddrNumOperands;
     if (HasVEX_I8Reg)
       I8RegNum = getX86RegEncoding(MI, CurOp++);
     break;
   }
   case X86II::MRMSrcMem4VOp3: {
     unsigned FirstMemOp = CurOp + 1;
 
case X86II::MRM7r:
     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
       ++CurOp;
     if (HasEVEX_K) // Skip writemask
       ++CurOp;
     emitByte(BaseOpcode, OS);
     emitRegModRMByte(MI.getOperand(CurOp++),
                      (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, OS);
     break;
+  case X86II::MRMr0:
+    emitByte(BaseOpcode, OS);
+    emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)),0), OS);
+    break;
 
   case X86II::MRMXmCC: {
     unsigned FirstMemOp = CurOp;
     CurOp = FirstMemOp + X86::AddrNumOperands;
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
     emitByte(BaseOpcode + CC, OS);
 

llvm/lib/Target/X86/X86.td

def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
                                       "Enable Cache Demote">;
 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
                                       "Support ptwrite instruction">;
 // FIXME: This feature is deprecated in 10.0 and should not be used for
 // anything, but removing it would break IR files that may contain it in a
 // target-feature attribute.
 def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false",
                                       "Deprecated. Support MPX instructions">;
+def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
+                                      "Support AMX-TILE instructions">;
+def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
+                                      "Support AMX-INT8 instructions",
+                                      [FeatureAMXTILE]>;
+def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
+                                      "Support AMX-BF16 instructions",
+                                      [FeatureAMXTILE]>;
 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
                                      "Use LEA for adjusting the stack pointer">;
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
                                      "HasSlowDivide64", "true",
                                      "Use 32-bit divide for positive values less than 2^32">;

llvm/lib/Target/X86/X86InstrAMX.td

+//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the Intel AMX instruction
+// set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// AMX instructions
+
+let Predicates = [HasAMXTILE, In64BitMode] in {
+  let SchedRW = [WriteSystem] in {
+    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
+    def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
+                       "ldtilecfg\t$src", []>, VEX, T8PS;
+    def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
+                       "sttilecfg\t$src", []>, VEX, T8PD;
+    def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
+                      (ins sibmem:$src),
+                      "tileloadd\t{$src, $dst|$dst, $src}", []>,
+                      VEX, T8XD;
+    def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
+                        (ins sibmem:$src),
+                        "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
+                        VEX, T8PD;
+    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
+    def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
+                        "tilerelease", []>, VEX, T8PS;
+    def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
+                       (ins sibmem:$dst, TILE:$src),
+                       "tilestored\t{$src, $dst|$dst, $src}", []>,
+                       VEX, T8XS;
+    def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
+                     "tilezero\t$dst", []>,
+                     VEX, T8XD;
+  } // SchedRW
+} // HasAMXTILE
+
+let Predicates = [HasAMXINT8, In64BitMode] in {
+  let SchedRW = [WriteSystem] in {
+    let Constraints = "$src1 = $dst" in {
+      def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
+                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
+                      "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                      VEX_4V, T8XD;
+      def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
+                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
+                      "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                      VEX_4V, T8XS;
+      def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
+                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
+                      "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                      VEX_4V, T8PD;
+      def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
+                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
+                      "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                      VEX_4V, T8PS;
+    }
+  }
+} // HasAMXTILE
+
+let Predicates = [HasAMXBF16, In64BitMode] in {
+  let SchedRW = [WriteSystem] in {
+    let Constraints = "$src1 = $dst" in
+    def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
+                      (ins TILE:$src1, TILE:$src2, TILE:$src3),
+                      "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+                      []>, VEX_4V, T8XS;
+  }
+} // HasAMXTILE, HasAMXBF16

llvm/lib/Target/X86/X86InstrFormats.td

 def RawFrmMemOffs : Format<3>;
 def RawFrmSrc     : Format<4>;
 def RawFrmDst     : Format<5>;
 def RawFrmDstSrc  : Format<6>;
 def RawFrmImm8    : Format<7>;
 def RawFrmImm16   : Format<8>;
 def AddCCFrm      : Format<9>;
 def PrefixByte    : Format<10>;
+def MRMr0          : Format<21>;
+def MRMSrcMemFSIB  : Format<22>;
+def MRMDestMemFSIB : Format<23>;
 def MRMDestMem     : Format<24>;
 def MRMSrcMem      : Format<25>;
 def MRMSrcMem4VOp3 : Format<26>;
 def MRMSrcMemOp4   : Format<27>;
 def MRMSrcMemCC    : Format<28>;
 def MRMXmCC: Format<30>;
 def MRMXm  : Format<31>;
 def MRM0m  : Format<32>;  def MRM1m  : Format<33>;  def MRM2m  : Format<34>;

llvm/lib/Target/X86/X86InstrInfo.td

let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
   def X86Mem64_RC128XOperand  : AsmOperandClass { let Name = "Mem64_RC128X"; }
   def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; }
   def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; }
   def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; }
   def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; }
   def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; }
   def X86Mem256_RC512Operand  : AsmOperandClass { let Name = "Mem256_RC512"; }
   def X86Mem512_RC512Operand  : AsmOperandClass { let Name = "Mem512_RC512"; }
+
+  def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; }
 }
 
 def X86AbsMemAsmOperand : AsmOperandClass {
   let Name = "AbsMem";
   let SuperClasses = [X86MemAsmOperand];
 }
 
 class X86MemOperand<string printMethod,

 def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
                           [(X86strict_fcmp node:$lhs, node:$rhs),
                            (X86fcmp node:$lhs, node:$rhs)]>;
 
 // FIXME: Right now we allow any size during parsing, but we might want to
 // restrict to only unsized memory.
 def opaquemem : X86MemOperand<"printMemReference">;
 
+def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>;
+
 def i8mem   : X86MemOperand<"printbytemem",   X86Mem8AsmOperand>;
 def i16mem  : X86MemOperand<"printwordmem",  X86Mem16AsmOperand>;
 def i32mem  : X86MemOperand<"printdwordmem",  X86Mem32AsmOperand>;
 def i64mem  : X86MemOperand<"printqwordmem",  X86Mem64AsmOperand>;
 def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand>;
 def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand>;
 def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand>;
 def f32mem  : X86MemOperand<"printdwordmem",  X86Mem32AsmOperand>;

 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
 def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def HasENQCMD    : Predicate<"Subtarget->hasENQCMD()">;
 def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
 def HasTSXLDTRK  : Predicate<"Subtarget->hasTSXLDTRK()">;
+def HasAMXTILE   : Predicate<"Subtarget->hasAMXTILE()">;
+def HasAMXBF16   : Predicate<"Subtarget->hasAMXBF16()">;
+def HasAMXINT8   : Predicate<"Subtarget->hasAMXINT8()">;
 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
                              AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">;
 def In64BitMode  : Predicate<"Subtarget->is64Bit()">,
                              AssemblerPredicate<(all_of Mode64Bit), "64-bit mode">;
 def IsLP64  : Predicate<"Subtarget->isTarget64BitLP64()">;
 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
 def In16BitMode  : Predicate<"Subtarget->is16Bit()">,
                              AssemblerPredicate<(all_of Mode16Bit), "16-bit mode">;

 include "X86InstrMPX.td"
 
 include "X86InstrVMX.td"
 include "X86InstrSVM.td"
 
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
 
+// AMX instructions
+include "X86InstrAMX.td"
+
 // System instructions.
 include "X86InstrSystem.td"
 
 // Compiler Pseudo Instructions and Pat Patterns
 include "X86InstrCompiler.td"
 include "X86InstrVecCompiler.td"
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86RegisterInfo.td

 // ZMM Registers, used by AVX-512 instructions.
 let SubRegIndices = [sub_ymm] in {
   foreach  Index = 0-31 in {
     def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
                     DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
   }
 }
 
+// Tile "registers".
+def TMM0:  X86Reg<"tmm0",   0>;
+def TMM1:  X86Reg<"tmm1",   1>;
+def TMM2:  X86Reg<"tmm2",   2>;
+def TMM3:  X86Reg<"tmm3",   3>;
+def TMM4:  X86Reg<"tmm4",   4>;
+def TMM5:  X86Reg<"tmm5",   5>;
+def TMM6:  X86Reg<"tmm6",   6>;
+def TMM7:  X86Reg<"tmm7",   7>;
+
 // Mask Registers, used by AVX-512 instructions.
 def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118,  93,  93]>;
 def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119,  94,  94]>;
 def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120,  95,  95]>;
 def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121,  96,  96]>;
 def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122,  97,  97]>;
 def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123,  98,  98]>;
 def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124,  99,  99]>;

 def VK4WM   : RegisterClass<"X86", [v4i1],  16,  (sub VK4, K0)> {let Size = 16;}
 def VK8WM   : RegisterClass<"X86", [v8i1],  16,  (sub VK8, K0)> {let Size = 16;}
 def VK16WM  : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>   {let Size = 16;}
 def VK32WM  : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
 def VK64WM  : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
 
 // Bound registers
 def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
+
+// Tiles
+let isAllocatable = 0 in
+def TILE : RegisterClass<"X86", [untyped], 0,
+                         (sequence "TMM%u", 0, 7)> {let Size = 8192;}

llvm/lib/Target/X86/X86Subtarget.h

protected:
   bool HasPCONFIG = false;
 
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
   /// Processor supports TSXLDTRK instruction
   bool HasTSXLDTRK = false;
 
+  /// Processor has AMX support
+  bool HasAMXTILE = false;
+  bool HasAMXBF16 = false;
+  bool HasAMXINT8 = false;
+
   /// Processor has a single uop BEXTR implementation.
   bool HasFastBEXTR = false;
 
   /// Try harder to combine to horizontal vector ops if they are fast.
   bool HasFastHorizontalOps = false;
 
   /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
   bool HasFastScalarShiftMasks = false;
public:
   bool hasINVPCID() const { return HasINVPCID; }
   bool hasENQCMD() const { return HasENQCMD; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
   bool useRetpolineIndirectBranches() const {
     return UseRetpolineIndirectBranches;
   }
+  bool hasAMXTILE() const { return HasAMXTILE; }
+  bool hasAMXBF16() const { return HasAMXBF16; }
+  bool hasAMXINT8() const { return HasAMXINT8; }
   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 
   // These are generic getters that OR together all of the thunk types
   // supported by the subtarget. Therefore useIndirectThunk*() will return true
   // if any respective thunk feature is enabled.
   bool useIndirectThunkCalls() const {
     return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
   }

llvm/test/CodeGen/X86/ipra-reg-usage.ll

 ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
 
 target triple = "x86_64-unknown-unknown"
 declare void @bar1()
 define preserve_allcc void @foo()#0 {
-; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $fpcw $fpsw $fs $gs $hip $ip $mxcsr $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh
+; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $fpcw $fpsw $fs $gs $hip $ip $mxcsr $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh
   call void @bar1()
   call void @bar2()
   ret void
 }
 declare void @bar2()
 
 @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)]
 
 attributes #0 = {nounwind}

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-bf16-att.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
+
+# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5c,0xda

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-bf16-intel.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK: tdpbf16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5c,0xda
+
+# CHECK: tdpbf16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5c,0xf5
+
+# CHECK: tdpbf16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5c,0xda

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-error.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding
+0xc4,0xe2,0x1a,0x5c,0xf5

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-int8-att.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
+
+# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x70,0x5e,0xda

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-int8-intel.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK: tdpbssd tmm6, tmm5, tmm4
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd tmm3, tmm2, tmm1
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd tmm6, tmm5, tmm4
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd tmm3, tmm2, tmm1
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud tmm6, tmm5, tmm4
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud tmm3, tmm2, tmm1
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd tmm6, tmm5, tmm4
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd tmm3, tmm2, tmm1
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd tmm6, tmm5, tmm4
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd tmm3, tmm2, tmm1
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud tmm6, tmm5, tmm4
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud tmm3, tmm2, tmm1
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd tmm6, tmm5, tmm4
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd tmm3, tmm2, tmm1
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd tmm6, tmm5, tmm4
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd tmm3, tmm2, tmm1
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud tmm6, tmm5, tmm4
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud tmm3, tmm2, tmm1
+0xc4,0xe2,0x70,0x5e,0xda
+
+# CHECK: tdpbssd tmm6, tmm5, tmm4
+0xc4,0xe2,0x5b,0x5e,0xf5
+
+# CHECK: tdpbssd tmm3, tmm2, tmm1
+0xc4,0xe2,0x73,0x5e,0xda
+
+# CHECK: tdpbsud tmm6, tmm5, tmm4
+0xc4,0xe2,0x5a,0x5e,0xf5
+
+# CHECK: tdpbsud tmm3, tmm2, tmm1
+0xc4,0xe2,0x72,0x5e,0xda
+
+# CHECK: tdpbusd tmm6, tmm5, tmm4
+0xc4,0xe2,0x59,0x5e,0xf5
+
+# CHECK: tdpbusd tmm3, tmm2, tmm1
+0xc4,0xe2,0x71,0x5e,0xda
+
+# CHECK: tdpbuud tmm6, tmm5, tmm4
+0xc4,0xe2,0x58,0x5e,0xf5
+
+# CHECK: tdpbuud tmm3, tmm2, tmm1
+0xc4,0xe2,0x70,0x5e,0xda

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tile-att.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilezero %tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero %tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: tilezero %tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero %tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: ldtilecfg  268435456(%rbp,%r14,8)
+0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: ldtilecfg  291(%r8,%rax,4)
+0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: ldtilecfg  (%rip)
+0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: ldtilecfg  -2048(,%rbp,2)
+0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: sttilecfg  268435456(%rbp,%r14,8)
+0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: sttilecfg  291(%r8,%rax,4)
+0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: sttilecfg  (%rip)
+0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: sttilecfg  -2048(,%rbp,2)
+0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
+0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloadd 291(%r8,%rax,4), %tmm3
+0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloadd -32(,%rbp,2), %tmm3
+0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloadd 64(%rbx), %tmm4
+0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40
+
+# CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
+0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
+0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloaddt1 16(%rbp), %tmm6
+0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
+0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tilestored %tmm3, 291(%r8,%rax,4)
+0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tilestored %tmm3, -32(,%rbp,2)
+0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilezero %tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero %tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: ldtilecfg  268435456(%rbp,%r14,8)
+0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: ldtilecfg  291(%r8,%rax,4)
+0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: ldtilecfg  (%rip)
+0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: ldtilecfg  -2048(,%rbp,2)
+0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: sttilecfg  268435456(%rbp,%r14,8)
+0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: sttilecfg  291(%r8,%rax,4)
+0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: sttilecfg  (%rip)
+0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: sttilecfg  -2048(,%rbp,2)
+0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
+0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloadd 291(%r8,%rax,4), %tmm3
+0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloadd -32(,%rbp,2), %tmm3
+0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
+0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
+0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
+0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tilestored %tmm3, 291(%r8,%rax,4)
+0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tilestored %tmm3, -32(,%rbp,2)
+0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilestored %tmm3, (%r8)
+0xc4,0xc2,0x7a,0x4b,0x1c,0x20
+
+# CHECK: tilezero %tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero %tmm3
+0xc4,0xe2,0x7b,0x49,0xd8

llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tile-intel.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilezero tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilezero tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: ldtilecfg [r8 + 4*rax + 291]
+0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: ldtilecfg [rip]
+0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: ldtilecfg [2*rbp - 2048]
+0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: sttilecfg [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: sttilecfg [r8 + 4*rax + 291]
+0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: sttilecfg [rip]
+0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: sttilecfg [2*rbp - 2048]
+0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
+0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloadd tmm3, [2*rbp - 32]
+0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloadd tmm4, [rbx + 64]
+0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40
+
+# CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
+0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloaddt1 tmm3, [2*rbp - 32]
+0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloaddt1     tmm6, [rbp + 16]
+0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
+0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tilestored [r8 + 4*rax + 291], tmm3
+0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tilestored [2*rbp - 32], tmm3
+0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilestored [r8], tmm3
+0xc4,0xc2,0x7a,0x4b,0x1c,0x20
+
+# CHECK: tilezero tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero tmm3
+0xc4,0xe2,0x7b,0x49,0xd8
+
+# CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: ldtilecfg [r8 + 4*rax + 291]
+0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: ldtilecfg [rip]
+0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: ldtilecfg [2*rbp - 2048]
+0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: sttilecfg [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: sttilecfg [r8 + 4*rax + 291]
+0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: sttilecfg [rip]
+0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
+
+# CHECK: sttilecfg [2*rbp - 2048]
+0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
+
+# CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
+0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloadd tmm3, [2*rbp - 32]
+0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
+0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tileloaddt1 tmm3, [2*rbp - 32]
+0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilerelease
+0xc4,0xe2,0x78,0x49,0xc0
+
+# CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
+0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: tilestored [r8 + 4*rax + 291], tmm3
+0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
+
+# CHECK: tilestored [2*rbp - 32], tmm3
+0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
+
+# CHECK: tilezero tmm6
+0xc4,0xe2,0x7b,0x49,0xf0
+
+# CHECK: tilezero tmm3
+0xc4,0xe2,0x7b,0x49,0xd8

llvm/test/MC/X86/AMX/x86-64-amx-bf16-att.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
+// some AMX instruction must use SIB.
+
+// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps %tmm1, %tmm2, %tmm3

llvm/test/MC/X86/AMX/x86-64-amx-bf16-intel.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: tdpbf16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps tmm6, tmm5, tmm4
+
+// CHECK: tdpbf16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps tmm3, tmm2, tmm1
+
+// CHECK: tdpbf16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps tmm6, tmm5, tmm4
+
+// CHECK: tdpbf16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps tmm3, tmm2, tmm1
+
+// CHECK: tdpbf16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps tmm6, tmm5, tmm4
+
+// CHECK: tdpbf16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps tmm3, tmm2, tmm1
+
+// CHECK: tdpbf16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
+          tdpbf16ps tmm6, tmm5, tmm4
+
+// CHECK: tdpbf16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
+          tdpbf16ps tmm3, tmm2, tmm1

llvm/test/MC/X86/AMX/x86-64-amx-error.s

+// RUN: not llvm-mc -triple x86_64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
+
+// CHECK: invalid operand for instruction
+tileloadd (%rip), %tmm0
+
+// CHECK: invalid operand for instruction
+tileloaddt1 1(%rip), %tmm1
+
+// CHECK: invalid operand for instruction
+tilestored %tmm2, (%rip)

llvm/test/MC/X86/AMX/x86-64-amx-int8-att.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
+// some AMX instruction must use SIB.
+
+// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd %tmm1, %tmm2, %tmm3
+
+// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud %tmm4, %tmm5, %tmm6
+
+// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud %tmm1, %tmm2, %tmm3

llvm/test/MC/X86/AMX/x86-64-amx-int8-intel.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: tdpbssd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd tmm6, tmm5, tmm4
+
+// CHECK: tdpbssd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd tmm3, tmm2, tmm1
+
+// CHECK: tdpbsud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud tmm6, tmm5, tmm4
+
+// CHECK: tdpbsud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud tmm3, tmm2, tmm1
+
+// CHECK: tdpbusd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd tmm6, tmm5, tmm4
+
+// CHECK: tdpbusd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd tmm3, tmm2, tmm1
+
+// CHECK: tdpbuud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud tmm6, tmm5, tmm4
+
+// CHECK: tdpbuud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud tmm3, tmm2, tmm1
+
+// CHECK: tdpbssd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd tmm6, tmm5, tmm4
+
+// CHECK: tdpbssd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd tmm3, tmm2, tmm1
+
+// CHECK: tdpbsud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud tmm6, tmm5, tmm4
+
+// CHECK: tdpbsud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud tmm3, tmm2, tmm1
+
+// CHECK: tdpbusd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd tmm6, tmm5, tmm4
+
+// CHECK: tdpbusd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd tmm3, tmm2, tmm1
+
+// CHECK: tdpbuud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud tmm6, tmm5, tmm4
+
+// CHECK: tdpbuud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud tmm3, tmm2, tmm1
+
+// CHECK: tdpbssd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd tmm6, tmm5, tmm4
+
+// CHECK: tdpbssd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd tmm3, tmm2, tmm1
+
+// CHECK: tdpbsud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud tmm6, tmm5, tmm4
+
+// CHECK: tdpbsud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud tmm3, tmm2, tmm1
+
+// CHECK: tdpbusd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd tmm6, tmm5, tmm4
+
+// CHECK: tdpbusd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd tmm3, tmm2, tmm1
+
+// CHECK: tdpbuud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud tmm6, tmm5, tmm4
+
+// CHECK: tdpbuud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud tmm3, tmm2, tmm1
+
+// CHECK: tdpbssd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
+          tdpbssd tmm6, tmm5, tmm4
+
+// CHECK: tdpbssd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
+          tdpbssd tmm3, tmm2, tmm1
+
+// CHECK: tdpbsud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
+          tdpbsud tmm6, tmm5, tmm4
+
+// CHECK: tdpbsud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
+          tdpbsud tmm3, tmm2, tmm1
+
+// CHECK: tdpbusd tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
+          tdpbusd tmm6, tmm5, tmm4
+
+// CHECK: tdpbusd tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
+          tdpbusd tmm3, tmm2, tmm1
+
+// CHECK: tdpbuud tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
+          tdpbuud tmm6, tmm5, tmm4
+
+// CHECK: tdpbuud tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
+          tdpbuud tmm3, tmm2, tmm1

llvm/test/MC/X86/AMX/x86-64-amx-tile-att.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
+// some AMX instruction must use SIB.
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilezero %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero %tmm6
+
+// CHECK: tilezero %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero %tmm3
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilezero %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero %tmm6
+
+// CHECK: tilezero %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero %tmm3
+
+// CHECK: ldtilecfg  268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          ldtilecfg  268435456(%rbp,%r14,8)
+
+// CHECK: ldtilecfg  291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          ldtilecfg  291(%r8,%rax,4)
+
+// CHECK: ldtilecfg  (%rip)
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
+          ldtilecfg  (%rip)
+
+// CHECK: ldtilecfg  -2048(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          ldtilecfg  -2048(,%rbp,2)
+
+// CHECK: sttilecfg  268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          sttilecfg  268435456(%rbp,%r14,8)
+
+// CHECK: sttilecfg  291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          sttilecfg  291(%r8,%rax,4)
+
+// CHECK: sttilecfg  (%rip)
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
+          sttilecfg  (%rip)
+
+// CHECK: sttilecfg  -2048(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          sttilecfg  -2048(,%rbp,2)
+
+// CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
+// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloadd 268435456(%rbp,%r14,8), %tmm6
+
+// CHECK: tileloadd 291(%r8,%rax,4), %tmm3
+// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloadd 291(%r8,%rax,4), %tmm3
+
+// CHECK: tileloadd 64(%rbx), %tmm4
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40]
+          tileloadd 64(%rbx), %tmm4
+
+// CHECK: tileloadd -32(,%rbp,2), %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloadd -32(,%rbp,2), %tmm3
+
+// CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+
+// CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
+// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloaddt1 291(%r8,%rax,4), %tmm3
+
+// CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloaddt1 -32(,%rbp,2), %tmm3
+
+// CHECK: tileloaddt1 16(%rbp), %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10]
+          tileloaddt1 16(%rbp), %tmm6
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tilestored %tmm6, 268435456(%rbp,%r14,8)
+
+// CHECK: tilestored %tmm3, 291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tilestored %tmm3, 291(%r8,%rax,4)
+
+// CHECK: tilestored %tmm3, -32(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tilestored %tmm3, -32(,%rbp,2)
+
+// CHECK: tilestored %tmm3, (%r8)
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x1c,0x20]
+          tilestored %tmm3, (%r8)
+
+// CHECK: tilezero %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero %tmm6
+
+// CHECK: tilezero %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero %tmm3
+
+// CHECK: ldtilecfg  268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          ldtilecfg  268435456(%rbp,%r14,8)
+
+// CHECK: ldtilecfg  291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          ldtilecfg  291(%r8,%rax,4)
+
+// CHECK: ldtilecfg  (%rip)
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
+          ldtilecfg  (%rip)
+
+// CHECK: ldtilecfg  -2048(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          ldtilecfg  -2048(,%rbp,2)
+
+// CHECK: sttilecfg  268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          sttilecfg  268435456(%rbp,%r14,8)
+
+// CHECK: sttilecfg  291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          sttilecfg  291(%r8,%rax,4)
+
+// CHECK: sttilecfg  (%rip)
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
+          sttilecfg  (%rip)
+
+// CHECK: sttilecfg  -2048(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          sttilecfg  -2048(,%rbp,2)
+
+// CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
+// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloadd 268435456(%rbp,%r14,8), %tmm6
+
+// CHECK: tileloadd 291(%r8,%rax,4), %tmm3
+// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloadd 291(%r8,%rax,4), %tmm3
+
+// CHECK: tileloadd -32(,%rbp,2), %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloadd -32(,%rbp,2), %tmm3
+
+// CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloaddt1 268435456(%rbp,%r14,8), %tmm6
+
+// CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
+// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloaddt1 291(%r8,%rax,4), %tmm3
+
+// CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloaddt1 -32(,%rbp,2), %tmm3
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
+// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tilestored %tmm6, 268435456(%rbp,%r14,8)
+
+// CHECK: tilestored %tmm3, 291(%r8,%rax,4)
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tilestored %tmm3, 291(%r8,%rax,4)
+
+// CHECK: tilestored %tmm3, -32(,%rbp,2)
+// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tilestored %tmm3, -32(,%rbp,2)
+
+// CHECK: tilezero %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero %tmm6
+
+// CHECK: tilezero %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero %tmm3

llvm/test/MC/X86/AMX/x86-64-amx-tile-intel.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilezero tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero tmm6
+
+// CHECK: tilezero tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero tmm3
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilezero tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero tmm6
+
+// CHECK: tilezero tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero tmm3
+
+// CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          ldtilecfg [rbp + 8*r14 + 268435456]
+
+// CHECK: ldtilecfg [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          ldtilecfg [r8 + 4*rax + 291]
+
+// CHECK: ldtilecfg [rip]
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
+          ldtilecfg [rip]
+
+// CHECK: ldtilecfg [2*rbp - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          ldtilecfg [2*rbp - 2048]
+
+// CHECK: sttilecfg [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          sttilecfg [rbp + 8*r14 + 268435456]
+
+// CHECK: sttilecfg [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          sttilecfg [r8 + 4*rax + 291]
+
+// CHECK: sttilecfg [rip]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
+          sttilecfg [rip]
+
+// CHECK: sttilecfg [2*rbp - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          sttilecfg [2*rbp - 2048]
+
+// CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloadd tmm6, [rbp + 8*r14 + 268435456]
+
+// CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloadd tmm3, [r8 + 4*rax + 291]
+
+// CHECK: tileloadd tmm3, [2*rbp - 32]
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloadd tmm3, [2*rbp - 32]
+
+// CHECK: tileloadd tmm4, [rbx + 64]
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40]
+          tileloadd tmm4, [rbx + 64]
+
+// CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+
+// CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloaddt1 tmm3, [r8 + 4*rax + 291]
+
+// CHECK: tileloaddt1 tmm3, [2*rbp - 32]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloaddt1 tmm3, [2*rbp - 32]
+
+// CHECK: tileloaddt1     tmm6, [rbp + 16]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10]
+          tileloaddt1     tmm6, [rbp + 16]
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
+// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tilestored [rbp + 8*r14 + 268435456], tmm6
+
+// CHECK: tilestored [r8 + 4*rax + 291], tmm3
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tilestored [r8 + 4*rax + 291], tmm3
+
+// CHECK: tilestored [2*rbp - 32], tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tilestored [2*rbp - 32], tmm3
+
+// CHECK: tilestored [r8], tmm3
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x1c,0x20]
+          tilestored [r8], tmm3
+
+// CHECK: tilezero tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero tmm6
+
+// CHECK: tilezero tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero tmm3
+
+// CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          ldtilecfg [rbp + 8*r14 + 268435456]
+
+// CHECK: ldtilecfg [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          ldtilecfg [r8 + 4*rax + 291]
+
+// CHECK: ldtilecfg [rip]
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
+          ldtilecfg [rip]
+
+// CHECK: ldtilecfg [2*rbp - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          ldtilecfg [2*rbp - 2048]
+
+// CHECK: sttilecfg [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
+          sttilecfg [rbp + 8*r14 + 268435456]
+
+// CHECK: sttilecfg [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
+          sttilecfg [r8 + 4*rax + 291]
+
+// CHECK: sttilecfg [rip]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
+          sttilecfg [rip]
+
+// CHECK: sttilecfg [2*rbp - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
+          sttilecfg [2*rbp - 2048]
+
+// CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloadd tmm6, [rbp + 8*r14 + 268435456]
+
+// CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloadd tmm3, [r8 + 4*rax + 291]
+
+// CHECK: tileloadd tmm3, [2*rbp - 32]
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloadd tmm3, [2*rbp - 32]
+
+// CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
+
+// CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tileloaddt1 tmm3, [r8 + 4*rax + 291]
+
+// CHECK: tileloaddt1 tmm3, [2*rbp - 32]
+// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tileloaddt1 tmm3, [2*rbp - 32]
+
+// CHECK: tilerelease
+// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
+          tilerelease
+
+// CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
+// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
+          tilestored [rbp + 8*r14 + 268435456], tmm6
+
+// CHECK: tilestored [r8 + 4*rax + 291], tmm3
+// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
+          tilestored [r8 + 4*rax + 291], tmm3
+
+// CHECK: tilestored [2*rbp - 32], tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
+          tilestored [2*rbp - 32], tmm3
+
+// CHECK: tilezero tmm6
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
+          tilezero tmm6
+
+// CHECK: tilezero tmm3
+// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
+          tilezero tmm3

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

static const char *isInvalidMemoryInstr(const Instruction &Instr) {
   case X86II::AddCCFrm:
   case X86II::PrefixByte:
   case X86II::MRMDestReg:
   case X86II::MRMSrcReg:
   case X86II::MRMSrcReg4VOp3:
   case X86II::MRMSrcRegOp4:
   case X86II::MRMSrcRegCC:
   case X86II::MRMXrCC:
+  case X86II::MRMr0:
   case X86II::MRMXr:
   case X86II::MRM0r:
   case X86II::MRM1r:
   case X86II::MRM2r:
   case X86II::MRM3r:
   case X86II::MRM4r:
   case X86II::MRM5r:
   case X86II::MRM6r:

llvm/utils/TableGen/X86DisassemblerTables.cpp

 ///   be compacted by eliminating redundant information.
 ///
 /// @param decision - The decision to be compacted.
 /// @return         - The compactest available representation for the decision.
 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
   bool satisfiesOneEntry = true;
   bool satisfiesSplitRM = true;
   bool satisfiesSplitReg = true;
+  bool satisfiesSplitRegM = true;
   bool satisfiesSplitMisc = true;
 
   for (unsigned index = 0; index < 256; ++index) {
     if (decision.instructionIDs[index] != decision.instructionIDs[0])
       satisfiesOneEntry = false;
 
     if (((index & 0xc0) == 0xc0) &&
        (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
       satisfiesSplitRM = false;
 
     if (((index & 0xc0) != 0xc0) &&
        (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
       satisfiesSplitRM = false;
 
     if (((index & 0xc0) == 0xc0) &&
        (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
       satisfiesSplitReg = false;
 
     if (((index & 0xc0) != 0xc0) &&
        (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
       satisfiesSplitMisc = false;
+
+    if (((index & 0xc0) == 0xc0) &&
+       (decision.instructionIDs[index] != decision.instructionIDs[index&0xc7]))
+      satisfiesSplitRegM = false;
   }
 
   if (satisfiesOneEntry)
     return MODRM_ONEENTRY;
 
   if (satisfiesSplitRM)
     return MODRM_SPLITRM;
 
   if (satisfiesSplitReg && satisfiesSplitMisc)
     return MODRM_SPLITREG;
 
+  if (satisfiesSplitRegM)
+    return MODRM_SPLITREGM;
+
   if (satisfiesSplitMisc)
     return MODRM_SPLITMISC;
 
   return MODRM_FULL;
 }
 
 /// stringForDecisionType - Returns a statically-allocated string corresponding
 ///   to a particular decision type.
case MODRM_SPLITRM:
       ModRMDecision.push_back(decision.instructionIDs[0xc0]);
       break;
     case MODRM_SPLITREG:
       for (unsigned index = 0; index < 64; index += 8)
         ModRMDecision.push_back(decision.instructionIDs[index]);
       for (unsigned index = 0xc0; index < 256; index += 8)
         ModRMDecision.push_back(decision.instructionIDs[index]);
       break;
+    case MODRM_SPLITREGM:
+      for (unsigned index = 0xc0; index < 256; index += 8)
+        ModRMDecision.push_back(decision.instructionIDs[index]);
+      break;
     case MODRM_SPLITMISC:
       for (unsigned index = 0; index < 64; index += 8)
         ModRMDecision.push_back(decision.instructionIDs[index]);
       for (unsigned index = 0xc0; index < 256; ++index)
         ModRMDecision.push_back(decision.instructionIDs[index]);
       break;
     case MODRM_FULL:
       for (unsigned index = 0; index < 256; ++index)
case MODRM_ONEENTRY:
       sEntryNumber += 1;
       break;
     case MODRM_SPLITRM:
       sEntryNumber += 2;
       break;
     case MODRM_SPLITREG:
       sEntryNumber += 16;
       break;
+    case MODRM_SPLITREGM:
+      sEntryNumber += 8;
+      break;
     case MODRM_SPLITMISC:
       sEntryNumber += 8 + 64;
       break;
     case MODRM_FULL:
       sEntryNumber += 256;
       break;
   }
 

llvm/utils/TableGen/X86ModRMFilters.h

public:
 
   bool accepts(uint8_t modRM) const override {
     return (((R  && ((modRM & 0xc0) == 0xc0)) ||
              (!R && ((modRM & 0xc0) != 0xc0))) &&
             (((modRM & 0x38) >> 3) == NNN));
   }
 };
 
+/// ExtendedRMFilter - Extended opcodes are classified based on the value of the
+///   mod field [bits 7-6] and the value of the nnn field [bits 2-0].
+class ExtendedRMFilter : public ModRMFilter {
+  void anchor() override;
+  bool R;
+  uint8_t NNN;
+public:
+  /// Constructor
+  ///
+  /// \param r   True if the mod field must be set to 11; false otherwise.
+  ///            The name is explained at ModFilter.
+  /// \param nnn The required value of the nnn field.
+  ExtendedRMFilter(bool r, uint8_t nnn) :
+    ModRMFilter(),
+    R(r),
+    NNN(nnn) {
+  }
+
+  bool accepts(uint8_t modRM) const override {
+    return ((R && ((modRM & 0xc0) == 0xc0)) &&
+            ((modRM & 0x7) == NNN));
+  }
+};
 /// ExactFilter - The occasional extended opcode (such as VMCALL or MONITOR)
 ///   requires the ModR/M byte to have a specific value.
 class ExactFilter : public ModRMFilter {
   void anchor() override;
   uint8_t ModRM;
 public:
   /// Constructor
   ///

llvm/utils/TableGen/X86ModRMFilters.cpp

 void ModRMFilter::anchor() { }
 
 void DumbFilter::anchor() { }
 
 void ModFilter::anchor() { }
 
 void ExtendedFilter::anchor() { }
 
+void ExtendedRMFilter::anchor() { }
+
 void ExactFilter::anchor() { }

llvm/utils/TableGen/X86RecognizableInstr.h

enum {
     AddRegFrm     = 2,
     RawFrmMemOffs = 3,
     RawFrmSrc     = 4,
     RawFrmDst     = 5,
     RawFrmDstSrc  = 6,
     RawFrmImm8    = 7,
     RawFrmImm16   = 8,
     AddCCFrm      = 9,
     PrefixByte    = 10,
+    MRMr0          = 21,
+    MRMSrcMemFSIB  = 22,
+    MRMDestMemFSIB = 23,
     MRMDestMem     = 24,
     MRMSrcMem      = 25,
     MRMSrcMem4VOp3 = 26,
     MRMSrcMemOp4   = 27,
     MRMSrcMemCC    = 28,
     MRMXmCC = 30, MRMXm = 31,
     MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35,
     MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39,

llvm/utils/TableGen/X86RecognizableInstr.cpp

InstructionContext RecognizableInstr::insnContext() const {
 
   return insnContext;
 }
 
 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
   // The scaling factor for AVX512 compressed displacement encoding is an
   // instruction attribute.  Adjust the ModRM encoding type to include the
   // scale for compressed displacement.
-  if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0)
+  if ((encoding != ENCODING_RM &&
+       encoding != ENCODING_VSIB &&
+       encoding != ENCODING_SIB) ||CD8_Scale == 0)
     return;
   encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
   assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
+          (encoding == ENCODING_SIB) ||
           (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
          "Invalid CDisp scaling");
 }
 
 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
                                       unsigned &physicalOperandIndex,
                                       unsigned numPhysicalOperands,
                                       const unsigned *operandMapping,
if (HasVEX_4V)
       // FIXME: In AVX, the register below becomes the one encoded
       // in ModRMVEX and the one above the one in the VEX.VVVV field
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(roRegister)
     HANDLE_OPTIONAL(immediate)
     break;
   case X86Local::MRMDestMem:
+  case X86Local::MRMDestMemFSIB:
     // Operand 1 is a memory operand (possibly SIB-extended)
     // Operand 2 is a register operand in the Reg/Opcode field.
     // - In AVX, there is a register operand in the VEX.vvvv field here -
     // Operand 3 (optional) is an immediate.
     assert(numPhysicalOperands >= 2 + additionalOperands &&
            numPhysicalOperands <= 3 + additionalOperands &&
            "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
 
#endif
   case X86Local::MRMSrcRegCC:
     assert(numPhysicalOperands == 3 &&
            "Unexpected number of operands for MRMSrcRegCC");
     HANDLE_OPERAND(roRegister)
     HANDLE_OPERAND(rmRegister)
     HANDLE_OPERAND(opcodeModifier)
     break;
   case X86Local::MRMSrcMem:
+  case X86Local::MRMSrcMemFSIB:
     // Operand 1 is a register operand in the Reg/Opcode field.
     // Operand 2 is a memory operand (possibly SIB-extended)
     // - In AVX, there is a register operand in the VEX.vvvv field here -
     // Operand 3 (optional) is an immediate.
 
     assert(numPhysicalOperands >= 2 + additionalOperands &&
            numPhysicalOperands <= 4 + additionalOperands &&
            "Unexpected number of operands for MRMSrcMemFrm");
case X86Local::MRMSrcMemCC:
     HANDLE_OPERAND(opcodeModifier)
     break;
   case X86Local::MRMXrCC:
     assert(numPhysicalOperands == 2 &&
            "Unexpected number of operands for MRMXrCC");
     HANDLE_OPERAND(rmRegister)
     HANDLE_OPERAND(opcodeModifier)
     break;
+  case X86Local::MRMr0:
+    // Operand 1 is a register operand in the R/M field.
+    HANDLE_OPERAND(roRegister)
+    break;
   case X86Local::MRMXr:
   case X86Local::MRM0r:
   case X86Local::MRM1r:
   case X86Local::MRM2r:
   case X86Local::MRM3r:
   case X86Local::MRM4r:
   case X86Local::MRM5r:
   case X86Local::MRM6r:
#define MAP(from, to)                     \
   case X86Local::MRMSrcReg4VOp3:
   case X86Local::MRMSrcRegOp4:
   case X86Local::MRMSrcRegCC:
   case X86Local::MRMXrCC:
   case X86Local::MRMXr:
     filter = std::make_unique<ModFilter>(true);
     break;
   case X86Local::MRMDestMem:
+  case X86Local::MRMDestMemFSIB:
   case X86Local::MRMSrcMem:
+  case X86Local::MRMSrcMemFSIB:
   case X86Local::MRMSrcMem4VOp3:
   case X86Local::MRMSrcMemOp4:
   case X86Local::MRMSrcMemCC:
   case X86Local::MRMXmCC:
   case X86Local::MRMXm:
     filter = std::make_unique<ModFilter>(false);
     break;
   case X86Local::MRM0r: case X86Local::MRM1r:
   case X86Local::MRM2r: case X86Local::MRM3r:
   case X86Local::MRM4r: case X86Local::MRM5r:
   case X86Local::MRM6r: case X86Local::MRM7r:
     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
     break;
   case X86Local::MRM0X: case X86Local::MRM1X:
   case X86Local::MRM2X: case X86Local::MRM3X:
   case X86Local::MRM4X: case X86Local::MRM5X:
   case X86Local::MRM6X: case X86Local::MRM7X:
     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
     break;
+  case X86Local::MRMr0:
+    filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
+    break;
   case X86Local::MRM0m: case X86Local::MRM1m:
   case X86Local::MRM2m: case X86Local::MRM3m:
   case X86Local::MRM4m: case X86Local::MRM5m:
   case X86Local::MRM6m: case X86Local::MRM7m:
     filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
     break;
   X86_INSTR_MRM_MAPPING
     filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
OperandType RecognizableInstr::typeFromString(const std::string &s,
   TYPE("brtarget8",           TYPE_REL)
   TYPE("f80mem",              TYPE_M)
   TYPE("lea64_32mem",         TYPE_M)
   TYPE("lea64mem",            TYPE_M)
   TYPE("VR64",                TYPE_MM64)
   TYPE("i64imm",              TYPE_IMM)
   TYPE("anymem",              TYPE_M)
   TYPE("opaquemem",           TYPE_M)
+  TYPE("sibmem",              TYPE_MSIB)
   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
   TYPE("srcidx8",             TYPE_SRCIDX)
   TYPE("srcidx16",            TYPE_SRCIDX)
   TYPE("srcidx32",            TYPE_SRCIDX)
   TYPE("srcidx64",            TYPE_SRCIDX)
   TYPE("dstidx8",             TYPE_DSTIDX)
OperandType RecognizableInstr::typeFromString(const std::string &s,
   TYPE("vx128xmem",           TYPE_MVSIBX)
   TYPE("vx256xmem",           TYPE_MVSIBX)
   TYPE("vy128xmem",           TYPE_MVSIBY)
   TYPE("vy256xmem",           TYPE_MVSIBY)
   TYPE("vy512xmem",           TYPE_MVSIBY)
   TYPE("vz256mem",            TYPE_MVSIBZ)
   TYPE("vz512mem",            TYPE_MVSIBZ)
   TYPE("BNDR",                TYPE_BNDR)
+  TYPE("TILE",                TYPE_TMM)
   errs() << "Unhandled type string " << s << "\n";
   llvm_unreachable("Unhandled type string");
 }
 #undef TYPE
 
 #define ENCODING(str, encoding) if (s == str) return encoding;
 OperandEncoding
 RecognizableInstr::immediateEncodingFromString(const std::string &s,
RecognizableInstr::immediateEncodingFromString(const std::string &s,
   ENCODING("FR128",           ENCODING_IB)
   ENCODING("VR128",           ENCODING_IB)
   ENCODING("VR256",           ENCODING_IB)
   ENCODING("FR32X",           ENCODING_IB)
   ENCODING("FR64X",           ENCODING_IB)
   ENCODING("VR128X",          ENCODING_IB)
   ENCODING("VR256X",          ENCODING_IB)
   ENCODING("VR512",           ENCODING_IB)
+  ENCODING("TILE",            ENCODING_IB)
   errs() << "Unhandled immediate encoding " << s << "\n";
   llvm_unreachable("Unhandled immediate encoding");
 }
 
 OperandEncoding
 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
                                                 uint8_t OpSize) {
   ENCODING("RST",             ENCODING_FP)
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
   ENCODING("VK32",            ENCODING_RM)
   ENCODING("VK64",            ENCODING_RM)
   ENCODING("VK1PAIR",         ENCODING_RM)
   ENCODING("VK2PAIR",         ENCODING_RM)
   ENCODING("VK4PAIR",         ENCODING_RM)
   ENCODING("VK8PAIR",         ENCODING_RM)
   ENCODING("VK16PAIR",        ENCODING_RM)
   ENCODING("BNDR",            ENCODING_RM)
+  ENCODING("TILE",            ENCODING_RM)
   errs() << "Unhandled R/M register encoding " << s << "\n";
   llvm_unreachable("Unhandled R/M register encoding");
 }
 
 OperandEncoding
 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
                                                 uint8_t OpSize) {
   ENCODING("GR16",            ENCODING_REG)
RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
   ENCODING("VK1WM",           ENCODING_REG)
   ENCODING("VK2WM",           ENCODING_REG)
   ENCODING("VK4WM",           ENCODING_REG)
   ENCODING("VK8WM",           ENCODING_REG)
   ENCODING("VK16WM",          ENCODING_REG)
   ENCODING("VK32WM",          ENCODING_REG)
   ENCODING("VK64WM",          ENCODING_REG)
   ENCODING("BNDR",            ENCODING_REG)
+  ENCODING("TILE",            ENCODING_REG)
   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
   llvm_unreachable("Unhandled reg/opcode register encoding");
 }
 
 OperandEncoding
 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
                                                   uint8_t OpSize) {
   ENCODING("GR32",            ENCODING_VVVV)
RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
   ENCODING("VK16",            ENCODING_VVVV)
   ENCODING("VK32",            ENCODING_VVVV)
   ENCODING("VK64",            ENCODING_VVVV)
   ENCODING("VK1PAIR",         ENCODING_VVVV)
   ENCODING("VK2PAIR",         ENCODING_VVVV)
   ENCODING("VK4PAIR",         ENCODING_VVVV)
   ENCODING("VK8PAIR",         ENCODING_VVVV)
   ENCODING("VK16PAIR",        ENCODING_VVVV)
+  ENCODING("TILE",            ENCODING_VVVV)
   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
   llvm_unreachable("Unhandled VEX.vvvv register encoding");
 }
 
 OperandEncoding
 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
                                                        uint8_t OpSize) {
   ENCODING("VK1WM",           ENCODING_WRITEMASK)
RecognizableInstr::memoryEncodingFromString(const std::string &s,
   ENCODING("i128mem",         ENCODING_RM)
   ENCODING("i256mem",         ENCODING_RM)
   ENCODING("i512mem",         ENCODING_RM)
   ENCODING("f80mem",          ENCODING_RM)
   ENCODING("lea64_32mem",     ENCODING_RM)
   ENCODING("lea64mem",        ENCODING_RM)
   ENCODING("anymem",          ENCODING_RM)
   ENCODING("opaquemem",       ENCODING_RM)
+  ENCODING("sibmem",          ENCODING_SIB)
   ENCODING("vx64mem",         ENCODING_VSIB)
   ENCODING("vx128mem",        ENCODING_VSIB)
   ENCODING("vx256mem",        ENCODING_VSIB)
   ENCODING("vy128mem",        ENCODING_VSIB)
   ENCODING("vy256mem",        ENCODING_VSIB)
   ENCODING("vx64xmem",        ENCODING_VSIB)
   ENCODING("vx128xmem",       ENCODING_VSIB)
   ENCODING("vx256xmem",       ENCODING_VSIB)