[PowerPC][Power10] Implement Vector Permute Builtins in LLVM/Clang

[biplmish]

Summary

This patch implements builtins for the following prototypes:

vector unsigned char vec_insertl (unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_insertl (unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_insertl (unsigned int, vector unsigned int, unsigned int);
vector unsigned long long vec_insertl (unsigned long long, vector unsigned long long, unsigned int);
vector unsigned char vec_insertl (vector unsigned char, vector unsigned char, unsigned int;
vector unsigned short vec_insertl (vector unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_insertl (vector unsigned int, vector unsigned int, unsigned int);
vector unsigned char vec_inserth (unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_inserth (unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_inserth (unsigned int, vector unsigned int, unsigned int);
vector unsigned long long vec_inserth (unsigned long long, vector unsigned long long, unsigned int);
vector unsigned char vec_inserth (vector unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_inserth (vector unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_inserth (vector unsigned int, vector unsigned int, unsigned int);

vector signed int vec_replace_elt (vector signed int, signed int, const int);
vector unsigned int vec_replace_elt (vector unsigned int, unsigned int, const int);
vector float vec_replace_elt (vector float, float, const int);
vector signed long long vec_replace_elt (vector signed long long, signed long long, const int);
vector unsigned long long vec_replace_elt (vector unsigned long long, unsigned long long, const int);
vector double rec_replace_elt (vector double, double, const int);

vector unsigned char vec_replace_unaligned (vector unsigned char, signed int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned int, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, float, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, signed long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, unsigned long long, const int);
vector unsigned char vec_replace_unaligned (vector unsigned char, double, const int);

vector signed char vec_sldb (vector signed char, vector signed char, const unsigned int);
vector unsigned char vec_sldb (vector unsigned char, vector unsigned char, const unsigned int);
vector signed short vec_sldb (vector signed short, vector signed short, const unsigned int);
vector unsigned short vec_sldb (vector unsigned short, vector unsigned short, const unsigned int);
vector signed int vec_sldb (vector signed int, vector signed int, const unsigned int);
vector unsigned int vec_sldb (vectoextracthr unsigned int, vector unsigned int, const unsigned int);
vector signed long long vec_sldb (vector signed long long, vector signed long long, const unsigned int);
vector unsigned long long vec_sldb (vector unsigned long long, vector unsigned long long, const unsigned int);
vector signed char vec_srdb (vector signed char, vector signed char, const unsigned int);
vector unsigned char vec_srdb (vector unsigned char, vector unsigned char, const unsigned int);
vector signed short vec_srdb (vector signed short, vector signed short, const unsigned int);
vector unsigned short vec_srdb (vector unsigned short, vector unsigned short, const unsigned int);
vector signed int vec_srdb (vector signed int, vector signed int, const unsigned int);
vector unsigned int vec_srdb (vector unsigned int, vector unsigned int, const unsigned int);
vector signed long long vec_srdb (vector signed long long, vector signed long long, const unsigned int);extracth
vector unsigned long long vec_srdb (vector unsigned long long, vector unsigned long long, const unsigned int);

vector signed int vec_splati (const signed int);
vector float vec_splati (const float);

vector double vec_splatid (const float);

vector signed int vec_splati_ins (vector signed int, const unsigned int, const signed int);
vector unsigned int vec_splati_ins (vector unsigned int, const unsigned int, const unsigned int);
vector float vec_splati_ins (vector float, const unsigned int, const float);

vector signed char vec_blendv (vector signed char, vector signed char, vector unsigned char);
vector unsigned char vec_blendv (vector unsigned char, vector unsigned char, vector unsigned char);
vector signed short vec_blendv (vector signed short, vector signed short, vector unsigned short);
vector unsigned short vec_blendv (vector unsigned short, vector unsigned short, vector unsigned short);
vector signed int vec_blendv (vector signed int, vector signed int, vector unsigned int);
vector unsigned int vec_blendv (vector unsigned int, vector unsigned int, vector unsigned int);
vector signed long long vec_blendv (vector signed long long, vector signed long long, vector unsigned long long);
vector unsigned long long vec_blendv (vector unsigned long long, vector unsigned long long, vector unsigned long long);
vector float vec_blendv (vector float, vector float, vector unsigned int);
vector double vec_blendv (vector double, vector double, vector unsigned long long);

vector signed char vec_permx (vector signed char, vector signed char, vector unsigned char, const int);
vector unsigned char vec_permx (vector unsigned char, vector unsigned char, vector unsigned char, const int);
vector signed short vec_permx (vector signed short, vector signed short, vector unsigned char, const int);
vector unsigned short vec_permx (vector unsigned short, vector unsigned short, vector unsigned char, const int);
vector signed int vec_permx (vector signed int, vector signed int, vector unsigned char, const int);
vector unsigned int vec_permx (vector unsigned int, vector unsigned int, vector unsigned char, const int);
vector signed long long vec_permx (vector signed long long, vector signed long long, vector unsigned char, const int);
vector unsigned long long vec_permx (vector unsigned long long, vector unsigned long long, vector unsigned char, const int);
vector float vec_permx (vector float, vector float, vector unsigned char, const int);
vector double vec_permx (vector double, vector double, vector unsigned char, const int);

Depends on D80758

[steven.zhang]

This is a huge patch. I suggest you to split them into small ones for each kind of builtins, so that, it would be more easy to review.

[lei]

This is PR still valid? I see dup def in https://reviews.llvm.org/D82365.

[biplmish]

This comment was removed by biplmish.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "")
 BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
 BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
 BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
 
+// P10 Vector Permute Extended built-in.
+BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")
+
 // Float 128 built-ins
 BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
 BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
 BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")

clang/lib/Headers/altivec.h

 
 /* vec_cnttzm */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_cnttzm(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vctzdm(__a, __b);
 }
 
+#ifdef __VSX__
+
+/* vec_permx */
+
+#define vec_permx(__a, __b, __c, __d)                                          \
+  _Generic((__a), vector signed char                                           \
+           : (vector signed char)__builtin_vsx_xxpermx(                        \
+                 (vector signed char)(__a), (__b), (__c), (__d)),              \
+             vector unsigned char                                              \
+           : (vector unsigned char)__builtin_vsx_xxpermx(                      \
+                 (vector unsigned char)(__a), (__b), (__c), (__d)),            \
+             vector signed short                                               \
+           : (vector signed short)__builtin_vsx_xxpermx(                       \
+                 (vector signed short)(__a), (__b), (__c), (__d)),             \
+             vector unsigned short                                             \
+           : (vector unsigned short)__builtin_vsx_xxpermx(                     \
+                 (vector unsigned short)(__a), (__b), (__c), (__d)),           \
+             vector signed int                                                 \
+           : (vector signed int)__builtin_vsx_xxpermx(                         \
+                 (vector signed int)(__a), (__b), (__c), (__d)),               \
+             vector unsigned int                                               \
+           : (vector unsigned int)__builtin_vsx_xxpermx(                       \
+                 (vector unsigned int)(__a), (__b), (__c), (__d)),             \
+             vector signed long long                                           \
+           : (vector signed long long)__builtin_vsx_xxpermx(                   \
+                 (vector signed long long)(__a), (__b), (__c), (__d)),         \
+             vector unsigned long long                                         \
+           : (vector unsigned long long)__builtin_vsx_xxpermx(                 \
+                 (vector unsigned long long)(__a), (__b), (__c), (__d)),       \
+             vector float                                                      \
+           : (vector float)__builtin_vsx_xxpermx((vector float)(__a), (__b),   \
+                                                 (__c), (__d)),                \
+             vector double                                                     \
+           : (vector double)__builtin_vsx_xxpermx((vector double)(__a), (__b), \
+                                                  (__c), (__d)))
+#endif /* __VSX__ */
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

clang/lib/Sema/SemaChecking.cpp

case PPC::BI__builtin_unpack_vector_int128:
     return SemaVSXCheck(TheCall) ||
            SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_pack_vector_int128:
     return SemaVSXCheck(TheCall);
   case PPC::BI__builtin_altivec_vgnb:
      return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_vsx_xxeval:
      return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
+  case PPC::BI__builtin_vsx_xxpermx:
+     return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 
 bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
                                           CallExpr *TheCall) {
   // position of memory order and scope arguments in the builtin
   unsigned OrderIndex, ScopeIndex;

clang/test/CodeGen/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s
 
 #include <altivec.h>
 
-vector signed char vsca;
+vector signed char vsca, vscb;
 vector unsigned char vuca, vucb, vucc;
+vector signed short vssa, vssb;
 vector unsigned short vusa, vusb, vusc;
+vector signed int vsia, vsib;
 vector unsigned int vuia, vuib, vuic;
+vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
 vector unsigned __int128 vui128a, vui128b, vui128c;
+vector float vfa, vfb;
+vector double vda, vdb;
 unsigned int uia;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
vector unsigned long long test_vclzdm(void) {
   return vec_cntlzm(vulla, vullb);
 }
 
 vector unsigned long long test_vctzdm(void) {
   // CHECK: @llvm.ppc.altivec.vctzdm(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_cnttzm(vulla, vullb);
 }
+
+vector signed char test_vec_permx_sc(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_permx(vsca, vscb, vucc, 0);
+}
+
+vector unsigned char test_vec_permx_uc(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_permx(vuca, vucb, vucc, 1);
+}
+
+vector signed short test_vec_permx_ss(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+  // CHECK-NEXT: ret <8 x i16>
+  return vec_permx(vssa, vssb, vucc, 2);
+}
+
+vector unsigned short test_vec_permx_us(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+  // CHECK-NEXT: ret <8 x i16>
+  return vec_permx(vusa, vusb, vucc, 3);
+}
+
+vector signed int test_vec_permx_si(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_permx(vsia, vsib, vucc, 4);
+}
+
+vector unsigned int test_vec_permx_ui(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_permx(vuia, vuib, vucc, 5);
+}
+
+vector signed long long test_vec_permx_sll(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_permx(vslla, vsllb, vucc, 6);
+}
+
+vector unsigned long long test_vec_permx_ull(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_permx(vulla, vullb, vucc, 7);
+}
+
+vector float test_vec_permx_f(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x float>
+  // CHECK-NEXT: ret <4 x float>
+  return vec_permx(vfa, vfb, vucc, 0);
+}
+
+vector double test_vec_permx_d(void) {
+  // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <2 x double>
+  // CHECK-NEXT: ret <2 x double>
+  return vec_permx(vda, vdb, vucc, 1);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xxgenpcvhm :
       PowerPC_VSX_Intrinsic<"xxgenpcvhm", [llvm_v8i16_ty],
                             [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxgenpcvwm :
       PowerPC_VSX_Intrinsic<"xxgenpcvwm", [llvm_v4i32_ty],
                             [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxgenpcvdm :
       PowerPC_VSX_Intrinsic<"xxgenpcvdm", [llvm_v2i64_ty],
                             [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
+// P10 VSX Vector permute extended.
+def  int_ppc_vsx_xxpermx: GCCBuiltin<"__builtin_vsx_xxpermx">,
+             Intrinsic<[llvm_v16i8_ty],
+                       [llvm_v16i8_ty,llvm_v16i8_ty,llvm_v16i8_ty,llvm_i32_ty],
+                       [IntrNoMem, ImmArg<ArgIndex<3>>]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
   def XXBLENDVD :
     8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
 }
 
+let Predicates = [PrefixInstrs] in {
+  def : Pat<(v16i8 
+            (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C , timm:$D)),
+            (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
+            (COPY_TO_REGCLASS $B, VSRC), (COPY_TO_REGCLASS $C, VSRC), $D),
+            VSRC)>;
+}
+
 let Predicates = [IsISA3_1] in {
   def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
                                 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
                                 "vsldbi $VRT, $VRA, $VRB, $SH",
                                 IIC_VecGeneral, []>;
   def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
                                 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
                                 "vsrdbi $VRT, $VRA, $VRB, $SH",

llvm/test/CodeGen/PowerPC/p10-permute-ops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
+define <16 x i8> @testXXPERMX(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: testXXPERMX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxpermx v2, v2, v3, v4, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
+  ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)