[PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

[amyk]

Summary

This patch implements builtins for the following prototypes:

vector unsigned long long vec_pdep(vector unsigned long long, vector unsigned long long);
vector unsigned long long vec_pext(vector unsigned long long, vector unsigned long long __b);
unsigned long long __builtin_pdepd (unsigned long long, unsigned long long);
unsigned long long __builtin_pextd (unsigned long long, unsigned long long);

Depends on D80758 

[amyk]

Updated a typo within the comment in llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll.

[amyk]

Ping.

[lei]

LGTM, just 1 minor comment/question.

llvm/lib/Target/PowerPC/PPCScheduleP9.td

47

Are PrefixInstrs and PCRelativeMemops not part of IsISA3_1?

[amyk]

llvm/lib/Target/PowerPC/PPCScheduleP9.td

47

Currently they are not. I believe those will need to be updated in the future to be apart of IsISA3_1.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "")
 
 // P9 Vector rotate built-ins
 BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 
+// P10 Vector Parallel Bits built-ins.
+BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
 BUILTIN(__builtin_vsx_lxvw4x, "V4iivC*", "")
 BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "")
 BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_stxvd2x, "vV2div*", "")

 BUILTIN(__builtin_ttest, "LUi", "")
 
 // Scalar built-ins
 BUILTIN(__builtin_divwe, "SiSiSi", "")
 BUILTIN(__builtin_divweu, "UiUiUi", "")
 BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "")
 BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
 BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
+BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
+BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
 
 // Vector int128 (un)pack
 BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "")
 BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "")
 
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
 // Cache built-ins
 BUILTIN(__builtin_dcbf, "vvC*", "")
 
 // FIXME: Obviously incomplete.
 
 #undef BUILTIN

clang/lib/Headers/altivec.h

 
 static vector signed short __ATTRS_o_ai vec_nabs(vector signed short __a) {
   return __builtin_altivec_vminsh(__a, -__a);
 }
 
 static vector signed char __ATTRS_o_ai vec_nabs(vector signed char __a) {
   return __builtin_altivec_vminsb(__a, -__a);
 }
+
+#ifdef __POWER10_VECTOR__
+/* vec_pdep */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_pdep(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vpdepd(__a, __b);
+}
+
+/* vec_pext */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_pext(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vpextd(__a, __b);
+}
+#endif /* __POWER10_VECTOR__ */
+
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

clang/test/CodeGen/builtins-ppc-p10.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+unsigned long long ulla, ullb;
+
+unsigned long long test_pdepd(void) {
+  // CHECK: @llvm.ppc.pdepd
+  return __builtin_pdepd(ulla, ullb);
+}
+
+unsigned long long test_pextd(void) {
+  // CHECK: @llvm.ppc.pextd
+  return __builtin_pextd(ulla, ullb);
+}

clang/test/CodeGen/builtins-ppc-p10vector.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
+
+#include <altivec.h>
+
+vector unsigned long long vulla, vullb;
+
+vector unsigned long long test_vpdepd(void) {
+  // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_pdep(vulla, vullb);
+}
+
+vector unsigned long long test_vpextd(void) {
+  // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_pext(vulla, vullb);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_divdeu : GCCBuiltin<"__builtin_divdeu">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
   // Bit permute doubleword
   def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
+  // Parallel Bits Deposit/Extract Doubleword Builtins.
+  def int_ppc_pdepd
+      : GCCBuiltin<"__builtin_pdepd">,
+        Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_pextd
+      : GCCBuiltin<"__builtin_pextd">,
+        Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+
   def int_ppc_truncf128_round_to_odd
       : GCCBuiltin<"__builtin_truncf128_round_to_odd">,
         Intrinsic <[llvm_double_ty], [llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_sqrtf128_round_to_odd
       : GCCBuiltin<"__builtin_sqrtf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_addf128_round_to_odd
       : GCCBuiltin<"__builtin_addf128_round_to_odd">,
def int_ppc_altivec_vctzlsbb : GCCBuiltin<"__builtin_altivec_vctzlsbb">,
               Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
   def int_ppc_altivec_vprtybw : GCCBuiltin<"__builtin_altivec_vprtybw">,
               Intrinsic<[llvm_v4i32_ty],[llvm_v4i32_ty],[IntrNoMem]>;
   def int_ppc_altivec_vprtybd : GCCBuiltin<"__builtin_altivec_vprtybd">,
               Intrinsic<[llvm_v2i64_ty],[llvm_v2i64_ty],[IntrNoMem]>;
   def int_ppc_altivec_vprtybq : GCCBuiltin<"__builtin_altivec_vprtybq">,
               Intrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
 
+  // P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
+  def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                        [IntrNoMem]>;
 }
 
 // Vector average.
 def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">;
 def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">;
 def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">;
 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
   def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
                                       !strconcat(asmstr, ", 0"), itin, []>;
   def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
                                     !strconcat(asmstr, ", 1"), itin, []>,
                                     isPCRel;
 }
 
 def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
+def IsISA3_1 : Predicate<"PPCSubTarget->isISA3_1()">;
 
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm:$SI),
                               "paddi $RT, $RA, $SI", IIC_LdStLFD>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def : Pat<(PPCstore_scal_int_from_vsr
               (PPCmatpcreladdr pcreladdr:$dst), 8),
             (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
 
   // If the PPCmatpcreladdr node is not caught by any other pattern it should be
   // caught here and turned into a paddi instruction to materialize the address.
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
+let Predicates = [IsISA3_1] in {
+   def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                         "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v2i64:$vD,
+                         (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
+   def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                         "vpextd $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v2i64:$vD,
+                         (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
+   def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
+                       "pdepd $rA, $rS, $rB", IIC_IntGeneral,
+                       [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>;
+   def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
+                       "pextd $rA, $rS, $rB", IIC_IntGeneral,
+                       [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
+}

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9Model : SchedMachineModel {
   // issue queue until all register sources and other dependencies have been
   // resolved and they can be issued. Each of four execution slices has an
   // 11-entry iop issue queue.
   let MicroOpBufferSize = 44;
 
   let CompleteModel = 1;
 
   // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
-  // Engine), prefixed instructions on Power 9 or PC relative mem ops.
-  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops];
+  // Engine), prefixed instructions on Power 9, PC relative mem ops, or
+  // instructions introduced in ISA 3.1.
+  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops,
+                             IsISA3_1];
 
 }
 
 let SchedModel = P9Model in {
 
   // ***************** Processor Resources *****************
 
   // Dispatcher slots:

llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aim to test the bit manipulation operations on Power10.
+
+declare <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
+declare i64 @llvm.ppc.pdepd(i64, i64)
+declare i64 @llvm.ppc.pextd(i64, i64)
+
+define <2 x i64> @test_vpdepd(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpdepd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpdepd v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %tmp
+}
+
+define <2 x i64> @test_vpextd(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vpextd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpextd v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %tmp
+}
+
+define i64 @test_pdepd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_pdepd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pdepd r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.pdepd(i64 %a, i64 %b)
+  ret i64 %tmp
+}
+
+define i64 @test_pextd(i64 %a, i64 %b) {
+; CHECK-LABEL: test_pextd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pextd r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
+  ret i64 %tmp
+}

llvm/test/MC/Disassembler/PowerPC/p10insts.txt

+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
+# RUN:   -mcpu=pwr10 | FileCheck %s
+
+# CHECK: vpdepd 1, 2, 0
+0x10 0x22 0x05 0xcd
+
+# CHECK: vpextd 1, 2, 0
+0x10 0x22 0x05 0x8d
+
+# CHECK: pdepd 1, 2, 4
+0x7c 0x41 0x21 0x38
+
+# CHECK: pextd 1, 2, 4
+0x7c 0x41 0x21 0x78

llvm/test/MC/PowerPC/p10.s

+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
+# RUN:   FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
+# RUN:   FileCheck -check-prefix=CHECK-LE %s
+
+# CHECK-BE: vpdepd 1, 2, 0                        # encoding: [0x10,0x22,0x05,0xcd]
+# CHECK-LE: vpdepd 1, 2, 0                        # encoding: [0xcd,0x05,0x22,0x10]
+            vpdepd 1, 2, 0
+# CHECK-BE: vpextd 1, 2, 0                        # encoding: [0x10,0x22,0x05,0x8d]
+# CHECK-LE: vpextd 1, 2, 0                        # encoding: [0x8d,0x05,0x22,0x10]
+            vpextd 1, 2, 0
+# CHECK-BE: pdepd 1, 2, 4                         # encoding: [0x7c,0x41,0x21,0x38]
+# CHECK-LE: pdepd 1, 2, 4                         # encoding: [0x38,0x21,0x41,0x7c]
+            pdepd 1, 2, 4
+# CHECK-BE: pextd 1, 2, 4                         # encoding: [0x7c,0x41,0x21,0x78]
+# CHECK-LE: pextd 1, 2, 4                         # encoding: [0x78,0x21,0x41,0x7c]
+            pextd 1, 2, 4