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[PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang
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Authored by amyk on Jun 1 2020, 9:16 AM.

Details

Summary

This patch implements builtins for the following prototypes:

vector unsigned long long vec_pdep(vector unsigned long long, vector unsigned long long);
vector unsigned long long vec_pext(vector unsigned long long, vector unsigned long long __b);
unsigned long long __builtin_pdepd (unsigned long long, unsigned long long);
unsigned long long __builtin_pextd (unsigned long long, unsigned long long);

Depends on D80758 

Diff Detail

Event Timeline

amyk created this revision.Jun 1 2020, 9:16 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJun 1 2020, 9:16 AM
amyk updated this revision to Diff 267648.Jun 1 2020, 9:31 AM

Updated a typo within the comment in llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll.

jsji added a reviewer: Restricted Project.Jun 1 2020, 10:54 AM
jsji added a project: Restricted Project.
lei accepted this revision as: lei.Jun 15 2020, 12:31 PM

LGTM, just 1 minor comment/question.

llvm/lib/Target/PowerPC/PPCScheduleP9.td
47

Are PrefixInstrs and PCRelativeMemops not part of IsISA3_1?

This revision is now accepted and ready to land.Jun 15 2020, 12:31 PM
amyk marked an inline comment as done.Jun 18 2020, 11:06 AM
amyk added inline comments.
llvm/lib/Target/PowerPC/PPCScheduleP9.td
47

Currently they are not. I believe those will need to be updated in the future to be apart of IsISA3_1.

This revision was automatically updated to reflect the committed changes.