Add support for vmsumudm

[saghir]

Summary

This patch adds support for Vector Multiply-Sum Unsigned Doubleword Modulo instruction; vmsumudm.
This instruction is available on POWER 9.

[saghir]

Added vec_msum builtin for vmsumudm.

[saghir]

Removing the builtin support.

[amyk]

I think this overall looks good, but just curious, why was the builtin support removed?

[saghir]

In D80294#2048049, @amyk wrote:

I think this overall looks good, but just curious, why was the builtin support removed?

I was hitting some errors with that, so removed it and would add that later on.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1365

Maybe we can put this definition near the other VMSUM instructions? Since it's also nearby them in BuiltinsPPC.def and IntrinsicsPowerPC.td.

[saghir]

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

1365

This needed to be in the block for Power9 Altivec instructions, the other vmsum instructions are outside the P9 block.

[nemanjai]

LGTM.

[amyk]

Thanks for explaining. This LGTM.

clang/include/clang/Basic/BuiltinsPPC.def

 
 BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "")
 BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "")
 BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "")
 
 BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "")
 BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "")
+BUILTIN(__builtin_altivec_vmsumudm, "V1ULLLiV2ULLV2ULLV1ULLLi", "")
 BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "")
 BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "")
 BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "")
 
 BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "")
 BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "")

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
                        llvm_v4i32_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
                        llvm_v4i32_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
                        llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vmsumudm : GCCBuiltin<"__builtin_altivec_vmsumudm">,
+            Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
+                       llvm_v1i128_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
             Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
                        llvm_v4i32_ty], [IntrNoMem]>;
 
   // Vector Multiply Instructions.
   def int_ppc_altivec_vmulesb : GCCBuiltin<"__builtin_altivec_vmulesb">,
           Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
                     [IntrNoMem]>;

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
     VCFUX_0,
     VMHRADDSHS,
     VMLADDUHM,
     VMSUMMBM,
     VMSUMSHM,
     VMSUMSHS,
     VMSUMUBM,
     VMSUMUHM,
+    VMSUMUDM,
     VMSUMUHS,
     VMULESB,
     VMULESH,
     VMULESW,
     VMULEUB,
     VMULEUH,
     VMULEUW,
     VMULOSB,

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
                               int_ppc_altivec_crypto_vncipherlast, v2i64>;
 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
 } // HasP8Crypto
 
 // The following altivec instructions were introduced in Power ISA 3.0
 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
 let Predicates = [HasP9Altivec] in {
 
+// Vector Multiply-Sum
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
+                            v1i128, v2i64, v1i128>;
+
 // i8 element comparisons.
 def VCMPNEB   : VCMP   <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
 def VCMPNEB_rec  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
 def VCMPNEZB  : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
 def VCMPNEZB_rec : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
 def VCMPNEH   : VCMP < 71, "vcmpneh $vD, $vA, $vB"  , v8i16>;

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x43 0x21 0x68
 
 # CHECK: vmsumshs 2, 3, 4, 5             
 0x10 0x43 0x21 0x69
 
 # CHECK: vmsumuhm 2, 3, 4, 5             
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5             
 0x10 0x43 0x21 0x67
 
 # CHECK: vsumsws 2, 3, 4                 
 0x10 0x43 0x27 0x88
 
 # CHECK: vsum2sws 2, 3, 4                
 0x10 0x43 0x26 0x88

llvm/test/MC/PowerPC/ppc64-encoding-vmx.s

 # CHECK-LE: vmsumshm 2, 3, 4, 5             # encoding: [0x68,0x21,0x43,0x10]
             vmsumshm 2, 3, 4, 5
 # CHECK-BE: vmsumshs 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x69]
 # CHECK-LE: vmsumshs 2, 3, 4, 5             # encoding: [0x69,0x21,0x43,0x10]
             vmsumshs 2, 3, 4, 5
 # CHECK-BE: vmsumuhm 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5             # encoding: [0x66,0x21,0x43,0x10]
             vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5             # encoding: [0x63,0x21,0x43,0x10]
+            vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5             # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5             # encoding: [0x67,0x21,0x43,0x10]
             vmsumuhs 2, 3, 4, 5
 
 # CHECK-BE: vsumsws 2, 3, 4                 # encoding: [0x10,0x43,0x27,0x88]
 # CHECK-LE: vsumsws 2, 3, 4                 # encoding: [0x88,0x27,0x43,0x10]
             vsumsws 2, 3, 4
 # CHECK-BE: vsum2sws 2, 3, 4                # encoding: [0x10,0x43,0x26,0x88]