[SVE] Remove usages of VectorType::getNumElements() from AMDGPU

[efriedma]

llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

1129

Unnecessary "const".

[ctetreau]

llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

1129

It was there before and it's not hurting anything. I can remove it if you really want me to.

[ctetreau]

catch straggler

[ctetreau]

remove accidentally added ARM changes

[efriedma]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

unsigned AMDGPUCodeGenPrepare::getBaseElementBitWidth(const Type *T) const {
   return cast<VectorType>(T)->getElementType()->getIntegerBitWidth();
 }
 
 Type *AMDGPUCodeGenPrepare::getI32Ty(IRBuilder<> &B, const Type *T) const {
   assert(needsPromotionToI32(T) && "T does not need promotion to i32");
 
   if (T->isIntegerTy())
     return B.getInt32Ty();
-  return VectorType::get(B.getInt32Ty(), cast<VectorType>(T)->getNumElements());
+  return FixedVectorType::get(B.getInt32Ty(), cast<FixedVectorType>(T));
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
   return I.getOpcode() == Instruction::AShr ||
       I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
 }
 
 bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {

 }
 
 bool AMDGPUCodeGenPrepare::isU24(Value *V, unsigned ScalarSize) const {
   return numBitsUnsigned(V, ScalarSize) <= 24;
 }
 
 static void extractValues(IRBuilder<> &Builder,
                           SmallVectorImpl<Value *> &Values, Value *V) {
-  VectorType *VT = dyn_cast<VectorType>(V->getType());
+  auto *VT = dyn_cast<FixedVectorType>(V->getType());
   if (!VT) {
     Values.push_back(V);
     return;
   }
 
   for (int I = 0, E = VT->getNumElements(); I != E; ++I)
     Values.push_back(Builder.CreateExtractElement(V, I));
 }
bool AMDGPUCodeGenPrepare::visitFDiv(BinaryOperator &FDiv) {
   IRBuilder<> Builder(FDiv.getParent(), std::next(FDiv.getIterator()));
   Builder.setFastMathFlags(FMF);
   Builder.SetCurrentDebugLocation(FDiv.getDebugLoc());
 
   Value *Num = FDiv.getOperand(0);
   Value *Den = FDiv.getOperand(1);
 
   Value *NewFDiv = nullptr;
-  if (VectorType *VT = dyn_cast<VectorType>(FDiv.getType())) {
+  if (auto *VT = dyn_cast<FixedVectorType>(FDiv.getType())) {
     NewFDiv = UndefValue::get(VT);
 
     // FIXME: Doesn't do the right thing for cases where the vector is partially
     // constant. This works when the scalarizer pass is run first.
     for (unsigned I = 0, E = VT->getNumElements(); I != E; ++I) {
       Value *NumEltI = Builder.CreateExtractElement(Num, I);
       Value *DenEltI = Builder.CreateExtractElement(Den, I);
       // Try rcp first.
if ((Opc == Instruction::URem || Opc == Instruction::UDiv ||
        Opc == Instruction::SRem || Opc == Instruction::SDiv) &&
       ScalarSize <= 64 &&
       !DisableIDivExpand) {
     Value *Num = I.getOperand(0);
     Value *Den = I.getOperand(1);
     IRBuilder<> Builder(&I);
     Builder.SetCurrentDebugLocation(I.getDebugLoc());
 
-    if (VectorType *VT = dyn_cast<VectorType>(Ty)) {
+    if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
       NewDiv = UndefValue::get(VT);
 
       for (unsigned N = 0, E = VT->getNumElements(); N != E; ++N) {
         Value *NumEltN = Builder.CreateExtractElement(Num, N);
         Value *DenEltN = Builder.CreateExtractElement(Den, N);
 
         Value *NewElt;
         if (ScalarSize <= 32) {

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

std::string MetadataStreamerV2::getTypeName(Type *Ty, bool Signed) const {
   }
   case Type::HalfTyID:
     return "half";
   case Type::FloatTyID:
     return "float";
   case Type::DoubleTyID:
     return "double";
   case Type::FixedVectorTyID: {
-    auto VecTy = cast<VectorType>(Ty);
+    auto VecTy = cast<FixedVectorType>(Ty);
     auto ElTy = VecTy->getElementType();
     auto NumElements = VecTy->getNumElements();
     return (Twine(getTypeName(ElTy, Signed)) + Twine(NumElements)).str();
   }
   default:
     return "unknown";
   }
 }
std::string MetadataStreamerV3::getTypeName(Type *Ty, bool Signed) const {
   }
   case Type::HalfTyID:
     return "half";
   case Type::FloatTyID:
     return "float";
   case Type::DoubleTyID:
     return "double";
   case Type::FixedVectorTyID: {
-    auto VecTy = cast<VectorType>(Ty);
+    auto VecTy = cast<FixedVectorType>(Ty);
     auto ElTy = VecTy->getElementType();
     auto NumElements = VecTy->getNumElements();
     return (Twine(getTypeName(ElTy, Signed)) + Twine(NumElements)).str();
   }
   default:
     return "unknown";
   }
 }

llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B,
   nval = B.CreateFMul(opr1, nval, "__ylogx");
   nval = CreateCallEx(B,ExpExpr, nval, "__exp2");
 
   if (needcopysign) {
     Value *opr_n;
     Type* rTy = opr0->getType();
     Type* nTyS = eltType->isDoubleTy() ? B.getInt64Ty() : B.getInt32Ty();
     Type *nTy = nTyS;
-    if (const VectorType *vTy = dyn_cast<VectorType>(rTy))
-      nTy = VectorType::get(nTyS, vTy->getNumElements());
+    if (const auto *vTy = dyn_cast<FixedVectorType>(rTy))
+      nTy = FixedVectorType::get(nTyS, vTy);
     unsigned size = nTy->getScalarSizeInBits();
     opr_n = CI->getArgOperand(1);
     if (opr_n->getType()->isIntegerTy())
       opr_n = B.CreateZExtOrBitCast(opr_n, nTy, "__ytou");
     else
       opr_n = B.CreateFPToSI(opr1, nTy, "__ytou");
 
     Value *sign = B.CreateShl(opr_n, size-1, "__yeven");

llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp

if (PointerType *PT = dyn_cast<PointerType>(ArgTy)) {
         continue;
 
       // FIXME: We can replace this with equivalent alias.scope/noalias
       // metadata, but this appears to be a lot of work.
       if (Arg.hasNoAliasAttr())
         continue;
     }
 
-    VectorType *VT = dyn_cast<VectorType>(ArgTy);
+    auto *VT = dyn_cast<FixedVectorType>(ArgTy);
     bool IsV3 = VT && VT->getNumElements() == 3;
     bool DoShiftOpt = Size < 32 && !ArgTy->isAggregateType();
 
     VectorType *V4Ty = nullptr;
 
     int64_t AlignDownOffset = alignDown(EltOffset, 4);
     int64_t OffsetDiff = EltOffset - AlignDownOffset;
     Align AdjustedAlign = commonAlignment(

llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp

if (ConstExpr) {
         unsigned ArgSize = TD->getTypeAllocSizeInBits(ArgType);
         ArgSize = ArgSize / 8;
         //
         // ArgSize by design should be a multiple of DWORD_ALIGN,
         // expand the arguments that do not follow this rule.
         //
         if (ArgSize % DWORD_ALIGN != 0) {
           llvm::Type *ResType = llvm::Type::getInt32Ty(Ctx);
-          VectorType *LLVMVecType = llvm::dyn_cast<llvm::VectorType>(ArgType);
+          auto *LLVMVecType = llvm::dyn_cast<llvm::FixedVectorType>(ArgType);
           int NumElem = LLVMVecType ? LLVMVecType->getNumElements() : 1;
           if (LLVMVecType && NumElem > 1)
-            ResType = llvm::VectorType::get(ResType, NumElem);
+            ResType = llvm::FixedVectorType::get(ResType, NumElem);
           Builder.SetInsertPoint(CI);
           Builder.SetCurrentDebugLocation(CI->getDebugLoc());
           if (OpConvSpecifiers[ArgCount - 1] == 'x' ||
               OpConvSpecifiers[ArgCount - 1] == 'X' ||
               OpConvSpecifiers[ArgCount - 1] == 'u' ||
               OpConvSpecifiers[ArgCount - 1] == 'o')
             Arg = Builder.CreateZExt(Arg, ResType);
           else
if (ConstExpr) {
             uint64_t Size = TD->getTypeAllocSizeInBits(ArgType);
             assert((Size == 32 || Size == 64) && "unsupported size");
             Type *DstType = (Size == 32) ? Int32Ty : Int64Ty;
             Arg = new PtrToIntInst(Arg, DstType, "PrintArgPtr", Brnch);
             WhatToStore.push_back(Arg);
           }
         } else if (isa<FixedVectorType>(ArgType)) {
           Type *IType = NULL;
-          uint32_t EleCount = cast<VectorType>(ArgType)->getNumElements();
+          uint32_t EleCount = cast<FixedVectorType>(ArgType)->getNumElements();
           uint32_t EleSize = ArgType->getScalarSizeInBits();
           uint32_t TotalSize = EleCount * EleSize;
           if (EleCount == 3) {
             ShuffleVectorInst *Shuffle =
                 new ShuffleVectorInst(Arg, Arg, ArrayRef<int>{0, 1, 2, 2});
             Shuffle->insertBefore(Brnch);
             Arg = Shuffle;
             ArgType = Arg->getType();

llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

Value *AMDGPUPromoteAlloca::getWorkitemID(IRBuilder<> &Builder, unsigned N) {
 
   Function *WorkitemIdFn = Intrinsic::getDeclaration(Mod, IntrID);
   CallInst *CI = Builder.CreateCall(WorkitemIdFn);
   ST.makeLIDRangeMetadata(CI);
 
   return CI;
 }
 
-static VectorType *arrayTypeToVecType(ArrayType *ArrayTy) {
-  return VectorType::get(ArrayTy->getElementType(),
+static FixedVectorType *arrayTypeToVecType(ArrayType *ArrayTy) {
+  return FixedVectorType::get(ArrayTy->getElementType(),
                               ArrayTy->getNumElements());
 }
 
 static Value *stripBitcasts(Value *V) {
   while (Instruction *I = dyn_cast<Instruction>(V)) {
     if (I->getOpcode() != Instruction::BitCast)
       break;
     V = I->getOperand(0);
   }

 static bool tryPromoteAllocaToVector(AllocaInst *Alloca, const DataLayout &DL) {
 
   if (DisablePromoteAllocaToVector) {
     LLVM_DEBUG(dbgs() << "  Promotion alloca to vector is disabled\n");
     return false;
   }
 
   Type *AllocaTy = Alloca->getAllocatedType();
-  VectorType *VectorTy = dyn_cast<VectorType>(AllocaTy);
+  auto *VectorTy = dyn_cast<FixedVectorType>(AllocaTy);
   if (auto *ArrayTy = dyn_cast<ArrayType>(AllocaTy)) {
     if (VectorType::isValidElementType(ArrayTy->getElementType()) &&
         ArrayTy->getNumElements() > 0)
       VectorTy = arrayTypeToVecType(ArrayTy);
   }
 
   LLVM_DEBUG(dbgs() << "Alloca candidate for vectorization\n");
 

llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp

 
 bool AMDGPURewriteOutArguments::doInitialization(Module &M) {
   DL = &M.getDataLayout();
   return false;
 }
 
 #ifndef NDEBUG
 bool AMDGPURewriteOutArguments::isVec3ToVec4Shuffle(Type *Ty0, Type* Ty1) const {
-  VectorType *VT0 = dyn_cast<VectorType>(Ty0);
-  VectorType *VT1 = dyn_cast<VectorType>(Ty1);
+  auto *VT0 = dyn_cast<FixedVectorType>(Ty0);
+  auto *VT1 = dyn_cast<FixedVectorType>(Ty1);
   if (!VT0 || !VT1)
     return false;
 
   if (VT0->getNumElements() != 3 ||
       VT1->getNumElements() != 4)
     return false;
 
   return DL->getTypeSizeInBits(VT0->getElementType()) ==

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

bool GCNTTIImpl::rewriteIntrinsicWithAddressSpace(
   default:
     return false;
   }
 }
 
 unsigned GCNTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *VT,
                                     int Index, VectorType *SubTp) {
   if (ST->hasVOP3PInsts()) {
-    if (VT->getNumElements() == 2 &&
+    if (cast<FixedVectorType>(VT)->getNumElements() == 2 &&
         DL.getTypeSizeInBits(VT->getElementType()) == 16) {
       // With op_sel VOP3P instructions freely can access the low half or high
       // half of a register, so any swizzle is free.
 
       switch (Kind) {
       case TTI::SK_Broadcast:
       case TTI::SK_Reverse:
       case TTI::SK_PermuteSingleSrc:

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
 
   return TargetLowering::getVectorTypeBreakdownForCallingConv(
     Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
 }
 
 static EVT memVTFromImageData(Type *Ty, unsigned DMaskLanes) {
   assert(DMaskLanes != 0);
 
-  if (auto *VT = dyn_cast<VectorType>(Ty)) {
+  if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
     unsigned NumElts = std::min(DMaskLanes,
-                                static_cast<unsigned>(VT->getNumElements()));
+                                VT->getNumElements());
     return EVT::getVectorVT(Ty->getContext(),
                             EVT::getEVT(VT->getElementType()),
                             NumElts);
   }
 
   return EVT::getEVT(Ty);
 }