In RISC-V V specification, 'undisturbed' means the values of destination registers will not be changed. There are two scenarios there will be 'undisturbed' elements. One is for tail elements and the other is masked off elements. If the instructions have 'undisturbed' semantics, destination register is also one of the inputs of the instructions.
Shouldn't these instructions have a maskedoff field as well? As you mention undisturbed applies both to inactive elements (masked-off) and tail elements.
That is what I understand from https://riscv.github.io/documents/riscv-v-spec/#sec-mask-register-logical