Page MenuHomePhabricator

[RISCV] Enable 'undisturbed' semantics in instruction definitions.
AbandonedPublic

Authored by HsiangKai on May 6 2020, 7:53 PM.

Details

Summary

In RISC-V V specification, 'undisturbed' means the values of destination registers will not be changed. There are two scenarios there will be 'undisturbed' elements. One is for tail elements and the other is masked off elements. If the instructions have 'undisturbed' semantics, destination register is also one of the inputs of the instructions.

Diff Detail

Event Timeline

HsiangKai created this revision.May 6 2020, 7:53 PM
rogfer01 added inline comments.May 7 2020, 12:50 AM
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
831

Shouldn't these instructions have a maskedoff field as well? As you mention undisturbed applies both to inactive elements (masked-off) and tail elements.

That is what I understand from https://riscv.github.io/documents/riscv-v-spec/#sec-mask-register-logical

Vector mask logical instructions are always unmasked so there are no inactive elements. Mask elements past vl, the tail elements, are unchanged.

HsiangKai marked an inline comment as done.May 19 2020, 2:23 AM
HsiangKai added inline comments.
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
831

It seems like every instruction should have maskedoff argument, because every instruction may have tail elements. I will review it. Thanks, Roger.

HsiangKai abandoned this revision.Jun 9 2020, 11:43 PM

I need to think about is it necessary to describe 'undisturbed' semantics in instruction definitions. Do not review it now.