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[RISCV] Add SiFive's interrupt modes
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Authored by apazos on May 6 2020, 2:36 PM.



RISC-V already has support for all the standard interrupt modes:
void f (void) _attribute_ ((interrupt ("machine")));
void f (void) _attribute_ ((interrupt ("user")));
void f (void) _attribute_ ((interrupt ("supervisor")));

This patch adds SiFive's interrupt modes which are available in SiFive's IP.


void f (void) _attribute_ ((interrupt ("SiFive-CLIC-preemptible")));
In this type of interrupt handler, in the prologue, the mepc and mcause
registers are saved, and interrupts are enabled. In the epilogue,
interrupts are disabled, and the mepc and mcause registers are restored.
This type of interrupt handler must be @code{machine} mode,and must not
use the frame pointer.

void f (void) _attribute_ ((interrupt ("SiFive-CLIC-stack-swap")));
In this type of interrupt handler, the stack pointer will be swapped with
the @code{mscratch} register in the prologue before the first use of the stack
pointer, and in the epilogue after the last use of the stack pointer.
This type of interrupt handler must be @code{machine} mode.

Diff Detail

Event Timeline

apazos created this revision.May 6 2020, 2:36 PM
asb added a comment.May 6 2020, 10:46 PM

Just to understand the current status with respect to GCC, am I right that support for these attributes is not in upstream GCC? @kito-cheng is there any plan to upstream?

As previously discussed, I think there's a good argument for supporting attributes and features in Clang/LLVM that have real-world users and where there is capacity to maintain it, but it would be useful to know if GCC was likely to support this or not.

Upstream didn't support those SiFive specific function attribute, and there is no plan to upstream unless CLIC ratified.
And I guess the attribute name would changed after GCC upstream, at least the prefix of SiFive- would be removed.

apazos updated this revision to Diff 262982.May 8 2020, 5:12 PM

Remove wrong setting of Framesetup flags

WIP - requires adding a flag to control clic mode version. Maybe something similar to what is being proposed in binutils.
New options: -mpriv-spec=[1p9|1p9p1|1p10|1p11] -misa-spec = [2p0|2p1|2p2|20190608|20191213]

khchen added a subscriber: khchen.Aug 20 2020, 6:44 AM
pli123 added a subscriber: pli123.Jun 10 2021, 4:25 PM
pli123 removed a subscriber: pli123.Jun 10 2021, 4:34 PM
pli123 added a subscriber: pli123.


I am working on a project that would like to use this feature in clang. This patch is from last year. What's the process to get this patch checked in?

lenary removed a subscriber: lenary.Jun 11 2021, 2:36 AM
rkruppe removed a subscriber: rkruppe.Jun 11 2021, 9:12 AM
asb added a comment.Jun 24 2021, 4:21 AM

We haven't yet added vendor-specific extensions to upstream RISC-V LLVM. Given SiFive are active in the upstream community I think I'd look to see one of those contributors advocating for this being merged, and we may need to have a slightly broader conversation about what the policy / expectations should be for such extensions going forwards.