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[RISCV] Support CLIC interruption mode named operands for CSR instructions
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Authored by apazos on May 6 2020, 11:25 AM.



Based on RISC-V Core-Local Interrupt Controller (CLIC) Version 0.9-draft-20200423 proposal.

WIP - requires adding a flag to control click mode version. Maybe something similar to what is being proposed in binutils:
New options: -mpriv-spec=[1p9|1p9p1|1p10|1p11] -misa-spec = [2p0|2p1|2p2|20190608|20191213]

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apazos created this revision.May 6 2020, 11:25 AM
apazos edited the summary of this revision. (Show Details)May 8 2020, 4:32 PM
pli123 added a subscriber: pli123.Jun 10 2021, 4:26 PM

Similar to, it would be nice to see progress on this feature since I am working on a project that would like to use this feature on clang.

I don't see adding experimental CSRs as hugely necessary. With CodeGen, intrinsics and instructions there's no nice way to do it without toolchain support, but for CSRs you can just #define the name.

Especially since there is shipping hardware with an implementation of a draft CLIC spec. As the spec evolves we would change the CSRs here, breaking code, but if you just #define to your particular platform's version of the CLIC then it will keep working forever.

lenary removed a subscriber: lenary.Jun 11 2021, 2:36 AM
rkruppe removed a subscriber: rkruppe.Jun 11 2021, 9:11 AM