[RISCV] Update debug scratch register names

[pzheng]

Summary

The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.

[jrtc27]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

358

I think

def : SysReg<"dscratch0", 0x7B2> {
  let AltName = "dscratch";
}

is nicer, but otherwise please drop the braces, ie:

let AltName = "dscratch" in
def : SysReg<"dscratch0", 0x7B2>

[pzheng]

Addressing comments

[apazos]

llvm/test/MC/RISCV/machine-csr-names.s

369

Maybe we should move these tests to debug-csr-names.s, similar to what you did in D78583.
I created this file in the past for CSRs vailid in machine mode.

[pzheng]

Moving debug mode registers to a new test file

[apazos]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

23

I think this limitation is fine.
I have not seen a case with CSRs where we need a list of strings to support multiple aliases.
Let's see what Alex or others say

[asb]

Sorry to ask you to move things back, but I think the debug CSR tests would make most sense in machine-csr-names.s on the basis that the privileged spec does list those CSRs in the "machine-level CSR names" table.

llvm/lib/Target/RISCV/RISCVSystemOperands.td

23

I agree the limitation isn't a problem for the RISC-V backend right now. It's conceivable it could become one. My only concern with leaving it as a FIXME is it might prompt someone to invest effort in this when there's not much reason to do so. Maybe better as // Note: changes to SearchableTableEmitter may be needed if multiple aliases are needed in the future. But I'm not sure what is most consistent with the use of FIXME elsewhere in the codebase. Plus a note like that risks becoming stale. With that in mind, I'd err towards a factual // A maximum of one alias is supported right now.

But ultimately, I don't have a particularly strong view about how to best comment this.

[pzheng]

Address @asb's comments

[asb]

LGTM, thanks. Left one tiny nit inline.

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

160

I'd drop this FIXME - it's not an immediate problem and the limitation is documented in RISCVSystemOperands.td

[pzheng]

Good catch. Thanks for reviewing, @asb.

[evandro]

Note: this patch maintains backwards compatibility with a preliminary spec.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

case AsmToken::String: {
     return MatchOperand_ParseFail;
   }
   case AsmToken::Identifier: {
     StringRef Identifier;
     if (getParser().parseIdentifier(Identifier))
       return MatchOperand_ParseFail;
 
     auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier);
+    if (!SysReg)
+      SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier);
     // Accept a named Sys Reg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {
         Error(S, "system register use requires an option to be enabled");
         return MatchOperand_ParseFail;
       }
       Operands.push_back(RISCVOperand::createSysReg(
           Identifier, S, SysReg->Encoding, isRV64()));

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 
 //===----------------------------------------------------------------------===//
 // CSR (control and status register read/write) instruction options.
 //===----------------------------------------------------------------------===//
 
 class SysReg<string name, bits<12> op> {
   string Name = name;
   bits<12> Encoding = op;
+  // FIXME: support multiple aliases when needed
+  string AltName = name;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
   // Privilege Mode: User = 0, System = 1 or Machine = 3.
   // bits<2> ReadWrite = op{11 - 10};
   // bits<2> XMode = op{9 - 8};
   // Check Extra field name and what bits 7-6 correspond to.
   // bits<2> Extra = op{7 - 6};
   // Register number without the privilege bits.
   // bits<6> Number = op{5 - 0};
   code FeaturesRequired = [{ {} }];
   bit isRV32Only = 0;
 }
 
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
   // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
-  let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
+  let Fields = [ "Name", "Encoding", "AltName", "FeaturesRequired", "isRV32Only" ];
 
   let PrimaryKey = [ "Encoding" ];
   let PrimaryKeyName = "lookupSysRegByEncoding";
 }
 
 def lookupSysRegByName : SearchIndex {
   let Table = SysRegsList;
   let Key = [ "Name" ];
 }
 
+def lookupSysRegByAltName : SearchIndex {
+  let Table = SysRegsList;
+  let Key = [ "AltName" ];
+}
+
 // The following CSR encodings match those given in Tables 2.2,
 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
 
 //===--------------------------
 // User Trap Setup
 //===--------------------------
 def : SysReg<"ustatus", 0x000>;

 def : SysReg<"tdata2", 0x7A2>;
 def : SysReg<"tdata3", 0x7A3>;
 
 //===-----------------------------------------------
 // Debug Mode Registers
 //===-----------------------------------------------
 def : SysReg<"dcsr", 0x7B0>;
 def : SysReg<"dpc", 0x7B1>;
-def : SysReg<"dscratch", 0x7B2>;
+// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
+// drafts of the RISC-V debug spec
+let AltName = "dscratch" in
+def : SysReg<"dscratch0", 0x7B2>;
+def : SysReg<"dscratch1", 0x7B3>;

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

inline static bool isValidRoundingMode(unsigned Mode) {
   }
 }
 } // namespace RISCVFPRndMode
 
 namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
   unsigned Encoding;
+  // FIXME: support multiple aliases when needed
+  const char *AltName;
   // FIXME: add these additional fields when needed.
   // Privilege Access: Read, Write, Read-Only.
   // unsigned ReadWrite;
   // Privilege Mode: User, System or Machine.
   // unsigned Mode;
   // Check field name.
   // unsigned Extra;
   // Register number without the privilege bits.

llvm/test/MC/RISCV/debug-csr-names.s

+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+#######################
+# Debug Mode Registers
+########################
+# dcsr
+# name
+# CHECK-INST: csrrs t1, dcsr, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dcsr
+# uimm12
+# CHECK-INST: csrrs t2, dcsr, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dcsr
+# name
+csrrs t1, dcsr, zero
+# uimm12
+csrrs t2, 0x7B0, zero
+
+# dpc
+# name
+# CHECK-INST: csrrs t1, dpc, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dpc
+# uimm12
+# CHECK-INST: csrrs t2, dpc, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dpc
+# name
+csrrs t1, dpc, zero
+# uimm12
+csrrs t2, 0x7B1, zero
+
+# dscratch0
+# name
+# CHECK-INST: csrrs t1, dscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch0
+# uimm12
+# CHECK-INST: csrrs t2, dscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch0
+# name
+csrrs t1, dscratch0, zero
+# uimm12
+csrrs t2, 0x7B2, zero
+
+# dscratch
+# name
+# CHECK-INST: csrrs t1, dscratch0, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch0
+# uimm12
+# CHECK-INST: csrrs t2, dscratch0, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch0
+# name
+csrrs t1, dscratch, zero
+# uimm12
+csrrs t2, 0x7B2, zero
+
+# dscratch1
+# name
+# CHECK-INST: csrrs t1, dscratch1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t1, dscratch1
+# uimm12
+# CHECK-INST: csrrs t2, dscratch1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7b]
+# CHECK-INST-ALIAS: csrr t2, dscratch1
+# name
+csrrs t1, dscratch1, zero
+# uimm12
+csrrs t2, 0x7B3, zero

llvm/test/MC/RISCV/machine-csr-names.s

 # CHECK-INST: csrrs t2, tdata3, zero
 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7a]
 # CHECK-INST-ALIAS: csrr t2, tdata3
 # name
 csrrs t1, tdata3, zero
 # uimm12
 csrrs t2, 0x7A3, zero
 
-#######################
-# Debug Mode Registers
-########################
-# dcsr
-# name
-# CHECK-INST: csrrs t1, dcsr, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x00,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dcsr
-# uimm12
-# CHECK-INST: csrrs t2, dcsr, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dcsr
-# name
-csrrs t1, dcsr, zero
-# uimm12
-csrrs t2, 0x7B0, zero
-
-# dpc
-# name
-# CHECK-INST: csrrs t1, dpc, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x10,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dpc
-# uimm12
-# CHECK-INST: csrrs t2, dpc, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dpc
-# name
-csrrs t1, dpc, zero
-# uimm12
-csrrs t2, 0x7B1, zero
-
-# dscratch
-# name
-# CHECK-INST: csrrs t1, dscratch, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t1, dscratch
-# uimm12
-# CHECK-INST: csrrs t2, dscratch, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7b]
-# CHECK-INST-ALIAS: csrr t2, dscratch
-# name
-csrrs t1, dscratch, zero
-# uimm12
-csrrs t2, 0x7B2, zero
-
 # mhpmcounter3
 # name
 # CHECK-INST: csrrs t1, mhpmcounter3, zero
 # CHECK-ENC:  encoding: [0x73,0x23,0x30,0xb0]
 # CHECK-INST-ALIAS: csrr t1, mhpmcounter3
 # uimm12
 # CHECK-INST: csrrs t2, mhpmcounter3, zero
 # CHECK-ENC:  encoding: [0xf3,0x23,0x30,0xb0]
 # CHECK-INST-ALIAS: csrr t2, mhpmcounter3