[MIR] Add comments to INLINEASM immediate flag MachineOperands

[kschwarz]

Summary

The INLINEASM MIR instructions use immediate operands to encode the values of some operands.
The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature.

[kschwarz]

I've thought about adding enum to string conversion functions to InlineAsm.h, which could be reused from both MachineInstr.cpp and TargetInstrInfo.cpp to avoid code duplication.
Would that be preferred here?

[SjoerdMeijer]

I like it!
Some minor comments and nits in line.

llvm/lib/CodeGen/TargetInstrInfo.cpp

1330

Can we do an early exit here:

if (!MI.isInlineAsm())
  return std::string();

that also reduces some identation below..

1332

do we need OS here?

1338

can we then just do

return "sideeffect";

here, and similar for the if-stmts below?

1353

We don't need the 'else'?

1369

probably just an assert here is better?

1404

and same here?

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

498–508

This comment is out of date now and needs a minor update.

[kschwarz]

llvm/lib/CodeGen/TargetInstrInfo.cpp

1332

We could simply append to a std::string here, but the cases below need to append other things (integers), so I felt like using an ostream might be more elegant?

1338

Unfortunately no, the immediate we are looking at here encodes multiple values at once, so we need to compose the string here.

[arsenm]

llvm/lib/CodeGen/TargetInstrInfo.cpp

1330

return ""?

1334

This is essentially repeated in MachineInstr, should unify these? I guess we are already duplicated the flag handling

[kschwarz]

Address review comments

[arsenm]

llvm/include/llvm/IR/InlineAsm.h

403–404

llvm_unreachable

451–452

llvm_unreachable

[kschwarz]

Change assert to llvm_unreachable

[arsenm]

llvm/lib/CodeGen/TargetInstrInfo.cpp

1326

Should this write to a raw_ostream rather than returning a string?

[kschwarz]

1a3e89aa2bd26ad05b25635457bad28f46427eeb

[kschwarz]

llvm/lib/CodeGen/TargetInstrInfo.cpp

1326

I'm not sure why it originally returned a string, but the function already existed before this patch

[craig.topper]

llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir

41

So if the register class encodings in the tablegen generated files have changed since the test was created, the input MIR is incorrect and the output will just show whatever class has that encoding today? And will suddently fail the next time the encodings change?

[kschwarz]

llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir

41

Yes, the register class is encoded in the "flags" immediate operand (7405578 in this case). If that encoding changes, this test needs to be updated. The change made here simply adds a human-readable comment to the immediate operands. The intent is to make tests more meaningful for humans to read.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
 
   /// Return true for post-incremented instructions.
   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
 
   /// Returns true if the instruction is already predicated.
   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
 
   // Returns a MIRPrinter comment for this machine operand.
-  virtual std::string createMIROperandComment(const MachineInstr &MI,
-                                              const MachineOperand &Op,
-                                              unsigned OpIdx) const {
-    return std::string();
-  };
+  virtual std::string
+  createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
+                          unsigned OpIdx, const TargetRegisterInfo *TRI) const;
 
   /// Returns true if the instruction is a
   /// terminator instruction that has not been predicated.
   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
 
   /// Returns true if MI is an unconditional tail call.
   virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
     return false;

llvm/include/llvm/IR/InlineAsm.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_IR_INLINEASM_H
 #define LLVM_IR_INLINEASM_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/IR/Value.h"
+#include "llvm/Support/ErrorHandling.h"
 #include <cassert>
 #include <string>
 #include <vector>
 
 namespace llvm {
 
 class FunctionType;
 class PointerType;
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
     unsigned High = Flag >> 16;
     // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
     // stores RC + 1.
     if (!High)
       return false;
     RC = High - 1;
     return true;
   }
+
+  static std::vector<StringRef> getExtraInfoNames(unsigned ExtraInfo) {
+    std::vector<StringRef> Result;
+    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
+      Result.push_back("sideeffect");
+    if (ExtraInfo & InlineAsm::Extra_MayLoad)
+      Result.push_back("mayload");
+    if (ExtraInfo & InlineAsm::Extra_MayStore)
+      Result.push_back("maystore");
+    if (ExtraInfo & InlineAsm::Extra_IsConvergent)
+      Result.push_back("isconvergent");
+    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
+      Result.push_back("alignstack");
+
+    AsmDialect Dialect =
+        InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect));
+
+    if (Dialect == InlineAsm::AD_ATT)
+      Result.push_back("attdialect");
+    if (Dialect == InlineAsm::AD_Intel)
+      Result.push_back("inteldialect");
+
+    return Result;
+  }
+
+  static StringRef getKindName(unsigned Kind) {
+    switch (Kind) {
+    case InlineAsm::Kind_RegUse:
+      return "reguse";
+    case InlineAsm::Kind_RegDef:
+      return "regdef";
+    case InlineAsm::Kind_RegDefEarlyClobber:
+      return "regdef-ec";
+    case InlineAsm::Kind_Clobber:
+      return "clobber";
+    case InlineAsm::Kind_Imm:
+      return "imm";
+    case InlineAsm::Kind_Mem:
+      return "mem";
+    default:
+      llvm_unreachable("Unknown operand kind");
+    }
+  }
+
+  static StringRef getMemConstraintName(unsigned Constraint) {
+    switch (Constraint) {
+    case InlineAsm::Constraint_es:
+      return "es";
+    case InlineAsm::Constraint_i:
+      return "i";
+    case InlineAsm::Constraint_m:
+      return "m";
+    case InlineAsm::Constraint_o:
+      return "o";
+    case InlineAsm::Constraint_v:
+      return "v";
+    case InlineAsm::Constraint_Q:
+      return "Q";
+    case InlineAsm::Constraint_R:
+      return "R";
+    case InlineAsm::Constraint_S:
+      return "S";
+    case InlineAsm::Constraint_T:
+      return "T";
+    case InlineAsm::Constraint_Um:
+      return "Um";
+    case InlineAsm::Constraint_Un:
+      return "Un";
+    case InlineAsm::Constraint_Uq:
+      return "Uq";
+    case InlineAsm::Constraint_Us:
+      return "Us";
+    case InlineAsm::Constraint_Ut:
+      return "Ut";
+    case InlineAsm::Constraint_Uv:
+      return "Uv";
+    case InlineAsm::Constraint_Uy:
+      return "Uy";
+    case InlineAsm::Constraint_X:
+      return "X";
+    case InlineAsm::Constraint_Z:
+      return "Z";
+    case InlineAsm::Constraint_ZC:
+      return "ZC";
+    case InlineAsm::Constraint_Zy:
+      return "Zy";
+    default:
+      llvm_unreachable("Unknown memory constraint");
+    }
+  }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_IR_INLINEASM_H

llvm/lib/CodeGen/MIRPrinter.cpp

 }
 
 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
                       const TargetRegisterInfo *TRI,
                       const TargetInstrInfo *TII,
                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
                       bool PrintDef) {
   const MachineOperand &Op = MI.getOperand(OpIdx);
-  std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
+  std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
 
   switch (Op.getType()) {
   case MachineOperand::MO_Immediate:
     if (MI.isOperandSubregIdx(OpIdx)) {
       MachineOperand::printTargetFlags(OS, Op);
       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
       break;
     }

llvm/lib/CodeGen/MachineInstr.cpp

if (isDebugValue() && MO.isMetadata()) {
         unsigned TiedOperandIdx = getTiedOperandIdx(i);
         MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
       }
     } else if (i == AsmDescOp && MO.isImm()) {
       // Pretty print the inline asm operand descriptor.
       OS << '$' << AsmOpCount++;
       unsigned Flag = MO.getImm();
-      switch (InlineAsm::getKind(Flag)) {
-      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
-      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
-      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
-      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
-      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
-      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
-      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
-      }
+      OS << ":[";
+      OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
 
       unsigned RCID = 0;
       if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
           InlineAsm::hasRegClassConstraint(Flag, RCID)) {
         if (TRI) {
           OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
         } else
           OS << ":RC" << RCID;
       }
 
       if (InlineAsm::isMemKind(Flag)) {
         unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
-        switch (MCID) {
-        case InlineAsm::Constraint_es: OS << ":es"; break;
-        case InlineAsm::Constraint_i:  OS << ":i"; break;
-        case InlineAsm::Constraint_m:  OS << ":m"; break;
-        case InlineAsm::Constraint_o:  OS << ":o"; break;
-        case InlineAsm::Constraint_v:  OS << ":v"; break;
-        case InlineAsm::Constraint_Q:  OS << ":Q"; break;
-        case InlineAsm::Constraint_R:  OS << ":R"; break;
-        case InlineAsm::Constraint_S:  OS << ":S"; break;
-        case InlineAsm::Constraint_T:  OS << ":T"; break;
-        case InlineAsm::Constraint_Um: OS << ":Um"; break;
-        case InlineAsm::Constraint_Un: OS << ":Un"; break;
-        case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
-        case InlineAsm::Constraint_Us: OS << ":Us"; break;
-        case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
-        case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
-        case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
-        case InlineAsm::Constraint_X:  OS << ":X"; break;
-        case InlineAsm::Constraint_Z:  OS << ":Z"; break;
-        case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
-        case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
-        default: OS << ":?"; break;
-        }
+        OS << ":" << InlineAsm::getMemConstraintName(MCID);
       }
 
       unsigned TiedTo = 0;
       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
         OS << " tiedto:$" << TiedTo;
 
       OS << ']';
 

llvm/lib/CodeGen/TargetInstrInfo.cpp

bool TargetInstrInfo::getInsertSubregInputs(
   BaseReg.SubReg = MOBaseReg.getSubReg();
 
   InsertedReg.Reg = MOInsertedReg.getReg();
   InsertedReg.SubReg = MOInsertedReg.getSubReg();
   InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
   return true;
 }
 
+// Returns a MIRPrinter comment for this machine operand.
+std::string TargetInstrInfo::createMIROperandComment(
+    const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
+    const TargetRegisterInfo *TRI) const {
+
+  if (!MI.isInlineAsm())
+    return "";
+
+  std::string Flags;
+  raw_string_ostream OS(Flags);
+
+  if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
+    // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
+    unsigned ExtraInfo = Op.getImm();
+    bool First = true;
+    for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
+      if (!First)
+        OS << " ";
+      First = false;
+      OS << Info;
+    }
+
+    return OS.str();
+  }
+
+  int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
+  if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
+    return "";
+
+  assert(Op.isImm() && "Expected flag operand to be an immediate");
+  // Pretty print the inline asm operand descriptor.
+  unsigned Flag = Op.getImm();
+  unsigned Kind = InlineAsm::getKind(Flag);
+  OS << InlineAsm::getKindName(Kind);
+
+  unsigned RCID = 0;
+  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
+      InlineAsm::hasRegClassConstraint(Flag, RCID)) {
+    if (TRI) {
+      OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
+    } else
+      OS << ":RC" << RCID;
+  }
+
+  if (InlineAsm::isMemKind(Flag)) {
+    unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
+    OS << ":" << InlineAsm::getMemConstraintName(MCID);
+  }
+
+  unsigned TiedTo = 0;
+  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
+    OS << " tiedto:$" << TiedTo;
+
+  return OS.str();
+}
+
 TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() {}

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

public:
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   // Predication support.
   bool isPredicated(const MachineInstr &MI) const override;
 
   // MIR printer helper function to annotate Operands with a comment.
-  std::string createMIROperandComment(const MachineInstr &MI,
-                                      const MachineOperand &Op,
-                                      unsigned OpIdx) const override;
+  std::string
+  createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
+                          unsigned OpIdx,
+                          const TargetRegisterInfo *TRI) const override;
 
   ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
     int PIdx = MI.findFirstPredOperandIdx();
     return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
                       : ARMCC::AL;
   }
 
   bool PredicateInstruction(MachineInstr &MI,

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

if (MI.isBundle()) {
     }
     return false;
   }
 
   int PIdx = MI.findFirstPredOperandIdx();
   return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
 }
 
-std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
-                                                      const MachineOperand &Op,
-                                                      unsigned OpIdx) const {
-  // Only support immediates for now.
+std::string ARMBaseInstrInfo::createMIROperandComment(
+    const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
+    const TargetRegisterInfo *TRI) const {
+
+  // First, let's see if there is a generic comment for this operand
+  std::string GenericComment =
+      TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
+  if (!GenericComment.empty())
+    return GenericComment;
+
+  // If not, check if we have an immediate operand.
   if (Op.getType() != MachineOperand::MO_Immediate)
     return std::string();
 
   // And print its corresponding condition code if the immediate is a
   // predicate.
   int FirstPredOp = MI.findFirstPredOperandIdx();
   if (FirstPredOp != (int) OpIdx)
     return std::string();

llvm/test/CodeGen/AArch64/seqpairspill.mir

bb.0:
     ; CHECK: INLINEASM
     ; CHECK: renamable $[[REG2:[a-z0-9]+]], renamable $[[REG3:[a-z0-9]+]] = LDPXi %stack.0, 0, implicit-def $[[REG2]]_[[REG3]] :: (load 16 from %stack.0, align 8)
     ; CHECK-NEXT: $xzr = COPY renamable $[[REG2]]
     ; CHECK-NEXT: $xzr = COPY renamable $[[REG3]]
     %0 : xseqpairsclass = IMPLICIT_DEF
     %1 : xseqpairsclass = IMPLICIT_DEF
     %2 : gpr64common = IMPLICIT_DEF
     %0 = CASPALX %0, %1, %2
-    INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
+    INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
     $xzr = COPY %0.sube64
     $xzr = COPY %0.subo64
 ...
 ---
 # CHECK-LABEL: name: spill_reload_wseqpairs
 name: spill_reload_wseqpairs
 body: |
   bb.0:
     ; Check the spill/reload sequence for the %0 register
     ; CHECK: $[[REG0:[a-z0-9]+]]_[[REG1:[a-z0-9]+]] = CASPALW
     ; CHECK-NEXT: STPWi renamable $[[REG0]], renamable $[[REG1]], %stack.0, 0, implicit killed $[[REG0]]_[[REG1]] :: (store 8 into %stack.0, align 4)
     ; CHECK: INLINEASM
     ; CHECK: renamable $[[REG2:[a-z0-9]+]], renamable $[[REG3:[a-z0-9]+]] = LDPWi %stack.0, 0, implicit-def $[[REG2]]_[[REG3]] :: (load 8 from %stack.0, align 4)
     ; CHECK-NEXT: $xzr = COPY renamable $[[REG2]]
     ; CHECK-NEXT: $xzr = COPY renamable $[[REG3]]
     %0 : wseqpairsclass = IMPLICIT_DEF
     %1 : wseqpairsclass = IMPLICIT_DEF
     %2 : gpr64common = IMPLICIT_DEF
     %0 = CASPALW %0, %1, %2
-    INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
+    INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
     $xzr = COPY %0.sube32
     $xzr = COPY %0.subo32
 ...

llvm/test/CodeGen/AMDGPU/endpgm-dce.mir

registers:
   - { id: 1, class: vgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     %2:sreg_64 = IMPLICIT_DEF
-    INLINEASM &"", 0, 0
+    INLINEASM &"", 0
     S_ENDPGM 0
 ...
 
 ---
 # GCN-LABEL: name: inlineasm_sideeffect
 # GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
 # GCN-NEXT: IMPLICIT_DEF
 # GCN-NEXT: INLINEASM
 # GCN-NEXT: S_ENDPGM 0
 name: inlineasm_sideeffect
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
 body:             |
   bb.0:
     $vcc = IMPLICIT_DEF
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
     %2:sreg_64 = IMPLICIT_DEF
-    INLINEASM &"", 1, 0
+    INLINEASM &"", 1
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir

bb.2:
     S_NOP 0, implicit %0.sub2
 
 ...
 # In this test, there are two pairs of tied operands
 # within the inline asm statement:
 # (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
 # Check that renaming (2) does not inadvertently rename (1).
 # CHECK-LABEL: name: test2
-# CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
+# CHECK: INLINEASM &"", 32 /* isconvergent attdialect */, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def undef %0.sub0, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
 name: test2
 body: |
   bb.0:
     undef %0.sub0:vreg_64 = IMPLICIT_DEF
 
   bb.1:
     undef %0.sub1:vreg_64 = V_ALIGNBIT_B32 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
     INLINEASM &"", 32, 327690, def undef %0.sub0:vreg_64, 327690, def %0.sub1:vreg_64, 2147483657, undef %0.sub0:vreg_64(tied-def 3), 2147549193, %0.sub1:vreg_64(tied-def 5)
     S_BRANCH %bb.1
 
 ...

llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir

body:             |
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, align 8, addrspace 5)
   ; CHECK:   dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
   ; CHECK:   dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
   ; CHECK:   dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
   ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
   ; CHECK:   undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
-  ; CHECK:   INLINEASM &"", 1, 851978, def dead [[COPY1]], 851978, def dead [[COPY]].sub1, 2147483657, [[COPY1]], 2147549193, [[COPY]].sub1
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY1]], 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
   ; CHECK:   %11.sub0:vreg_512 = COPY [[COPY]].sub0
   ; CHECK:   %11.sub3:vreg_512 = COPY [[COPY]].sub3
   ; CHECK:   dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
   ; CHECK:   %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
   ; CHECK:   %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
   ; CHECK:   [[COPY2:%[0-9]+]]:vreg_512 = COPY %11
   ; CHECK:   S_BRANCH %bb.1
   bb.0:

llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir

body:             |
   ; CHECK:   undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
   ; CHECK:   [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
   ; CHECK:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; CHECK:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   INLINEASM &"", 1, 851978, def dead %11
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead %11
   ; CHECK:   GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
   ; CHECK:   [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
-  ; CHECK:   INLINEASM &"def $0 $1", 1, 851978, def %15, 851978, def %16
+  ; CHECK:   INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %15, 851978 /* regdef:VRegOrLds_32 */, def %16
   ; CHECK:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
   ; CHECK:   [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
   ; CHECK:   [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
-  ; CHECK:   INLINEASM &"def $0 $1", 1, 851978, def %21, 851978, def %22
+  ; CHECK:   INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %21, 851978 /* regdef:VRegOrLds_32 */, def %22
   ; CHECK:   [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
-  ; CHECK:   INLINEASM &"", 1, 851978, def dead [[V_MOV_B32_e32_2]], 851978, def dead [[V_MOV_B32_e32_3]], 851977, [[DS_READ_B64_gfx9_]].sub0, 2147483657, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193, [[V_MOV_B32_e32_3]](tied-def 5), 851977, %15, 851977, %16, 851977, [[DS_READ_B32_gfx9_1]], 851977, [[DS_READ_B32_gfx9_]], 851977, [[DS_READ_B32_gfx9_3]], 851977, [[DS_READ_B32_gfx9_2]]
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:VRegOrLds_32 */, %15, 851977 /* reguse:VRegOrLds_32 */, %16, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_2]]
   ; CHECK:   %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
   ; CHECK:   DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
   ; CHECK:   DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
   ; CHECK:   DS_WRITE_B64_gfx9 undef %30:vgpr_32, %5, 0, 0, implicit $exec :: (store 8, addrspace 3)
   ; CHECK:   undef %31.sub1:vreg_64 = FLAT_LOAD_DWORD undef %32:vreg_64, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
   ; CHECK:   [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 1, [[DEF2]], implicit $exec
   ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
   ; CHECK:   [[DEF]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
   ; CHECK:   [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[V_ADD_U32_e32_]], [[S_MOV_B32_]], implicit $exec
   ; CHECK:   [[V_CMP_GT_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U32_e64 64, [[V_ADD_U32_e32_]], implicit $exec
   ; CHECK:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, [[V_ADD_U32_e32_]], [[V_CMP_GT_U32_e64_]], implicit $exec
   ; CHECK:   [[V_SUB_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e32 [[V_MUL_LO_U32_]], [[DEF1]], implicit $exec
   ; CHECK:   [[V_MUL_LO_U32_1:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[V_CNDMASK_B32_e64_]], [[S_MOV_B32_]], implicit $exec
   ; CHECK:   [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_SUB_U32_e32_]], [[DEF]].sub0, implicit $exec
   ; CHECK:   [[V_SUB_U32_e32_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e32 [[V_MUL_LO_U32_1]], [[V_MUL_LO_U32_]], implicit $exec
   ; CHECK:   [[DEF]].sub0:vreg_64 = V_ADD_U32_e32 [[V_SUB_U32_e32_1]], [[V_ADD_U32_e32_1]], implicit $exec
   ; CHECK:   undef %38.sub0:vreg_64, %39:sreg_64_xexec = V_ADD_I32_e64 [[S_LOAD_DWORDX2_IMM]].sub0, [[DEF]].sub0, 0, implicit $exec
   ; CHECK:   undef %40.sub1:vreg_64, dead %41:sreg_64_xexec = V_ADDC_U32_e64 [[COPY1]], [[DEF]].sub1, %39, 0, implicit $exec
   ; CHECK:   undef %42.sub0:sgpr_64 = V_READFIRSTLANE_B32 %38.sub0, implicit $exec
   ; CHECK:   %42.sub1:sgpr_64 = V_READFIRSTLANE_B32 %40.sub1, implicit $exec
   ; CHECK:   [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %42, 0, 0, 0 :: (load 4, addrspace 1)
-  ; CHECK:   INLINEASM &"", 1
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */
   ; CHECK:   [[DS_READ_B32_gfx9_4:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %45:vgpr_32, 0, 0, implicit $exec :: (load 4, addrspace 3)
   ; CHECK:   GLOBAL_STORE_DWORD undef %46:vreg_64, [[DS_READ_B32_gfx9_4]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
   ; CHECK:   %31.sub0:vreg_64 = COPY [[S_LOAD_DWORD_IMM]], implicit $exec
   ; CHECK:   DS_WRITE_B64_gfx9 undef %47:vgpr_32, %31, 0, 0, implicit $exec :: (store 8, addrspace 3)
   ; CHECK:   S_BRANCH %bb.1
   bb.0:
     liveins: $sgpr4_sgpr5
 

llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir

body:             |
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
-  ; CHECK:   INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
-  ; CHECK:   INLINEASM &"", 1, 851977, [[DS_READ_B32_gfx9_]]
-  ; CHECK:   INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def undef %0.sub1
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]]
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub0, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub1
   ; CHECK:   S_NOP 0, implicit %0.sub1
   ; CHECK:   $sgpr10 = S_MOV_B32 -1
   ; CHECK:   S_BRANCH %bb.1
   bb.0:
     undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
body:             |
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
-  ; CHECK:   INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
-  ; CHECK:   INLINEASM &"", 1, 851977, [[DS_READ_B32_gfx9_]]
-  ; CHECK:   INLINEASM &"", 1, 851978, def undef %0.sub1, 851978, def undef %0.sub0
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]]
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub1, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub0
   ; CHECK:   S_NOP 0, implicit %0.sub1
   ; CHECK:   $sgpr10 = S_MOV_B32 -1
   ; CHECK:   S_BRANCH %bb.1
   bb.0:
     undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 

llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir

body: |
   bb.1:
 
 ...
 ---
 # Test that after inline asm that defines vcc_lo, we insert any necessary
 # instructions to fix vccz.
 
 # CHECK-LABEL: name: inlineasm_def_vcc_lo
-# CHECK: INLINEASM &"; def vcc_lo", 1, 10, implicit-def $vcc_lo
+# CHECK: INLINEASM &"; def vcc_lo", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc_lo
 # SI:    $vcc = S_MOV_B64 $vcc
 # GFX9:  $vcc = S_MOV_B64 $vcc
 # CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
 
 name: inlineasm_def_vcc_lo
 body: |
   bb.0:
     INLINEASM &"; def vcc_lo", 1, 10, implicit-def $vcc_lo
     S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
   bb.1:
 
 ...
 ---
 # Test that after inline asm that defines vcc, no unnecessary instructions are
 # inserted to fix vccz.
 
 # CHECK-LABEL: name: inlineasm_def_vcc
-# CHECK: INLINEASM &"; def vcc", 1, 10, implicit-def $vcc
+# CHECK: INLINEASM &"; def vcc", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc
 # CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
 
 name: inlineasm_def_vcc
 body: |
   bb.0:
     INLINEASM &"; def vcc", 1, 10, implicit-def $vcc
     S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
   bb.1:
 
 ...

llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir

body:             |
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: $r0, $r1, $r2, $r4, $lr
   ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
   ; CHECK:   t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
   ; CHECK:   $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
   ; CHECK:   $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
   ; CHECK:   tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
-  ; CHECK:   INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
+  ; CHECK:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 0, 13 /* imm */, blockaddress(@fn1, %ir-block.l_yes)
   ; CHECK:   t2B %bb.1, 14 /* CC::al */, $noreg
   ; CHECK: bb.1:
-  ; CHECK:   INLINEASM &"", 1
+  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */
   ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
   ; CHECK: bb.2.l_yes (address-taken):
   ; CHECK:   $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $r0, $r1, $r2, $r4, $lr
 
     $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr

llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir

 body: |
   bb.0.entry:
     liveins: $edi, $esi
 
     frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     $ecx = COPY $edi
     $ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags
-  ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
+  ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $ax, 12 /* clobber */, implicit-def dead early-clobber $di
     INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
     $edi = COPY killed $ecx
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
     $rax = POP64r implicit-def $rsp, implicit $rsp
     RETQ
 ...

llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir

 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body: |
   bb.0.entry:
     liveins: $rdi, $rsi
 
   ; CHECK-LABEL: name: test
-  ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi,
+  ; CHECK: INLINEASM &foo, 0 /* attdialect */, 2818058 /* regdef:GR32_TC */, def $rsi, 2818058 /* regdef:GR32_TC */, def dead $rdi,
     INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
     $rax = MOV64rr killed $rsi
     RETQ killed $rax
 ...
 ---
 name:            test2
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }
 body: |
   bb.0.entry:
     liveins: $rdi, $rsi
 
   ; Verify that the register ties are preserved.
   ; CHECK-LABEL: name: test2
-  ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
+  ; CHECK: INLINEASM &foo, 0 /* attdialect */, 2818058 /* regdef:GR32_TC */, def $rsi, 2818058 /* regdef:GR32_TC */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags
     INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
     $rax = MOV64rr killed $rsi
     RETQ killed $rax
 ...

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir

body:             |
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.if.then:
-  ; MM:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; MM:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d6, $d7
body:             |
   ; MM:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; MM:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.2.if.then:
-  ; MM:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; MM:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; PIC:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; PIC:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC: bb.2.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $d6, $d7
 
     FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
     BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir

body:             |
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MM:   $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
   ; MM:   BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   BC_MMR6 %bb.3
   ; MM: bb.2.if.then:
-  ; MM:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MM:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
   ; PIC:   BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d12_64, $d14_64
body:             |
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; MM:   $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
   ; MM:   BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   BC_MMR6 %bb.3
   ; MM: bb.2.if.then:
-  ; MM:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MM:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
   ; PIC:   $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
   ; PIC:   BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
   ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $d12_64, $d14_64

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir

body:             |
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
-  ; MIPS:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; MIPS:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: a
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
-  ; MIPS:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; MIPS:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: b
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:

llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir

body:             |
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1NEZ $d0_64, %bb.2 {
   ; R6:     NOP
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
-  ; R6:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; R6:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: a
body:             |
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
body:             |
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1EQZ $d0_64, %bb.2 {
   ; R6:     NOP
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
-  ; R6:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; R6:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: b
body:             |
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:

llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir

body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z4bz_8Dv16_a
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_16Dv8_s
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_32Dv4_i
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_64Dv2_x
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bz_64_vDv2_x
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z5bnz_8Dv16_a
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_16Dv8_s
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_32Dv4_i
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_64Dv2_x
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:
body:             |
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.1.entry:
   ; MSA:   successors: %bb.3(0x80000000)
   ; MSA:   J %bb.3, implicit-def $at {
   ; MSA:     NOP
   ; MSA:   }
   ; MSA: bb.2.if.then:
-  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; MSA:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 1
   ; MSA:   }
   ; MSA: bb.3:
   ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; MSA:     renamable $v0 = ADDiu $zero, 0
   ; MSA:   }
   ; PIC-LABEL: name: _Z6bnz_64_vDv2_x
body:             |
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at_64 = DADDu $ra_64, $at_64
   ; PIC:   $ra_64 = LD $sp_64, 0
   ; PIC:   JR64 $at_64 {
   ; PIC:     $sp_64 = DADDiu $sp_64, 16
   ; PIC:   }
   ; PIC: bb.3.if.then:
-  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+  ; PIC:   INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 1
   ; PIC:   }
   ; PIC: bb.4:
   ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
   ; PIC:     renamable $v0 = ADDiu $zero, 0
   ; PIC:   }
   bb.0.entry:

llvm/test/CodeGen/Thumb2/high-reg-spill.mir

stack:
   - { id: 0, name: i, size: 4, alignment: 4, stack-id: default, local-offset: -4 }
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: constraint_h
     ; CHECK: renamable $r0 = tLDRspi %stack.0.i, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from %ir.i)
     ; CHECK: renamable $r12 = COPY killed renamable $r0
     ; CHECK: t2STRi12 killed $r12, %stack.1, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
     ; CHECK: $r8 = t2LDRi12 %stack.1, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
-    ; CHECK: INLINEASM &"@ $0", 1, 589833, renamable $r8, 12, implicit-def early-clobber $r12
+    ; CHECK: INLINEASM &"@ $0", 1 /* sideeffect attdialect */, 589833 /* reguse:GPRnopc */, renamable $r8, 12 /* clobber */, implicit-def early-clobber $r12
     ; CHECK: tBX_RET 14 /* CC::al */, $noreg
     %1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
     %0:hgpr = COPY %1
     INLINEASM &"@ $0", 1, 589833, %0, 12, implicit-def early-clobber $r12
     tBX_RET 14, $noreg
 
 ...

llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll

 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s
 
 ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
 ; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
-; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0 /* attdialect */, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
 
 define <8 x i64> @mask_Yk_i8(i8 signext %msk, <8 x i64> %x, <8 x i64> %y) {
 entry:
   %0 = tail call <8 x i64> asm "vpaddq\09$3, $2, $0 {$1}", "=x,^Yk,x,x,~{dirflag},~{fpsr},~{flags}"(i8 %msk, <8 x i64> %x, <8 x i64> %y)
   ret <8 x i64> %0
 }

llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll

 ; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s
 
-; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
 define void @foo() {
 entry:
   call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
   ret void
 }

llvm/test/CodeGen/X86/stack-folding-adx.mir

bb.0 (%ir-block.0):
     liveins: $edi, $esi, $edx, $rcx
 
     ; CHECK-LABEL: name: stack_fold_adcx32
     ; CHECK: liveins: $edi, $esi, $edx, $rcx
     ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rcx :: (store 8 into %stack.0)
     ; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
     ; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
-    ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
     ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
     ; CHECK: [[ADCX32rm:%[0-9]+]]:gr32 = ADCX32rm [[ADCX32rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 4 from %stack.1)
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV32mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADCX32rm]] :: (store 4 into %ir.4, align 1)
     ; CHECK: $al = COPY [[SETCCr]]
bb.0 (%ir-block.0):
     liveins: $edi, $rsi, $rdx, $rcx
 
     ; CHECK-LABEL: name: stack_fold_adcx64
     ; CHECK: liveins: $edi, $rsi, $rdx, $rcx
     ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rcx :: (store 8 into %stack.0)
     ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
     ; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
-    ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
     ; CHECK: [[ADCX64rm:%[0-9]+]]:gr64 = ADCX64rm [[ADCX64rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 8 from %stack.1)
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV64mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADCX64rm]] :: (store 8 into %ir.4, align 1)
     ; CHECK: $al = COPY [[SETCCr]]
bb.0 (%ir-block.0):
     liveins: $edi, $esi, $edx, $rcx
 
     ; CHECK-LABEL: name: stack_fold_adox32
     ; CHECK: liveins: $edi, $esi, $edx, $rcx
     ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rcx :: (store 8 into %stack.0)
     ; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
     ; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
-    ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
     ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
     ; CHECK: [[ADOX32rm:%[0-9]+]]:gr32 = ADOX32rm [[ADOX32rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 4 from %stack.1)
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 0, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV32mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADOX32rm]] :: (store 4 into %ir.4, align 1)
     ; CHECK: $al = COPY [[SETCCr]]
bb.0 (%ir-block.0):
     liveins: $edi, $rsi, $rdx, $rcx
 
     ; CHECK-LABEL: name: stack_fold_adox64
     ; CHECK: liveins: $edi, $rsi, $rdx, $rcx
     ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rcx :: (store 8 into %stack.0)
     ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
     ; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
-    ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
     ; CHECK: [[ADOX64rm:%[0-9]+]]:gr64 = ADOX64rm [[ADOX64rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 8 from %stack.1)
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 0, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV64mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADOX64rm]] :: (store 8 into %ir.4, align 1)
     ; CHECK: $al = COPY [[SETCCr]]

llvm/test/CodeGen/X86/stack-folding-bmi2.mir

 body:             |
   bb.0 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: stack_fold_mulx_u32
     ; CHECK: liveins: $edi, $esi
     ; CHECK: MOV32mr %stack.0, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
     ; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.1)
-    ; CHECK: INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 4063242 /* regdef:LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: $edx = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load 4 from %stack.1)
     ; CHECK: %3:gr32, dead %4:gr32 = MULX32rm %stack.0, 1, $noreg, 0, $noreg, implicit $edx :: (load 4 from %stack.0)
     ; CHECK: $eax = COPY %3
     ; CHECK: RET 0, $eax
     %1:gr32 = COPY $esi
     %0:gr32 = COPY $edi
     INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     $edx = COPY %0

 body:             |
   bb.0 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: stack_fold_mulx_u64
     ; CHECK: liveins: $rdi, $rsi
     ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.0)
     ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdi :: (store 8 into %stack.1)
-    ; CHECK: INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 4063242 /* regdef:LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
     ; CHECK: $rdx = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load 8 from %stack.1)
     ; CHECK: %3:gr64, dead %4:gr64 = MULX64rm %stack.0, 1, $noreg, 0, $noreg, implicit $rdx :: (load 8 from %stack.0)
     ; CHECK: $rax = COPY %3
     ; CHECK: RET 0, $rax
     %1:gr64 = COPY $rsi
     %0:gr64 = COPY $rdi
     INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     $rdx = COPY %0
     %3:gr64, dead %4:gr64 = MULX64rr %1, implicit killed $rdx
     $rax = COPY %3
     RET 0, killed $rax
 
 ...

llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir

 body:             |
   bb.0 (%ir-block.0):
     liveins: $xmm0, $xmm1
 
     ; CHECK-LABEL: name: stack_fold_addpd
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: MOVAPSmr %stack.0, 1, $noreg, 0, $noreg, $xmm1 :: (store 16 into %stack.0)
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
-    ; CHECK: INLINEASM &nop, 1, 7405578, def dead %2, 12, implicit-def dead early-clobber $xmm2, 12, implicit-def dead early-clobber $xmm3, 12, implicit-def dead early-clobber $xmm4, 12, implicit-def dead early-clobber $xmm5, 12, implicit-def dead early-clobber $xmm6, 12, implicit-def dead early-clobber $xmm7, 12, implicit-def dead early-clobber $xmm8, 12, implicit-def dead early-clobber $xmm9, 12, implicit-def dead early-clobber $xmm10, 12, implicit-def dead early-clobber $xmm11, 12, implicit-def dead early-clobber $xmm12, 12, implicit-def dead early-clobber $xmm13, 12, implicit-def dead early-clobber $xmm14, 12, implicit-def dead early-clobber $xmm15, 12, implicit-def dead early-clobber $eflags
+    ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 7405578 /* regdef:VR128 */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $xmm2, 12 /* clobber */, implicit-def dead early-clobber $xmm3, 12 /* clobber */, implicit-def dead early-clobber $xmm4, 12 /* clobber */, implicit-def dead early-clobber $xmm5, 12 /* clobber */, implicit-def dead early-clobber $xmm6, 12 /* clobber */, implicit-def dead early-clobber $xmm7, 12 /* clobber */, implicit-def dead early-clobber $xmm8, 12 /* clobber */, implicit-def dead early-clobber $xmm9, 12 /* clobber */, implicit-def dead early-clobber $xmm10, 12 /* clobber */, implicit-def dead early-clobber $xmm11, 12 /* clobber */, implicit-def dead early-clobber $xmm12, 12 /* clobber */, implicit-def dead early-clobber $xmm13, 12 /* clobber */, implicit-def dead early-clobber $xmm14, 12 /* clobber */, implicit-def dead early-clobber $xmm15, 12 /* clobber */, implicit-def dead early-clobber $eflags
     ; CHECK: [[COPY]]:vr128 = nofpexcept ADDPDrm [[COPY]], %stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 16 from %stack.0)
     ; CHECK: $xmm0 = COPY [[COPY]]
     ; CHECK: RET 0, $xmm0
     %1:vr128 = COPY $xmm1
     %3:vr128 = COPY $xmm0
     INLINEASM &nop, 1, 7405578, def dead %2, 12, implicit-def dead early-clobber $xmm2, 12, implicit-def dead early-clobber $xmm3, 12, implicit-def dead early-clobber $xmm4, 12, implicit-def dead early-clobber $xmm5, 12, implicit-def dead early-clobber $xmm6, 12, implicit-def dead early-clobber $xmm7, 12, implicit-def dead early-clobber $xmm8, 12, implicit-def dead early-clobber $xmm9, 12, implicit-def dead early-clobber $xmm10, 12, implicit-def dead early-clobber $xmm11, 12, implicit-def dead early-clobber $xmm12, 12, implicit-def dead early-clobber $xmm13, 12, implicit-def dead early-clobber $xmm14, 12, implicit-def dead early-clobber $xmm15, 12, implicit-def dead early-clobber $eflags
     %3:vr128 = nofpexcept ADDPDrr %3, %1, implicit $mxcsr
     $xmm0 = COPY %3
     RET 0, $xmm0
 
 ...