[DO NOT MERGE] added FileCheck colons that broke things

[jroelofs]

Summary

This is a series of "fixes" for missing FileCheck directive colons found by https://reviews.llvm.org/D77227 that ended up breaking the offending test. More diagnosis definitely needed.

[foad]

I have fixed some of the obvious mistakes in CodeGen/AMDGPU.

[atanasyan]

I have fixed MIPS-related mistakes at rGf22445b. Thanks for finding them.

[jroelofs]

In D77354#1959175, @foad wrote:

I have fixed some of the obvious mistakes in CodeGen/AMDGPU.

In D77354#1959542, @atanasyan wrote:

I have fixed MIPS-related mistakes at rGf22445b. Thanks for finding them.

Thank you both!

For my own reference later:

c7e1fc8496dc2c6289c803f89d7a9eae9c2cbd01
f22445bf57606ffc9914777c228936d4b3f8140d

[RKSimon]

@jroelofs please can you rebase to see what test are still broken?

[jroelofs]

Rebased

[RKSimon]

@jroelofs Please can you rebase again? I think I've dealt with all the low hanging fruit now, so you will probably have to git blame to find code owners to help fix the remaining issues.

[jroelofs]

rebased

Thanks for all the fixes everyone!

[jroelofs]

@atanasyan there's one more case of this in llvm/test/CodeGen/Mips/ci2.ll. Looks like the constant has been de-duplicated since that test was written. Mind checking whether that's correct behavior for your target? (it does seem better, but I don't want to assume).

diff --git a/llvm/test/CodeGen/Mips/ci2.ll b/llvm/test/CodeGen/Mips/ci2.ll
index 5e6b7814d5e..1b07df371eb 100644
--- a/llvm/test/CodeGen/Mips/ci2.ll
+++ b/llvm/test/CodeGen/Mips/ci2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=constisle
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands   < %s | FileCheck %s -check-prefix=CONSTISLE
 
 @i = common global i32 0, align 4
 @b = common global i32 0, align 4
@@ -24,13 +24,11 @@ if.end:                                           ; preds = %if.else, %if.then
   call void asm sideeffect ".space 100000", ""() #1, !srcloc !1
   store i32 305419896, i32* @l, align 4
   ret void
-; constisle: $CPI0_1:
-; constisle	.4byte	305419896               # 0x12345678
-; constisle	#APP
-; constisle	.space 100000
-; constisle	#NO_APP
-; constisle $CPI0_0:
-; constisle	.4byte	305419896               # 0x12345678
+; CONSTISLE: $CPI0_1:
+; CONSTISLE:    .4byte    305419896               # 0x12345678
+; CONSTISLE:    #APP
+; CONSTISLE:    .space 100000
+; CONSTISLE:    #NO_APP
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/Analysis/MemorySSA/invariant-groups.ll

 ; CHECK-NEXT: call void @clobber8(i8* %ptr)
   call void @clobber8(i8* %ptr)
 ; 6 = MemoryDef(5)
-; CHECK-NEXT  call void @use(i8* %ptr2)
+; CHECK-NEXT: call void @use(i8* %ptr2)
   call void @use(i8* %ptr2)
 ; CHECK: 7 = MemoryDef(6)
 ; CHECK-NEXT: call void @use(i8* %ptr3)

llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

   br label %block
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing:
 define void @nonpow2_add_narrowing() {

   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_add_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing:
 define void @nonpow2_or_narrowing() {

   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %1 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_load_narrowing)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %1 :: (store 12 into `i96* undef`, align 16) (in function: nonpow2_load_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing:
 define void @nonpow2_load_narrowing() {

llvm/test/CodeGen/AArch64/swap-compare-operands.ll

 ; RUN: llc < %s -mtriple=arm64 | FileCheck %s
 
 define i1 @testSwapCmpWithLSL64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithLSL64_1:
+; CHECK-LABEL: testSwapCmpWithLSL64_1:
 ; CHECK:      cmp     x1, x0, lsl #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSL64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithLSL64_63:
+; CHECK-LABEL: testSwapCmpWithLSL64_63:
 ; CHECK:      cmp     x1, x0, lsl #63
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSL32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithLSL32_1:
+; CHECK-LABEL: testSwapCmpWithLSL32_1:
 ; CHECK:      cmp     w1, w0, lsl #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSL32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithLSL32_31:
+; CHECK-LABEL: testSwapCmpWithLSL32_31:
 ; CHECK:      cmp     w1, w0, lsl #31
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSR64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithLSR64_1:
+; CHECK-LABEL: testSwapCmpWithLSR64_1:
 ; CHECK:      cmp     x1, x0, lsr #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSR64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithLSR64_63:
+; CHECK-LABEL: testSwapCmpWithLSR64_63:
 ; CHECK:      cmp     x1, x0, lsr #63
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSR32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithLSR32_1:
+; CHECK-LABEL: testSwapCmpWithLSR32_1:
 ; CHECK:      cmp     w1, w0, lsr #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithLSR32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithLSR32_31:
+; CHECK-LABEL: testSwapCmpWithLSR32_31:
 ; CHECK:      cmp     w1, w0, lsr #31
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithASR64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithASR64_1:
+; CHECK-LABEL: testSwapCmpWithASR64_1:
 ; CHECK:      cmp     x1, x0, asr #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithASR64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithASR64_63:
+; CHECK-LABEL: testSwapCmpWithASR64_63:
 ; CHECK:      cmp     x1, x0, asr #63
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithASR32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithASR32_1:
+; CHECK-LABEL: testSwapCmpWithASR32_1:
 ; CHECK:      cmp     w1, w0, asr #1
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithASR32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithASR32_31:
+; CHECK-LABEL: testSwapCmpWithASR32_31:
 ; CHECK:      cmp     w1, w0, asr #31
 ; CHECK-NEXT: cset    w0, gt
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedZeroExtend32_64(i32 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend32_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend32_64
 ; CHECK:      cmp    x1, w0, uxtw #2
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedZeroExtend16_64(i16 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend16_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_64
 ; CHECK:      cmp    x1, w0, uxth #2
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedZeroExtend8_64(i8 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_64
 ; CHECK:      cmp    x1, w0, uxtb #4
 ; CHECK-NEXT: cset    w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedZeroExtend16_32(i16 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_64
 ; CHECK:      cmp    w1, w0, uxth #3
 ; CHECK-NEXT: cset    w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedZeroExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_64
 ; CHECK:      cmp    w1, w0, uxtb #4
 ; CHECK-NEXT: cset    w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithTooLargeShiftedZeroExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithTooLargeShiftedZeroExtend8_64
+; CHECK-LABEL: testSwapCmpWithTooLargeShiftedZeroExtend8_64
 ; CHECK:      and    [[REG:w[0-9]+]], w0, #0xff
 ; CHECK:      cmp    w1, [[REG]], lsl #5
 ; CHECK-NEXT: cset   w0, lo

 }
 
 define i1 @testSwapCmpWithZeroExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithZeroExtend8_64
+; CHECK-LABEL: testSwapCmpWithZeroExtend8_64
 ; CHECK:      cmp    w1, w0, uxtb
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedSignExtend32_64(i32 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend32_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend32_64
 ; CHECK:      cmp    x1, w0, sxtw #2
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedSignExtend16_64(i16 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedZeroExtend16_64
+; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_64
 ; CHECK:      cmp    x1, w0, sxth #2
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedSignExtend8_64(i8 %a, i64 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedSignExtend8_64
 ; CHECK:      cmp    x1, w0, sxtb #4
 ; CHECK-NEXT: cset    w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedSignExtend16_32(i16 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedSignExtend8_64
 ; CHECK:      cmp    w1, w0, sxth #3
 ; CHECK-NEXT: cset    w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithShiftedSignExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithShiftedSignExtend8_64
+; CHECK-LABEL: testSwapCmpWithShiftedSignExtend8_64
 ; CHECK:      cmp    w1, w0, sxtb #4
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmpWithTooLargeShiftedSignExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithTooLargeShiftedSignExtend8_64
+; CHECK-LABEL: testSwapCmpWithTooLargeShiftedSignExtend8_64
 ; CHECK:      sxtb   [[REG:w[0-9]+]], w0
 ; CHECK-NEXT: cmp    w1, [[REG]], lsl #5
 ; CHECK-NEXT: cset   w0, lo

 }
 
 define i1 @testSwapCmpWithSignExtend8_32(i8 %a, i32 %b) {
-; CHECK-LABEL testSwapCmpWithSignExtend8_64
+; CHECK-LABEL: testSwapCmpWithSignExtend8_64
 ; CHECK:      cmp    w1, w0, sxtb
 ; CHECK-NEXT: cset   w0, lo
 entry:

 }
 
 define i1 @testSwapCmnWithLSL64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSL64_1:
+; CHECK-LABEL: testSwapCmnWithLSL64_1:
 ; CHECK:      cmn    x1, x0, lsl #1
 ; CHECK-NEXT: cset   w0, ne
 entry:

 
 ; Note: testing with a 62 bits shift as 63 has another optimization kicking in.
 define i1 @testSwapCmnWithLSL64_62(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSL64_62:
+; CHECK-LABEL: testSwapCmnWithLSL64_62:
 ; CHECK:      cmn    x1, x0, lsl #62
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithLSL64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSL64_63:
+; CHECK-LABEL: testSwapCmnWithLSL64_63:
 ; CHECK:      cmp    x1, x0, lsl #63
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i1 @testSwapCmnWithLSL32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSL32_1:
+; CHECK-LABEL: testSwapCmnWithLSL32_1:
 ; CHECK:      cmn    w1, w0, lsl #1
 ; CHECK-NEXT: cset   w0, ne
 entry:

 
 ; Note: testing with a 30 bits shift as 30 has another optimization kicking in.
 define i1 @testSwapCmnWithLSL32_30(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSL32_30:
+; CHECK-LABEL: testSwapCmnWithLSL32_30:
 ; CHECK:      cmn    w1, w0, lsl #30
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithLSL32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSL32_31:
+; CHECK-LABEL: testSwapCmnWithLSL32_31:
 ; CHECK:      cmp    w1, w0, lsl #31
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i1 @testSwapCmnWithLSR64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSR64_1:
+; CHECK-LABEL: testSwapCmnWithLSR64_1:
 ; CHECK:      cmn    x1, x0, lsr #1
 ; CHECK-NEXT: cset   w0, ne
 entry:

 
 ; Note: testing with a 62 bits shift as 63 has another optimization kicking in.
 define i1 @testSwapCmnWithLSR64_62(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSR64_62:
+; CHECK-LABEL: testSwapCmnWithLSR64_62:
 ; CHECK:      cmn    x1, x0, lsr #62
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithLSR64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithLSR64_63:
+; CHECK-LABEL: testSwapCmnWithLSR64_63:
 ; CHECK:      cmp    x1, x0, asr #63
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i1 @testSwapCmnWithLSR32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSR32_1:
+; CHECK-LABEL: testSwapCmnWithLSR32_1:
 ; CHECK:      cmn    w1, w0, lsr #1
 ; CHECK-NEXT: cset   w0, ne
 entry:

 
 ; Note: testing with a 30 bits shift as 31 has another optimization kicking in.
 define i1 @testSwapCmnWithLSR32_30(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSR32_30:
+; CHECK-LABEL: testSwapCmnWithLSR32_30:
 ; CHECK:      cmn    w1, w0, lsr #30
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithLSR32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithLSR32_31:
+; CHECK-LABEL: testSwapCmnWithLSR32_31:
 ; CHECK:      cmp    w1, w0, asr #31
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i1 @testSwapCmnWithASR64_1(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithASR64_1:
+; CHECK-LABEL: testSwapCmnWithASR64_1:
 ; CHECK:      cmn    x1, x0, asr #3
 ; CHECK-NEXT: cset   w0, ne
 entry:

 
 ; Note: testing with a 62 bits shift as 63 has another optimization kicking in.
 define i1 @testSwapCmnWithASR64_62(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithASR64_62:
+; CHECK-LABEL: testSwapCmnWithASR64_62:
 ; CHECK:      cmn    x1, x0, asr #62
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithASR64_63(i64 %a, i64 %b) {
-; CHECK-LABEL testSwapCmnWithASR64_63:
+; CHECK-LABEL: testSwapCmnWithASR64_63:
 ; CHECK:      cmp    x1, x0, lsr #63
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i1 @testSwapCmnWithASR32_1(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithASR32_1:
+; CHECK-LABEL: testSwapCmnWithASR32_1:
 ; CHECK:      cmn    w1, w0, asr #1
 ; CHECK-NEXT: cset   w0, eq
 entry:

 
 ; Note: testing with a 30 bits shift as 31 has another optimization kicking in.
 define i1 @testSwapCmnWithASR32_30(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithASR32_30:
+; CHECK-LABEL: testSwapCmnWithASR32_30:
 ; CHECK:      cmn    w1, w0, asr #30
 ; CHECK-NEXT: cset   w0, ne
 entry:

 ; so that this test can be adapted should the optimization be done with the
 ; operand swap.
 define i1 @testSwapCmnWithASR32_31(i32 %a, i32 %b) {
-; CHECK-LABEL testSwapCmnWithASR32_31:
+; CHECK-LABEL: testSwapCmnWithASR32_31:
 ; CHECK:      cmp    w1, w0, lsr #31
 ; CHECK-NEXT: cset   w0, ne
 entry:

 }
 
 define i64 @testSwapCmpToCmnWithZeroExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {
-; CHECK-LABEL testSwapCmpToCmnWithZeroExtend:
+; CHECK-LABEL: testSwapCmpToCmnWithZeroExtend:
 t0:
   %conv0 = zext i32 %a32 to i64
   %shl0 = shl i64 %conv0, 1

   ret i64 1
 }
 define i64 @testSwapCmpToCmnWithSignExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {
-; CHECK-LABEL testSwapCmpToCmnWithSignExtend:
+; CHECK-LABEL: testSwapCmpToCmnWithSignExtend:
 t0:
   %conv0 = sext i32 %a32 to i64
   %shl0 = shl i64 %conv0, 1

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir

   bb.0:
     liveins: $sgpr0_sgpr1
     ; CHECK-LABEL: name: load_constant_v8i32_uniform
-    ; CHECK (<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4)
+    ; CHECK: (<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4)
     %0:_(p4) = COPY $sgpr0_sgpr1
     %1:_(<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4)
 ...

   bb.0:
     liveins: $sgpr0_sgpr1
     ; CHECK-LABEL: name: load_constant_v4i64_uniform
-    ; CHECK (<4 x s64>) = G_LOAD %0 :: (load 32, addrspace 4)
+    ; CHECK: (<4 x s64>) = G_LOAD %0 :: (load 32, addrspace 4)
     %0:_(p4) = COPY $sgpr0_sgpr1
     %1:_(<4 x s64>) = G_LOAD %0 :: (load 32, addrspace 4)
 ...

   bb.0:
     liveins: $sgpr0_sgpr1
     ; CHECK-LABEL: name: load_constant_v16i32_uniform
-    ; CHECK (<16 x s32>) = G_LOAD %0 :: (load 64, addrspace 4)
+    ; CHECK: (<16 x s32>) = G_LOAD %0 :: (load 64, addrspace 4)
     %0:_(p4) = COPY $sgpr0_sgpr1
     %1:_(<16 x s32>) = G_LOAD %0 :: (load 64, addrspace 4)
 ...

   bb.0:
     liveins: $sgpr0_sgpr1
     ; CHECK-LABEL: name: load_constant_v8i64_uniform
-    ; CHECK (<8 x s64>) = G_LOAD %0 :: (load 64, addrspace 4)
+    ; CHECK: (<8 x s64>) = G_LOAD %0 :: (load 64, addrspace 4)
     %0:_(p4) = COPY $sgpr0_sgpr1
     %1:_(<8 x s64>) = G_LOAD %0 :: (load 64, addrspace 4)
 ...

llvm/test/CodeGen/AMDGPU/fmin_legacy.ll

 
 ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
 
-; VI-SAFE v_cmp_le_f32_e32 vcc, [[A]], [[B]]
+; VI-SAFE: v_cmp_le_f32_e32 vcc, [[A]], [[B]]
 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
 
 ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]

 
 ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]
 
-; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
+; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
 
 ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]

 
 ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 
-; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
+; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
 
 ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]

 
 ; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]
 
-; VI-SAFE v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
+; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]
 ; VI-SAFE: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
 
 ; GCN-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]

 ; SI-SAFE: v_min_legacy_f32_e32
 ; SI-SAFE: v_min_legacy_f32_e32
 
-; VI-SAFE v_cmp_lt_f32_e32
+; VI-SAFE: v_cmp_lt_f32_e32
 ; VI-SAFE: v_cndmask_b32_e32
-; VI-SAFE v_cmp_lt_f32_e32
+; VI-SAFE: v_cmp_lt_f32_e32
 ; VI-SAFE: v_cndmask_b32_e32
 
 ; GCN-NONAN: v_min_f32_e32

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll

 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x80000{{$}}
 ; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
 
-; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; CI: s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
 
-; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; VI: s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
 define amdgpu_ps i32 @s_buffer_load_imm_bit19(<4 x i32> inreg %desc) {
   %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 524288, i32 0)
   ret i32 %load

 ; SI: s_mov_b32 [[K:s[0-9]+]], 0xfff80000{{$}}
 ; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
 
-; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; CI: s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
 
-; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; VI: s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
 define amdgpu_ps i32 @s_buffer_load_imm_neg_bit19(<4 x i32> inreg %desc) {
   %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -524288, i32 0)
   ret i32 %load

llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir

 ---
 # GCN-LABEL: name: shrink_addc_vop3{{$}}
 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
-# GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
+# GCN: %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
 
 name:            shrink_addc_vop3
 alignment:       1

llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll

 ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
 
 ; CHECK-LABEL: {{^}}test:
-; CHECK s_and_saveexec_b64
-; CHECK s_xor_b64
-; CHECK s_or_b64 exec, exec
-; CHECK s_andn2_b64 exec, exec
-; CHECK s_cbranch_execnz
+; CHECK: s_and_saveexec_b64
+; CHECK: s_xor_b64
+; CHECK: s_or_b64 exec, exec
+; CHECK: s_andn2_b64 exec, exec
+; CHECK: s_cbranch_execnz
 define amdgpu_kernel void @test(i32 %arg, i32 %arg1) {
 bb:
   %tmp = icmp ne i32 %arg, 0

llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll

 
 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
 
-; FUNC-LABEL {{^}}sextload_i1_to_i32_trunc_cmp_eq_0:
+; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_eq_0:
 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
 ; SI: v_cmp_eq_u32_e32 vcc, 0, [[TMP]]{{$}}

 }
 
 
-; FUNC-LABEL {{^}}sextload_i1_to_i32_trunc_cmp_ne_0:
+; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_ne_0:
 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
 ; SI: buffer_store_byte [[RESULT]]

llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

 ; No dynamic indexing required
 ; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4i32:
 ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}}
-; GCN-NOT buffer_load_dword
+; GCN-NOT: buffer_load_dword
 ; GCN-NOT: [[VAL]]
 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
 ; GCN-NOT: [[VVAL]]

 
 ; GCN-LABEL: {{^}}extract_insert_same_elt2_v4i32:
 ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}}
-; GCN-NOT buffer_load_dword
+; GCN-NOT: buffer_load_dword
 ; GCN-NOT: [[VAL]]
 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
 ; GCN-NOT: [[VVAL]]

 
 ; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4f32:
 ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}}
-; GCN-NOT buffer_load_dword
+; GCN-NOT: buffer_load_dword
 ; GCN-NOT: [[VAL]]
 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
 ; GCN-NOT: [[VVAL]]

llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir

 # CHECK_SWIFT: Latency    : 3
 # CHECK_R52:   Latency    : 4
 #
-# CHECK :      SU(6):   %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
+# CHECK:       SU(6):   %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3

llvm/test/CodeGen/ARM/thumb1_return_sequence.ll

 ; CHECK-V4T-NEXT:    ldr [[POP:r[4567]]], [sp, #16]
 ; CHECK-V4T-NEXT:    mov lr, [[POP]]
 ; CHECK-V4T-NEXT:    pop {[[SAVED]]}
-; CHECK-V4T-NEXT     add sp, sp, #4
+; CHECK-V4T-NEXT:    add sp, sp, #4
 ; The ISA for v4 does not support pop pc, so make sure we do not emit
 ; one even when we do not need to update SP.
 ; CHECK-V4T-NOT:     pop {pc}

 ; used for the return value).
 ; CHECK-V4T-NEXT:    pop {[[POP_REG:r[1-3]]]}
 ; CHECK-V4T-NEXT:    bx [[POP_REG]]
-; CHECK-V5T:    pop {[[SAVED]], pc}
+; CHECK-V5T:         pop {[[SAVED]], pc}
 }
 
 ; CHECK-V4T-LABEL: simplevariadicframe

llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir

 
 ---
 name: testIndexForm1
-#CHECK : name : testIndexForm1
+#CHECK-LABEL: name : testIndexForm1
 # ToBeDeletedReg equals to ScaleReg
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm2
-#CHECK : name : testIndexForm2
+#CHECK-LABEL: name : testIndexForm2
 # ToBeDeletedReg equals to ToBeChangedReg
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm3
-#CHECK : name : testIndexForm3
+#CHECK-LABEL: name : testIndexForm3
 # There is other use for ToBeDeletedReg between ADD instr and Imm instr
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm4
-#CHECK : name : testIndexForm3
+#CHECK-LABEL: name : testIndexForm3
 # There is other use for ToBeChangedReg between ADDI instr and ADD instr
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm5
-#CHECK : name : testIndexForm5
+#CHECK-LABEL: name : testIndexForm5
 # ToBeChangedReg has no killed flag
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm6
-#CHECK : name : testIndexForm6
+#CHECK-LABEL: name : testIndexForm6
 # ToBeDeletedReg has no killed flag
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm7
-#CHECK : name : testIndexForm7
+#CHECK-LABEL: name : testIndexForm7
 # There is other def for ToBeChangedReg between ADD instr and Imm instr
 tracksRegLiveness: true
 body: |

 ...
 ---
 name: testIndexForm8
-#CHECK : name : testIndexForm8
+#CHECK-LABEL: name : testIndexForm8
 # There is other def for ScaleReg between ADD instr and Imm instr
 tracksRegLiveness: true
 body: |

llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

 
 ---
 name: testFoldRLWINM
-#CHECK : name : testFoldRLWINM
+#CHECK-LABEL: name : testFoldRLWINM
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMSrcFullMask1
-#CHECK : name : testFoldRLWINMSrcFullMask1
+#CHECK-LABEL: name : testFoldRLWINMSrcFullMask1
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMSrcFullMask2
-#CHECK : name : testFoldRLWINMSrcFullMask2
+#CHECK-LABEL: name : testFoldRLWINMSrcFullMask2
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMSrcWrapped
-#CHECK : name : testFoldRLWINMSrcWrapped
+#CHECK-LABEL: name : testFoldRLWINMSrcWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMUserWrapped
-#CHECK : name : testFoldRLWINMUserWrapped
+#CHECK-LABEL: name : testFoldRLWINMUserWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMResultWrapped
-#CHECK : name : testFoldRLWINMResultWrapped
+#CHECK-LABEL: name : testFoldRLWINMResultWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMMultipleUses
-#CHECK : name : testFoldRLWINMMultipleUses
+#CHECK-LABEL: name : testFoldRLWINMMultipleUses
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMToZero
-#CHECK : name : testFoldRLWINMToZero
+#CHECK-LABEL: name : testFoldRLWINMToZero
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINM_recToZero
-#CHECK : name : testFoldRLWINM_recToZero
+#CHECK-LABEL: name : testFoldRLWINM_recToZero
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMoToZeroSrcCanNotBeDeleted
-#CHECK : name : testFoldRLWINMoToZeroSrcCanNotBeDeleted
+#CHECK-LABEL: name : testFoldRLWINMoToZeroSrcCanNotBeDeleted
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 ...
 ---
 name: testFoldRLWINMInvalidMask
-#CHECK : name : testFoldRLWINMInvalidMask
+#CHECK-LABEL: name : testFoldRLWINMInvalidMask
 tracksRegLiveness: true
 body: |
   bb.0.entry:

llvm/test/CodeGen/PowerPC/optcmp.ll

 ; CHECK: isel 3, 4, 3, 1
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b .LBB
-; CHECK-NO-ISEL addi: 3, 4, 0
+; CHECK-NO-ISEL: addi: 3, 4, 0
 ; CHECK: std [[REG]], 0(5)
 }
 

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

 ; PC64-NEXT:    ld 0, 16(1)
 ; PC64-NEXT:    mtlr 0
 ; PC64-NEXT:    blr
-; PC64LE9     :    clrldi 5, 5, 32
+; PC64LE9:      clrldi 5, 5, 32
 entry:
   %powi = call ppc_fp128 @llvm.experimental.constrained.powi.ppcf128(
                     ppc_fp128 %first,

llvm/test/CodeGen/X86/GlobalISel/select-copy.mir

 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL           %0:gr8 = COPY $al
-# ALL-NEXT      %1:gr32 = MOVZX32rr8 %0
-# ALL-NEXT      $eax = COPY %1
-# ALL-NEXT      RET 0, implicit $eax
+# ALL:           %0:gr8 = COPY $al
+# ALL-NEXT:      %1:gr32 = MOVZX32rr8 %0
+# ALL-NEXT:      $eax = COPY %1
+# ALL-NEXT:      RET 0, implicit $eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $eax

   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
-# ALL           %0:gr16 = COPY $ax
-# ALL-NEXT      %1:gr8 = COPY %0.sub_8bit
-# ALL-NEXT      %2:gr32 = MOVZX32rr8 %1
-# ALL-NEXT      $eax = COPY %2
-# ALL-NEXT      RET 0, implicit $eax
+# ALL:           %0:gr16 = COPY $ax
+# ALL-NEXT:      %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:      %2:gr32 = MOVZX32rr8 %1
+# ALL-NEXT:      $eax = COPY %2
+# ALL-NEXT:      RET 0, implicit $eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $eax

   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
-# ALL           %0:gr32 = COPY $eax
-# ALL-NEXT      %1:gr16 = COPY %0.sub_16bit
-# ALL-NEXT      %2:gr32 = MOVZX32rr16 %1
-# ALL-NEXT      $eax = COPY %2
-# ALL-NEXT      RET 0, implicit $eax
+# ALL:           %0:gr32 = COPY $eax
+# ALL-NEXT:      %1:gr16 = COPY %0.sub_16bit
+# ALL-NEXT:      %2:gr32 = MOVZX32rr16 %1
+# ALL-NEXT:      $eax = COPY %2
+# ALL-NEXT:      RET 0, implicit $eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $eax

   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
-# ALL           %0:gr32[[ABCD]] = COPY $edx
-# ALL-NEXT      %1:gr8 = COPY %0.sub_8bit
-# ALL-NEXT      %2:gr32 = MOVZX32rr8 %1
-# ALL-NEXT      $eax = COPY %2
-# ALL-NEXT      RET 0, implicit $eax
+# ALL:           %0:gr32[[ABCD]] = COPY $edx
+# ALL-NEXT:      %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:      %2:gr32 = MOVZX32rr8 %1
+# ALL-NEXT:      $eax = COPY %2
+# ALL-NEXT:      RET 0, implicit $eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $eax,$edx

llvm/test/CodeGen/X86/emutls.ll

 
 ;;;;;;;;;;;;;; 32-bit __emutls_v. and __emutls_t.
 
-; X32       .section .data.rel.local,
+; X32:      .section .data.rel.local,
 ; X32-LABEL: __emutls_v.i1:
 ; X32-NEXT: .long 4
 ; X32-NEXT: .long 4
 ; X32-NEXT: .long 0
 ; X32-NEXT: .long __emutls_t.i1
 
-; X32       .section .rodata,
+; X32:      .section .rodata,
 ; X32-LABEL: __emutls_t.i1:
 ; X32-NEXT: .long 15
 
 ; X32-NOT:   __emutls_v.i2
 
-; X32       .section .data.rel.local,
+; X32:      .section .data.rel.local,
 ; X32-LABEL: __emutls_v.i3:
 ; X32-NEXT: .long 4
 ; X32-NEXT: .long 4
 ; X32-NEXT: .long 0
 ; X32-NEXT: .long __emutls_t.i3
 
-; X32       .section .rodata,
+; X32:      .section .rodata,
 ; X32-LABEL: __emutls_t.i3:
 ; X32-NEXT: .long 15
 
-; X32       .section .data.rel.local,
+; X32:      .section .data.rel.local,
 ; X32-LABEL: __emutls_v.i4:
 ; X32-NEXT: .L__emutls_v.i4$local:
 ; X32-NEXT: .long 4

 ; X32-NEXT: .long 0
 ; X32-NEXT: .long __emutls_t.i4
 
-; X32       .section .rodata,
+; X32:      .section .rodata,
 ; X32-LABEL: __emutls_t.i4:
 ; X32-NEXT: .L__emutls_t.i4$local:
 ; X32-NEXT: .long 15
 
 ; X32-NOT:   __emutls_v.i5:
-; X32       .hidden __emutls_v.i5
+; X32:      .hidden __emutls_v.i5
 ; X32-NOT:   __emutls_v.i5:
 
-; X32 .section .data.rel.local,
+; X32: .section .data.rel.local,
 ; X32-LABEL: __emutls_v.s1:
 ; X32-NEXT: .long 2
 ; X32-NEXT: .long 2
 ; X32-NEXT: .long 0
 ; X32-NEXT: .long __emutls_t.s1
 
-; X32 .section .rodata,
+; X32: .section .rodata,
 ; X32-LABEL: __emutls_t.s1:
 ; X32-NEXT: .short 15
 
-; X32 .section .data.rel.local,
+; X32: .section .data.rel.local,
 ; X32-LABEL: __emutls_v.b1:
 ; X32-NEXT: .long 1
 ; X32-NEXT: .long 1

 
 ;;;;;;;;;;;;;; 64-bit __emutls_v. and __emutls_t.
 
-; X64       .section .data.rel.local,
+; X64:      .section .data.rel.local,
 ; X64-LABEL: __emutls_v.i1:
 ; X64-NEXT: .quad 4
 ; X64-NEXT: .quad 4
 ; X64-NEXT: .quad 0
 ; X64-NEXT: .quad __emutls_t.i1
 
-; X64       .section .rodata,
+; X64:      .section .rodata,
 ; X64-LABEL: __emutls_t.i1:
 ; X64-NEXT: .long 15
 
 ; X64-NOT:   __emutls_v.i2
 
-; X64       .section .data.rel.local,
+; X64:      .section .data.rel.local,
 ; X64-LABEL: __emutls_v.i3:
 ; X64-NEXT: .quad 4
 ; X64-NEXT: .quad 4
 ; X64-NEXT: .quad 0
 ; X64-NEXT: .quad __emutls_t.i3
 
-; X64       .section .rodata,
+; X64:      .section .rodata,
 ; X64-LABEL: __emutls_t.i3:
 ; X64-NEXT: .long 15
 
-; X64       .section .data.rel.local,
+; X64:      .section .data.rel.local,
 ; X64-LABEL: __emutls_v.i4:
 ; X64-NEXT: .L__emutls_v.i4$local:
 ; X64-NEXT: .quad 4

 ; X64-NEXT: .quad 0
 ; X64-NEXT: .quad __emutls_t.i4
 
-; X64       .section .rodata,
+; X64:      .section .rodata,
 ; X64-LABEL: __emutls_t.i4:
 ; X64-NEXT: .L__emutls_t.i4$local:
 ; X64-NEXT: .long 15
 
 ; X64-NOT:   __emutls_v.i5:
-; X64       .hidden __emutls_v.i5
+; X64:       .hidden __emutls_v.i5
 ; X64-NOT:   __emutls_v.i5:
 
-; X64       .section .data.rel.local,
+; X64:      .section .data.rel.local,
 ; X64-LABEL: __emutls_v.s1:
 ; X64-NEXT: .quad 2
 ; X64-NEXT: .quad 2
 ; X64-NEXT: .quad 0
 ; X64-NEXT: .quad __emutls_t.s1
 
-; X64       .section .rodata,
+; X64:      .section .rodata,
 ; X64-LABEL: __emutls_t.s1:
 ; X64-NEXT: .short 15
 
-; X64       .section .data.rel.local,
+; X64:      .section .data.rel.local,
 ; X64-LABEL: __emutls_v.b1:
 ; X64-NEXT: .quad 1
 ; X64-NEXT: .quad 1

llvm/test/CodeGen/X86/linux-preemption.ll

 define i32* @get_weak_preemptable_global() {
   ret i32* @weak_preemptable_global
 }
-; CHECK ;ADD_LABEL_BACK;  movq weak_preemptable_global@GOTPCREL(%rip), %rax
-; STATIC ;ADD_LABEL_BACK; movq weak_preemptable_global@GOTPCREL, %rax
-; CHECK32 ;ADD_LABEL_BACK; movl weak_preemptable_global@GOT(%eax), %eax
+; CHECK: ADD_LABEL_BACK;  movq weak_preemptable_global@GOTPCREL(%rip), %rax
+; STATIC: ADD_LABEL_BACK; movq weak_preemptable_global@GOTPCREL, %rax
+; CHECK32: ADD_LABEL_BACK; movl weak_preemptable_global@GOT(%eax), %eax
 
 @external_preemptable_global = external dso_preemptable global i32
 define i32* @get_external_preemptable_global() {

   ret void()* @strong_local_function
 }
 ; COMMON:     {{^}}strong_local_function:
-; COMMON-NEXT .Lstrong_local_function:
+; COMMON-NEXT: .Lstrong_local_function:
 ; CHECK: leaq .Lstrong_local_function$local(%rip), %rax
 ; STATIC: movl $.Lstrong_local_function$local, %eax
 ; CHECK32: leal .Lstrong_local_function$local@GOTOFF(%eax), %eax

 ; CHECK32: movl external_preemptable_function@GOT(%eax), %eax
 
 ; COMMON:     {{^}}strong_local_global:
-; COMMON-NEXT .Lstrong_local_global:
+; COMMON-NEXT: .Lstrong_local_global:
 
 ; COMMON:      .globl strong_default_alias
 ; COMMON-NEXT: .set strong_default_alias, aliasee

llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll

   %res = select i1 %cmp, fp128 %sub, fp128 0xL00000000000000000000000000000000
   ret fp128 %res
 ; CHECK-LABEL: TestSelect:
-; CHECK        movaps 16(%rsp), %xmm1
-; CHECK-NEXT   callq __subtf3
-; CHECK-NEXT   testl %ebx, %ebx
-; CHECK-NEXT   jg .LBB0_2
-; CHECK-NEXT # %bb.1:
-; CHECK-NEXT   movaps .LCPI0_0(%rip), %xmm0
-; CHECK-NEXT .LBB0_2:
-; CHECK-NEXT   addq $32, %rsp
-; CHECK-NEXT   popq %rbx
-; CHECK-NEXT   retq
+; CHECK:        movaps 16(%rsp), %xmm1
+; CHECK-NEXT:   callq __subtf3
+; CHECK-NEXT:   testl %ebx, %ebx
+; CHECK-NEXT:   jg .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT:   movaps .LCPI0_0(%rip), %xmm0
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT:   addq $32, %rsp
+; CHECK-NEXT:   popq %rbx
+; CHECK-NEXT:   retq
 }
 
 define fp128 @TestFabs(fp128 %a) {
   %res = call fp128 @llvm.fabs.f128(fp128 %a)
   ret fp128 %res
 ; CHECK-LABEL: TestFabs:
-; CHECK      andps .LCPI1_0(%rip), %xmm0
-; CHECK-NEXT retq
+; CHECK:      andps .LCPI1_0(%rip), %xmm0
+; CHECK-NEXT: retq
 }
 
 define fp128 @TestCopysign(fp128 %a, fp128 %b) {
   %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b)
   ret fp128 %res
 ; CHECK-LABEL: TestCopysign:
-; CHECK      andps .LCPI2_1(%rip), %xmm0
-; CHECK-NEXT orps %xmm1, %xmm0
-; CHECK-NEXT retq
+; CHECK:      andps .LCPI2_1(%rip), %xmm0
+; CHECK-NEXT: orps %xmm1, %xmm0
+; CHECK-NEXT: retq
 }
 
 define fp128 @TestFneg(fp128 %a) {

   %res = fsub fp128 0xL00000000000000008000000000000000, %mul
   ret fp128 %res
 ; CHECK-LABEL: TestFneg:
-; CHECK      movaps %xmm0, %xmm1
-; CHECK-NEXT callq __multf3
-; CHECK-NEXT xorps .LCPI3_0(%rip), %xmm0
-; CHECK-NEXT popq %rax
-; CHECK-NEXT retq
+; CHECK:      movaps %xmm0, %xmm1
+; CHECK-NEXT: callq __multf3
+; CHECK-NEXT: xorps .LCPI3_0(%rip), %xmm0
+; CHECK-NEXT: popq %rax
+; CHECK-NEXT: retq
 }

llvm/test/CodeGen/X86/stack-clash-medium-natural-probes-mutliple-objects.ll

 
 ; CHECK-LABEL: foo:
 ; CHECK:         # %bb.0:
-; CHECK-NEXT  subq  $4096, %rsp # imm = 0x1000
-; CHECK-NEXT  .cfi_def_cfa_offset 5888
-; CHECK-NEXT  movl  $1, 2088(%rsp)
-; CHECK-NEXT  subq  $1784, %rsp # imm = 0x6F8
-; CHECK-NEXT  movl  $2, 672(%rsp)
-; CHECK-NEXT  movl  1872(%rsp), %eax
-; CHECK-NEXT  addq  $5880, %rsp # imm = 0x16F8
-; CHECK-NEXT  .cfi_def_cfa_offset 8
-; CHECK-NEXT  retq
+; CHECK-NEXT: subq  $4096, %rsp # imm = 0x1000
+; CHECK-NEXT: .cfi_def_cfa_offset 5888
+; CHECK-NEXT: movl  $1, 2088(%rsp)
+; CHECK-NEXT: subq  $1784, %rsp # imm = 0x6F8
+; CHECK-NEXT: movl  $2, 672(%rsp)
+; CHECK-NEXT: movl  1872(%rsp), %eax
+; CHECK-NEXT: addq  $5880, %rsp # imm = 0x16F8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 
 
   %a = alloca i32, i64 1000, align 16

llvm/test/MC/Mips/mips32r2/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.

llvm/test/MC/Mips/mips32r3/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.

llvm/test/MC/Mips/mips32r5/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.

llvm/test/MC/Mips/mips32r6/valid.s

         not       $3             # CHECK: not $3, $3             # encoding: [0x00,0x60,0x18,0x27]
         pause                    # CHECK: pause                  # encoding:  [0x00,0x00,0x01,0x40]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} PAUSE
-                                 # CHECK-NOT                     # <MCInst #{{[0-9}+}} PAUSE_MM
+                                 # CHECK-NOT:                    # <MCInst #{{[0-9}+}} PAUSE_MM
         pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]
                                  # CHECK-NEXT:                   # <MCInst #{{.*}} PREF_R6
         # FIXME: Use the code generator in order to print the .set directives

llvm/test/MC/Mips/mips64r2/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pll.ps  $f26,$f10,$f30         # CHECK: pll.ps $f26, $f10, $f30  # encoding: [0x46,0xde,0x56,0xac]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLL_PS64
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]

llvm/test/MC/Mips/mips64r3/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pll.ps  $f26,$f10,$f30         # CHECK: pll.ps $f26, $f10, $f30  # encoding: [0x46,0xde,0x56,0xac]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLL_PS64
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]

llvm/test/MC/Mips/mips64r5/valid.s

         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
                                        # CHECK-NEXT:  # <MCInst #{{[0-9]+}} PAUSE
-                                       # CHECK-NOT    # <MCInst #{{[0-9}+}} PAUSE_MM
+                                       # CHECK-NOT:   # <MCInst #{{[0-9}+}} PAUSE_MM
         pll.ps  $f26,$f10,$f30         # CHECK: pll.ps $f26, $f10, $f30  # encoding: [0x46,0xde,0x56,0xac]
                                        # CHECK:                          # <MCInst #{{[0-9]+}} PLL_PS64
         plu.ps  $f2,$f26,$f30          # CHECK: plu.ps $f2, $f26, $f30    # encoding: [0x46,0xde,0xd0,0xad]

llvm/test/MC/Mips/mips64r6/valid.s

         or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         pause                    # CHECK: pause                  # encoding:  [0x00,0x00,0x01,0x40]
                                  # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} PAUSE
-                                 # CHECK-NOT                     # <MCInst #{{[0-9}+}} PAUSE_MM
+                                 # CHECK-NOT:                    # <MCInst #{{[0-9}+}} PAUSE_MM
         pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]
         # FIXME: Use the code generator in order to print the .set directives
         #        instead of the instruction printer.

llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll

   ret void
 }
 
-; CHECK-LABEL define internal void @_Z3foo_unknown_calli.1_bb3
+; CHECK-LABEL: define internal void @_Z3foo_unknown_calli.1_bb3
 ; CHECK: newFuncRoot:
 ; CHECK-NEXT: br label %bb3
 

llvm/test/Transforms/InstCombine/phi-preserve-ir-flags.ll

 
 ; The fast-math flags should always be transfered if possible.
 ; CHECK-LABEL: cond.end
-; CHECK  [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
-; CHECK  fsub fast float %a, [[PHI]]
+; CHECK:  [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
+; CHECK:  fsub fast float %a, [[PHI]]
 cond.end:
   %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
   ret float %e

 
 ; The fast-math flags should always be transfered if possible.
 ; CHECK-LABEL: cond.end
-; CHECK  [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
-; CHECK  fsub float %a, [[PHI]]
+; CHECK:  [[PHI:%[^ ]*]] = phi float [ %b, %cond.true ], [ %c, %cond.false ]
+; CHECK:  fsub float %a, [[PHI]]
 cond.end:
   %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
   ret float %e

   br label %cond.end
 
 ; CHECK-LABEL: cond.end
-; CHECK  [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
-; CHECK  fadd fast float %a, [[PHI]]
+; CHECK:  [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+; CHECK:  fadd fast float %a, [[PHI]]
 cond.end:
   %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
   ret float %e

   br label %cond.end
 
 ; CHECK-LABEL: cond.end
-; CHECK  [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
-; CHECK  fadd float %a, [[PHI]]
+; CHECK:  [[PHI:%[^ ]*]] = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+; CHECK:  fadd float %a, [[PHI]]
 cond.end:
   %e = phi float [ %sub0, %cond.true ], [ %sub1, %cond.false ]
   ret float %e

llvm/test/Transforms/InstSimplify/compare.ll

 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8* [[X]], null
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
-; CHECK getelementptr inbounds i8, i8* %ptr, i32 %b
+; CHECK: getelementptr inbounds i8, i8* %ptr, i32 %b
   %b = or i32 %a, 1
   %x = getelementptr inbounds i8, i8* %ptr, i32 %b
   %cmp = icmp eq i8* %x, null

llvm/test/Transforms/LoopRotate/pr35210.ll

 
 
 ; CHECK-LABEL: define i8 @f() {
-; CHECK-NEXT : entry:
-; CHECK-NEXT :   br label %bb
-; CHECK-NEXT :
-; CHECK-NEXT : bb:                                               ; preds = %bb, %entry
-; CHECK-NEXT :   %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb ]
-; CHECK-NEXT :   %tmp5 = icmp eq i8 %mode.0, 1
-; CHECK-NEXT :   %indvar.next = add i8 %mode.0, 1
-; CHECK-NEXT :   br i1 %tmp5, label %bb5, label %bb
-; CHECK-NEXT :
-; CHECK-NEXT : bb5:                                              ; preds = %bb
-; CHECK-NEXT :   tail call void @raise_exception() #0
-; CHECK-NEXT :   unreachable
-; CHECK-NEXT : }
-; CHECK-NEXT :
-; CHECK-NEXT : ; Function Attrs: noreturn
-; CHECK-NEXT : declare void @raise_exception() #0
-; CHECK-NEXT :
-; CHECK-NEXT : attributes #0 = { noreturn }
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label %bb
+; CHECK-NEXT:  bb:                                               ; preds = %bb, %entry
+; CHECK-NEXT:    %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb ]
+; CHECK-NEXT:    %tmp5 = icmp eq i8 %mode.0, 1
+; CHECK-NEXT:    %indvar.next = add i8 %mode.0, 1
+; CHECK-NEXT:    br i1 %tmp5, label %bb5, label %bb
+; CHECK-NEXT:  bb5:                                              ; preds = %bb
+; CHECK-NEXT:    tail call void @raise_exception() #0
+; CHECK-NEXT:    unreachable
+; CHECK-NEXT:  }
+; CHECK-NEXT:  ; Function Attrs: noreturn
+; CHECK-NEXT:  declare void @raise_exception() #0
+; CHECK-NEXT:
+; CHECK-NEXT:  attributes #0 = { noreturn }
 
 ; MSSA-LABEL: define i8 @f() {
-; MSSA-NEXT : entry:
-; MSSA-NEXT :   br label %bb
-; MSSA-NEXT :
-; MSSA-NEXT : bb:                                               ; preds = %bb, %entry
-; MSSA-NEXT :   %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb ]
-; MSSA-NEXT :   %tmp5 = icmp eq i8 %mode.0, 1
-; MSSA-NEXT :   %indvar.next = add i8 %mode.0, 1
-; MSSA-NEXT :   br i1 %tmp5, label %bb5, label %bb
-; MSSA-NEXT :
-; MSSA-NEXT : bb5:                                              ; preds = %bb
-; MSSA-NEXT :   tail call void @raise_exception() #0
-; MSSA-NEXT :   unreachable
-; MSSA-NEXT : }
-; MSSA-NEXT :
-; MSSA-NEXT : ; Function Attrs: noreturn
-; MSSA-NEXT : declare void @raise_exception() #0
-; MSSA-NEXT :
-; MSSA-NEXT : attributes #0 = { noreturn }
+; MSSA-NEXT:  entry:
+; MSSA-NEXT:    br label %bb
+; MSSA-NEXT:  bb:                                               ; preds = %bb, %entry
+; MSSA-NEXT:    %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb ]
+; MSSA-NEXT:    %tmp5 = icmp eq i8 %mode.0, 1
+; MSSA-NEXT:    %indvar.next = add i8 %mode.0, 1
+; MSSA-NEXT:    br i1 %tmp5, label %bb5, label %bb
+; MSSA-NEXT:  bb5:                                              ; preds = %bb
+; MSSA-NEXT:    tail call void @raise_exception() #0
+; MSSA-NEXT:    unreachable
+; MSSA-NEXT:  }
+; MSSA-NEXT:  ; Function Attrs: noreturn
+; MSSA-NEXT:  declare void @raise_exception() #0
+; MSSA-NEXT:  attributes #0 = { noreturn }
 
 define i8 @f() {
 entry:

llvm/test/Transforms/SampleProfile/gcc-simple.ll

   ret i32 %cond, !dbg !71
 }
 
-; CHECK ![[EC1]] = !{!"function_entry_count", i64 24108}
-; CHECK ![[PROF1]] = !{!"branch_weights", i32 1, i32 30124}
-; CHECK ![[PROF2]] = !{!"branch_weights", i32 30177, i32 29579}
-; CHECK ![[EC2]] = !{!"function_entry_count", i64 0}
-; CHECK ![[PROF3]] = !{!"branch_weights", i32 1, i32 1}
-; CHECK ![[PROF4]] = !{!"branch_weights", i32 1, i32 20238}
+; CHECK: ![[EC1]] = !{!"function_entry_count", i64 24108}
+; CHECK: ![[PROF1]] = !{!"branch_weights", i32 1, i32 30124}
+; CHECK: ![[PROF2]] = !{!"branch_weights", i32 30177, i32 29579}
+; CHECK: ![[EC2]] = !{!"function_entry_count", i64 0}
+; CHECK: ![[PROF3]] = !{!"branch_weights", i32 1, i32 1}
+; CHECK: ![[PROF4]] = !{!"branch_weights", i32 1, i32 20238}
 
 attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind readnone }

llvm/test/tools/dsymutil/X86/modules.m

 //
 // CHECK: 0x{{0*}}[[PTR]]: DW_TAG_pointer_type
 // FIXME: The next line doesn't work.
-// CHECK-NEXT   DW_AT_type [DW_FORM_ref_addr] {0x{{0*}}[[INTERFACE]]
+// CHECK-NEXT:  DW_AT_type [DW_FORM_ref_addr] {0x{{0*}}[[INTERFACE]]
 extern int odr_violation;
 
 @import Foo;