[DAGCombine] Add basic optimizations for FREEZE in SelDag

[aqjune]

Summary

This patch is the first effort to adding basic optimizations for FREEZE in SelDag.

[aqjune]

Minor fix

[spatel]

This patch should include test improvement diffs after D29014?

[xbolva00]

Tests?

[aqjune]

Update changes to fastisel & legalize tests

[aqjune]

In D76707#1939393, @xbolva00 wrote:

Tests?

Would having the changes to the two test files be sufficient?

[lebedev.ri]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

11593

Why are we creating a new freeze x when we already have freeze x in the form of N0?
(if it's due to the freeze semantics, please explain that in the code comment)

[aqjune]

Don't create a redundant instruction

[aqjune]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

11593

You're right, it is fine to return N0. It was there because I was watching implementation of visitBITCAST.

[aqjune]

BTW, I tried to write a unit test that checks the freeze(freeze) -> freeze folding, but simply making llc print assembly wasn't enough to distinguish its effect. Is there a commandline option that prints SelDag just after dagcombiner?

[spatel]

In D76707#1939525, @aqjune wrote:

BTW, I tried to write a unit test that checks the freeze(freeze) -> freeze folding, but simply making llc print assembly wasn't enough to distinguish its effect. Is there a commandline option that prints SelDag just after dagcombiner?

You could try something like "-stop-before=finalize-isel" and then check the MIR for an extra COPY instruction.
See llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll for an example of that type of regression test.

[aqjune]

Add freeze-combine.ll

[aqjune]

Thank you, I added a test.

llvm/test/CodeGen/X86/freeze-combine.ll

18

This COPY seems to appear regardless of how many freezes are nested.

[spatel]

LGTM - I'm not sure if we should also do these folds in SelectionDAGBuilder / getNode(), but that can be another patch if needed.

llvm/include/llvm/CodeGen/SelectionDAG.h

#endif
   /// Return a bitcast using the SDLoc of the value operand, and casting to the
   /// provided type. Use getNode to set a custom SDLoc.
   SDValue getBitcast(EVT VT, SDValue V);
 
   /// Return an AddrSpaceCastSDNode.
   SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS,
                            unsigned DestAS);
 
+  /// Return a freeze using the SDLoc of the value operand.
+  SDValue getFreeze(SDValue V);
+
   /// Return the specified value casted to
   /// the target's desired shift amount type.
   SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
 
   /// Expand the specified \c ISD::VAARG node as the Legalize pass would.
   SDValue expandVAArg(SDNode *Node);
 
   /// Expand the specified \c ISD::VACOPY node as the Legalize pass would.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitZERO_EXTEND(SDNode *N);
     SDValue visitANY_EXTEND(SDNode *N);
     SDValue visitAssertExt(SDNode *N);
     SDValue visitSIGN_EXTEND_INREG(SDNode *N);
     SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
     SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
     SDValue visitTRUNCATE(SDNode *N);
     SDValue visitBITCAST(SDNode *N);
+    SDValue visitFREEZE(SDNode *N);
     SDValue visitBUILD_PAIR(SDNode *N);
     SDValue visitFADD(SDNode *N);
     SDValue visitFSUB(SDNode *N);
     SDValue visitFMUL(SDNode *N);
     SDValue visitFMA(SDNode *N);
     SDValue visitFDIV(SDNode *N);
     SDValue visitFREM(SDNode *N);
     SDValue visitFSQRT(SDNode *N);
SDValue DAGCombiner::visit(SDNode *N) {
   case ISD::INSERT_SUBVECTOR:   return visitINSERT_SUBVECTOR(N);
   case ISD::MGATHER:            return visitMGATHER(N);
   case ISD::MLOAD:              return visitMLOAD(N);
   case ISD::MSCATTER:           return visitMSCATTER(N);
   case ISD::MSTORE:             return visitMSTORE(N);
   case ISD::LIFETIME_END:       return visitLIFETIME_END(N);
   case ISD::FP_TO_FP16:         return visitFP_TO_FP16(N);
   case ISD::FP16_TO_FP:         return visitFP16_TO_FP(N);
+  case ISD::FREEZE:             return visitFREEZE(N);
   case ISD::VECREDUCE_FADD:
   case ISD::VECREDUCE_FMUL:
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_MUL:
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
SDValue DAGCombiner::visitBITCAST(SDNode *N) {
   return SDValue();
 }
 
 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
   EVT VT = N->getValueType(0);
   return CombineConsecutiveLoads(N, VT);
 }
 
+SDValue DAGCombiner::visitFREEZE(SDNode *N) {
+  SDValue N0 = N->getOperand(0);
+
+  // (freeze (freeze x)) -> (freeze x)
+  if (N0.getOpcode() == ISD::FREEZE)
+    return N0;
+
+  // If the input is a constant, return it.
+  if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0))
+    return N0;
+
+  return SDValue();
+}
+
 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
 /// operands. DstEltVT indicates the destination element value type.
 SDValue DAGCombiner::
 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
   EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
 
   // If this is already the right type, we're done.
   if (SrcEltVT == DstEltVT) return SDValue(BV, 0);

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

auto *N = newSDNode<AddrSpaceCastSDNode>(dl.getIROrder(), dl.getDebugLoc(),
                                            VT, SrcAS, DestAS);
   createOperands(N, Ops);
 
   CSEMap.InsertNode(N, IP);
   InsertNode(N);
   return SDValue(N, 0);
 }
 
+SDValue SelectionDAG::getFreeze(SDValue V) {
+  return getNode(ISD::FREEZE, SDLoc(V), V.getValueType(), V);
+}
+
 /// getShiftAmountOperand - Return the specified value casted to
 /// the target's desired shift amount type.
 SDValue SelectionDAG::getShiftAmountOperand(EVT LHSTy, SDValue Op) {
   EVT OpTy = Op.getValueType();
   EVT ShTy = TLI->getShiftAmountTy(LHSTy, getDataLayout());
   if (OpTy == ShTy || OpTy.isVector()) return Op;
 
   return getZExtOrTrunc(Op, SDLoc(Op), ShTy);

llvm/test/CodeGen/X86/fast-isel-freeze.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s                               -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=SDAG
 ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=FAST
 
 define i32 @freeze(i32 %t) {
 ; SDAG-LABEL: freeze:
 ; SDAG:       # %bb.0:
-; SDAG-NEXT:    movl $10, %eax
-; SDAG-NEXT:    xorl %edi, %eax
+; SDAG-NEXT:    movl %edi, %eax
+; SDAG-NEXT:    xorl $10, %eax
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: freeze:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    movl $10, %eax
 ; FAST-NEXT:    xorl %edi, %eax
 ; FAST-NEXT:    retq
   %1 = freeze i32 %t
   %2 = freeze i32 10
   %3 = xor i32 %1, %2
   ret i32 %3
 }

llvm/test/CodeGen/X86/freeze-combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -stop-after=finalize-isel -mtriple=x86_64-unknown < %s 2>&1 | FileCheck %s
+define i32 @const() {
+  ; CHECK-LABEL: name: const
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
+  ; CHECK:   $eax = COPY [[MOV32ri]]
+  ; CHECK:   RET 0, $eax
+  %y = freeze i32 1
+  ret i32 %y
+}
+
+define i32 @fold(i32 %x) {
+  ; CHECK-LABEL: name: fold
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK:   liveins: $edi
+  ; CHECK:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
+  ; CHECK:   [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]]
+  ; CHECK:   $eax = COPY [[COPY1]]
+  ; CHECK:   RET 0, $eax
+  %y = freeze i32 %x
+  %z = freeze i32 %y
+  ret i32 %z
+}

llvm/test/CodeGen/X86/freeze-legalize.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Make sure that seldag legalization works correctly for freeze instruction.
 ; RUN: llc -mtriple=i386-apple-darwin < %s 2>&1 | FileCheck %s
 
 define i64 @expand(i32 %x) {
 ; CHECK-LABEL: expand:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movl $303174162, %eax ## imm = 0x12121212
-; CHECK-NEXT:    movl $875836468, %ecx ## imm = 0x34343434
-; CHECK-NEXT:    movl $1448498774, %edx ## imm = 0x56565656
-; CHECK-NEXT:    xorl %eax, %edx
-; CHECK-NEXT:    movl $2021161080, %eax ## imm = 0x78787878
-; CHECK-NEXT:    xorl %ecx, %eax
+; CHECK-NEXT:    movl $1280068684, %eax ## imm = 0x4C4C4C4C
+; CHECK-NEXT:    movl $1145324612, %edx ## imm = 0x44444444
 ; CHECK-NEXT:    retl
   %y1 = freeze i64 1302123111658042420 ; 0x1212121234343434
   %y2 = freeze i64 6221254864647256184 ; 0x5656565678787878
   %t2 = xor i64 %y1, %y2
   ret i64 %t2
 }
 
 
 define <2 x i64> @expand_vec(i32 %x) nounwind {
 ; CHECK-LABEL: expand_vec:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    pushl %ebx
-; CHECK-NEXT:    pushl %edi
-; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl $16843009, %ecx ## imm = 0x1010101
-; CHECK-NEXT:    movl $589505315, %edx ## imm = 0x23232323
-; CHECK-NEXT:    movl $303174162, %esi ## imm = 0x12121212
-; CHECK-NEXT:    movl $875836468, %edi ## imm = 0x34343434
-; CHECK-NEXT:    movl $1162167621, %ebx ## imm = 0x45454545
-; CHECK-NEXT:    xorl %ecx, %ebx
-; CHECK-NEXT:    movl $1734829927, %ecx ## imm = 0x67676767
-; CHECK-NEXT:    xorl %edx, %ecx
-; CHECK-NEXT:    movl $1448498774, %edx ## imm = 0x56565656
-; CHECK-NEXT:    xorl %esi, %edx
-; CHECK-NEXT:    movl $2021161080, %esi ## imm = 0x78787878
-; CHECK-NEXT:    xorl %edi, %esi
-; CHECK-NEXT:    movl %ebx, 12(%eax)
-; CHECK-NEXT:    movl %ecx, 8(%eax)
-; CHECK-NEXT:    movl %edx, 4(%eax)
-; CHECK-NEXT:    movl %esi, (%eax)
-; CHECK-NEXT:    popl %esi
-; CHECK-NEXT:    popl %edi
-; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    movl $1145324612, 12(%eax) ## imm = 0x44444444
+; CHECK-NEXT:    movl $1145324612, 8(%eax) ## imm = 0x44444444
+; CHECK-NEXT:    movl $1145324612, 4(%eax) ## imm = 0x44444444
+; CHECK-NEXT:    movl $1280068684, (%eax) ## imm = 0x4C4C4C4C
 ; CHECK-NEXT:    retl $4
   ; <0x1212121234343434, 0x101010123232323>
   %y1 = freeze <2 x i64> <i64 1302123111658042420, i64 72340173410738979>
   ; <0x5656565678787878, 0x4545454567676767>
   %y2 = freeze <2 x i64> <i64 6221254864647256184, i64 4991471926399952743>
   %t2 = xor <2 x i64> %y1, %y2
   ret <2 x i64> %t2
 }
 
 define i10 @promote() {
 ; CHECK-LABEL: promote:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movw $682, %cx ## imm = 0x2AA
-; CHECK-NEXT:    movw $992, %ax ## imm = 0x3E0
-; CHECK-NEXT:    addl %ecx, %eax
-; CHECK-NEXT:    ## kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    movw $650, %ax ## imm = 0x28A
 ; CHECK-NEXT:    retl
   %a = freeze i10 682
   %b = freeze i10 992
   %res = add i10 %a, %b
   ret i10 %res
 }
 
 define <2 x i10> @promote_vec() {
 ; CHECK-LABEL: promote_vec:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    movw $125, %ax
-; CHECK-NEXT:    movw $682, %cx ## imm = 0x2AA
-; CHECK-NEXT:    movw $393, %dx ## imm = 0x189
-; CHECK-NEXT:    addl %eax, %edx
-; CHECK-NEXT:    movw $992, %ax ## imm = 0x3E0
-; CHECK-NEXT:    addl %ecx, %eax
-; CHECK-NEXT:    ## kill: def $ax killed $ax killed $eax
-; CHECK-NEXT:    ## kill: def $dx killed $dx killed $edx
+; CHECK-NEXT:    movw $1674, %ax ## imm = 0x68A
+; CHECK-NEXT:    movw $518, %dx ## imm = 0x206
 ; CHECK-NEXT:    retl
   %a = freeze <2 x i10> <i10 682, i10 125>
   %b = freeze <2 x i10> <i10 992, i10 393>
   %res = add <2 x i10> %a, %b
   ret <2 x i10> %res
 }