[TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness

[lewis-revill]

Summary

This patch rewrites the RegisterBankEmitter class to derive RegisterClassHierarchy from CodeGenTarget::getRegBank() rather than constructing our own copy. All are now accessed through a const reference.

This appeared to fix a case of invalidating vectors within RegisterClassHierarchy.getHwModes() - found when testing implementations for another RegisterBankEmitter patch.

[lewis-revill]

Clang format

llvm/utils/TableGen/CodeGenRegisters.h

public:
 
     std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
 
     const std::list<CodeGenRegisterClass> &getRegClasses() const {
       return RegClasses;
     }
 
     // Find a register class from its def.
-    CodeGenRegisterClass *getRegClass(Record*);
+    CodeGenRegisterClass *getRegClass(const Record*) const;
 
     /// getRegisterClassForRegister - Find the register class that contains the
     /// specified physical register.  If the register is not in a register
     /// class, return null. If the register is in multiple classes, and the
     /// classes have a superset-subset relationship and the same set of types,
     /// return the superclass.  Otherwise return null.
     const CodeGenRegisterClass* getRegClassForRegister(Record *R);
 

llvm/utils/TableGen/CodeGenRegisters.cpp

if (FoundI != Key2RC.end())
     return FoundI->second;
 
   // Sub-class doesn't exist, create a new one.
   RegClasses.emplace_back(*this, Name, K);
   addToMaps(&RegClasses.back());
   return &RegClasses.back();
 }
 
-CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
-  if (CodeGenRegisterClass *RC = Def2RC[Def])
+CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
+  if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
     return RC;
 
   PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
 }
 
 CodeGenSubRegIndex*
 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
                                         CodeGenSubRegIndex *B) {

llvm/utils/TableGen/RegisterBankEmitter.cpp

 #include "llvm/ADT/BitVector.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 
 #include "CodeGenHwModes.h"
 #include "CodeGenRegisters.h"
+#include "CodeGenTarget.h"
 
 #define DEBUG_TYPE "register-bank-emitter"
 
 using namespace llvm;
 
 namespace {
 class RegisterBank {
 
public:
 
   /// Get the name of the global instance variable.
   StringRef getInstanceVarName() const { return TheDef.getName(); }
 
   const Record &getDef() const { return TheDef; }
 
   /// Get the register classes listed in the RegisterBank.RegisterClasses field.
   std::vector<const CodeGenRegisterClass *>
-  getExplictlySpecifiedRegisterClasses(
-      CodeGenRegBank &RegisterClassHierarchy) const {
+  getExplicitlySpecifiedRegisterClasses(
+      const CodeGenRegBank &RegisterClassHierarchy) const {
     std::vector<const CodeGenRegisterClass *> RCs;
-    for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
+    for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
     return RCs;
   }
 
   /// Add a register class to the bank without duplicates.
   void addRegisterClass(const CodeGenRegisterClass *RC) {
     if (std::find_if(RCs.begin(), RCs.end(),
                      [&RC](const CodeGenRegisterClass *X) {
public:
   iterator_range<typename RegisterClassesTy::const_iterator>
   register_classes() const {
     return llvm::make_range(RCs.begin(), RCs.end());
   }
 };
 
 class RegisterBankEmitter {
 private:
+  CodeGenTarget Target;
   RecordKeeper &Records;
-  CodeGenRegBank RegisterClassHierarchy;
 
   void emitHeader(raw_ostream &OS, const StringRef TargetName,
                   const std::vector<RegisterBank> &Banks);
   void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
                                const std::vector<RegisterBank> &Banks);
   void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
                                    std::vector<RegisterBank> &Banks);
 
 public:
-  RegisterBankEmitter(RecordKeeper &R)
-      : Records(R), RegisterClassHierarchy(Records, CodeGenHwModes(R)) {}
+  RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
 
   void run(raw_ostream &OS);
 };
 
 } // end anonymous namespace
 
 /// Emit code to declare the ID enumeration and external global instance
 /// variables.

 /// This function must be called for each explicitly specified register class.
 ///
 /// \param RC The register class to search.
 /// \param Kind A debug string containing the path the visitor took to reach RC.
 /// \param VisitFn The action to take for each class visited. It may be called
 ///                multiple times for a given class if there are multiple paths
 ///                to the class.
 static void visitRegisterBankClasses(
-    CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
-    const Twine Kind,
+    const CodeGenRegBank &RegisterClassHierarchy,
+    const CodeGenRegisterClass *RC, const Twine Kind,
     std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
     SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
 
   // Make sure we only visit each class once to avoid infinite loops.
   if (VisitedRCs.count(RC))
     return;
   VisitedRCs.insert(RC);
 
for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
       }
     }
   }
 }
 
 void RegisterBankEmitter::emitBaseClassImplementation(
     raw_ostream &OS, StringRef TargetName,
     std::vector<RegisterBank> &Banks) {
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
 
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n";
   for (const auto &Bank : Banks) {
     std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
         (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
 
     for (const auto &RC : Bank.register_classes())
OS << TargetName << "GenRegisterBankInfo::" << TargetName
      << "  for (const auto &RB : RegBanks)\n"
      << "    assert(Index++ == RB->getID() && \"Index != ID\");\n"
      << "#endif // NDEBUG\n"
      << "}\n"
      << "} // end namespace llvm\n";
 }
 
 void RegisterBankEmitter::run(raw_ostream &OS) {
-  std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
-  if (Targets.size() != 1)
-    PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
-  StringRef TargetName = Targets[0]->getName();
+  StringRef TargetName = Target.getName();
+  const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
 
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
     SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
     RegisterBank Bank(*V);
 
     for (const CodeGenRegisterClass *RC :
-         Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+         Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
       visitRegisterBankClasses(
           RegisterClassHierarchy, RC, "explicit",
           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
             LLVM_DEBUG(dbgs()
                        << "Added " << RC->getName() << "(" << Kind << ")\n");
             Bank.addRegisterClass(RC);
           },
           VisitedRCs);
     }
 
     Banks.push_back(Bank);
   }
 
   // Warn about ambiguous MIR caused by register bank/class name clashes.
-  for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
+  for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
     for (const auto &Bank : Banks) {
-      if (Bank.getName().lower() == Class->getName().lower()) {
+      if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
         PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
                                              "distinct from register classes "
                                              "to avoid ambiguous MIR");
         PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
-        PrintNote(Class->getLoc(), "RegisterClass was declared here");
+        PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");
       }
     }
   }
 
   emitSourceFileHeader("Register Bank Source Fragments", OS);
   OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
      << "#undef GET_REGBANK_DECLARATIONS\n";
   emitHeader(OS, TargetName, Banks);