[PowerPC][Future] Add initial support for PC Relative addressing for constant pool loads

[stefanp]

Summary

Add initial support for PC Relative addressing for constant pool loads.
This includes adding a new relocation for @pcrel and adding a new PowerPC flag to identify PC relative addressing.

[jsji]

Note that Hexagon had already defined VK_Hexagon_PCREL so I modified the Hexagon code to use a non target specific VK_PCREL. The change with respect to Hexagon should be NFC.

Can we split it to be a NFC patch and reviewed by Hexagon guys?

[NeHuang]

llvm/test/CodeGen/PowerPC/constant-pool.ll

44

exceeding 80 columns

52

exceeding 80 columns

84

exceeding 80 columns

[nemanjai]

llvm/test/CodeGen/PowerPC/constant-pool.ll

44

Generally speaking, we don't try to keep test cases to 80 columns.

[stefanp]

Created a new review for only the NFC Hexagon changes here: https://reviews.llvm.org/D74788
Next, I will rework this patch.

[stefanp]

Cleaned up patch and removed the NFC part.
Also added a couple of new patterns to the td file and added a new PPCISD node MAT_PCREL_ADDR. The only purpose of this new node is to materialize PC Relative addresses.

[stefanp]

Removed the PCRelative guard that was incorrectly placed in PPCTargetLowering::SelectAddressRegRegOnly.
Removed the isPrefix class from the td file as it was not required.
Added more comments to the PPCInstrPrefix.td.

[stefanp]

Missed a tconstpool that should have been a pcreladdr.

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2542

I think it would be good if we had doxygen /// comments for this.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

375

s/meterialize/materialize

[anil9]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2414

The last comment and this comment could be made similar. I prefer this one.

[stefanp]

Fixed comments in the code as requested by reviewers.

[stefanp]

Accidentally added unnecessary code when I did a rebase. Removed that now.

[amyk]

Just found one more typo.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

340

s/temporatry/temporary

[nemanjai]

LGTM aside from some minor nits. Feel free to address those on the commit.

llvm/lib/Target/PowerPC/PPC.h

103

Please add to the comment the reasoning behind this being 16 rather than the next power of 2.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2769

Just return DAG.getNode(...);

llvm/lib/Target/PowerPC/PPCInstrInfo.td

326

All the other PPC-specific nodes start with PPC. Please maintain this convention.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

347

This sounds like wishful thinking and not like a commitment to provide this refactoring in the near future. Please change it to:

// Once pc-relative implementation is complete, a set of follow-up patches will
// address this refactoring and the AddedComplexity will be removed.

351

Nit: throughout this block, the name of the pc-relative address seems to suggest that this is only for constant pool entries (i.e. cp). However, this is presumably useful for any pc-relative memory operations. Perhaps $addr or $src.

355

Nit, the alignment is wrong here. When splitting on two lines, the input and output patterns should be aligned in the same column.

llvm/test/CodeGen/PowerPC/csr-split.ll

3

What is the addition to this test meant to accomplish? I do not see any constant pool loads in the test - or anything related to this patch TBH.

[NeHuang]

llvm/test/CodeGen/PowerPC/csr-split.ll

13

No PCRel instructions added for these test cases when add "mcpu=future". There are some non-GOT indirect-access load patterns but not constant pool loads in the test. We should revert the changes in this file. (most probably this file was touched by the old design.

[anil9]

llvm/lib/Target/PowerPC/PPC.h

102

"Fixup is VK_PCREL". or is it the variant kind ?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2319

In the comment above the function it says when it returns false, now that you have another condition when it returns false I think you should update the comment.

2405

Update the comment.

[thakis]

Looks like this breaks tests on Windows: http://45.33.8.238/win/12548/step_11.txt

[kamaub]

In D74486#1972299, @thakis wrote:

Looks like this breaks tests on Windows: http://45.33.8.238/win/12548/step_11.txt

Thank you, we are looking into the problem right now, it will likely be a simple fix so we will push(commit a fix) rather than revert.

[thakis]

Thanks for the fix!

llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_TLSLD
 #undef R_PPC64_ADDR16_HIGH
 #undef R_PPC64_ADDR16_HIGHA
 #undef R_PPC64_TPREL16_HIGH
 #undef R_PPC64_TPREL16_HIGHA
 #undef R_PPC64_DTPREL16_HIGH
 #undef R_PPC64_DTPREL16_HIGHA
 #undef R_PPC64_REL24_NOTOC
+#undef R_PPC64_PCREL34
 #undef R_PPC64_IRELATIVE
 #undef R_PPC64_REL16
 #undef R_PPC64_REL16_LO
 #undef R_PPC64_REL16_HI
 #undef R_PPC64_REL16_HA
 
 ELF_RELOC(R_PPC64_NONE,                 0)
 ELF_RELOC(R_PPC64_ADDR32,               1)

 ELF_RELOC(R_PPC64_TLSLD,                108)
 ELF_RELOC(R_PPC64_ADDR16_HIGH,          110)
 ELF_RELOC(R_PPC64_ADDR16_HIGHA,         111)
 ELF_RELOC(R_PPC64_TPREL16_HIGH,         112)
 ELF_RELOC(R_PPC64_TPREL16_HIGHA,        113)
 ELF_RELOC(R_PPC64_DTPREL16_HIGH,        114)
 ELF_RELOC(R_PPC64_DTPREL16_HIGHA,       115)
 ELF_RELOC(R_PPC64_REL24_NOTOC,          116)
+ELF_RELOC(R_PPC64_PCREL34,              132)
 ELF_RELOC(R_PPC64_IRELATIVE,            248)
 ELF_RELOC(R_PPC64_REL16,                249)
 ELF_RELOC(R_PPC64_REL16_LO,             250)
 ELF_RELOC(R_PPC64_REL16_HI,             251)
 ELF_RELOC(R_PPC64_REL16_HA,             252)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
   case PPC::fixup_ppc_br24:
   case PPC::fixup_ppc_br24abs:
   case PPC::fixup_ppc_br24_notoc:
     return Value & 0x3fffffc;
   case PPC::fixup_ppc_half16:
     return Value & 0xffff;
   case PPC::fixup_ppc_half16ds:
     return Value & 0xfffc;
+  case PPC::fixup_ppc_pcrel34:
+    return Value & 0x3ffffffff;
   }
 }
 
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
   case FK_NONE:
     return 0;
   case FK_Data_1:
     return 1;
   case FK_Data_2:
   case PPC::fixup_ppc_half16:
   case PPC::fixup_ppc_half16ds:
     return 2;
   case FK_Data_4:
   case PPC::fixup_ppc_brcond14:
   case PPC::fixup_ppc_brcond14abs:
   case PPC::fixup_ppc_br24:
   case PPC::fixup_ppc_br24abs:
   case PPC::fixup_ppc_br24_notoc:
     return 4;
+  case PPC::fixup_ppc_pcrel34:
   case FK_Data_8:
     return 8;
   case PPC::fixup_ppc_nofixup:
     return 0;
   }
 }
 
 namespace {
const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
       // name                    offset  bits  flags
       { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24_notoc",  6,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_brcond14",    16,     14,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24abs",     6,      24,   0 },
       { "fixup_ppc_brcond14abs", 16,     14,   0 },
       { "fixup_ppc_half16",       0,     16,   0 },
       { "fixup_ppc_half16ds",     0,     14,   0 },
+      { "fixup_ppc_pcrel34",     0,      34,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_nofixup",      0,      0,   0 }
     };
     const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
       // name                    offset  bits  flags
       { "fixup_ppc_br24",        2,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24_notoc",  2,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_brcond14",    2,      14,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_br24abs",     2,      24,   0 },
       { "fixup_ppc_brcond14abs", 2,      14,   0 },
       { "fixup_ppc_half16",      0,      16,   0 },
       { "fixup_ppc_half16ds",    2,      14,   0 },
+      { "fixup_ppc_pcrel34",     0,      34,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_ppc_nofixup",     0,       0,   0 }
     };
 
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
 
     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
            "Invalid kind!");

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

case PPC::fixup_ppc_half16:
         Type = ELF::R_PPC_REL16_HA;
         break;
       }
       break;
     case PPC::fixup_ppc_half16ds:
       Target.print(errs());
       errs() << '\n';
       report_fatal_error("Invalid PC-relative half16ds relocation");
+    case PPC::fixup_ppc_pcrel34:
+      Type = ELF::R_PPC64_PCREL34;
+      break;
     case FK_Data_4:
     case FK_PCRel_4:
       Type = ELF::R_PPC_REL32;
       break;
     case FK_Data_8:
     case FK_PCRel_8:
       Type = ELF::R_PPC64_REL64;
       break;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h

enum Fixups {
   /// A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like
   /// 'li' or 'addis'.
   fixup_ppc_half16,
 
   /// A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for
   /// instrs like 'std'.
   fixup_ppc_half16ds,
 
+  // A 34-bit fixup corresponding to PC-relative paddi.
+  fixup_ppc_pcrel34,
+
   /// Not a true fixup, but ties a symbol to a call to __tls_get_addr for the
   /// TLS general and local dynamic models, or inserts the thread-pointer
   /// register number.
   fixup_ppc_nofixup,
 
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
 }
 }
 
 #endif

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
   if (MI->getOperand(OpNo).isImm())
     O << (short)MI->getOperand(OpNo).getImm();
   else
     printOperand(MI, OpNo, O);
 }
 
 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
+  if (MI->getOperand(OpNo).isImm()) {
     long long Value = MI->getOperand(OpNo).getImm();
     assert(isInt<34>(Value) && "Invalid s34imm argument!");
     O << (long long)Value;
   }
+  else
+    printOperand(MI, OpNo, O);
+}
 
 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   if (MI->getOperand(OpNo).isImm())
     O << (unsigned short)MI->getOperand(OpNo).getImm();
   else
     printOperand(MI, OpNo, O);
 }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h

unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
   unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
                                 const MCSubtargetInfo &STI) const;
   unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const;
+  unsigned long getImm34Encoding(const MCInst &MI, unsigned OpNo,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const;
   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
   unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
 
   // Add a fixup for the immediate field.
   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_half16));
   return 0;
 }
 
+unsigned long
+PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
+                                   SmallVectorImpl<MCFixup> &Fixups,
+                                   const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isReg() || MO.isImm())
+    return getMachineOpValue(MI, MO, Fixups, STI);
+
+  // Add a fixup for the immediate field.
+  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 1, MO.getExpr(),
+                                   (MCFixupKind)PPC::fixup_ppc_pcrel34));
+  return 0;
+}
+
 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
                                             SmallVectorImpl<MCFixup> &Fixups,
                                             const MCSubtargetInfo &STI) const {
   // Encode (imm, reg) as a memri, which has the low 16-bits as the
   // displacement and the next 5 bits as the register #.
   assert(MI.getOperand(OpNo+1).isReg());
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
 
PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
   uint64_t RegBits =
     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
 
   if (RegBits != 0)
     report_fatal_error("Operand must be 0");
 
   const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isExpr()) {
+    const MCExpr *Expr = MO.getExpr();
+    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
+    assert(SRE->getKind() == MCSymbolRefExpr::VK_PCREL &&
+           "VariantKind must be VK_PCREL");
+    Fixups.push_back(
+        MCFixup::create(IsLittleEndian ? 0 : 1, Expr,
+                        static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
+    return 0;
+  }
   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
 }
 
 uint64_t
 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
   // Encode (imm, reg) as a memri34, which has the low 34-bits as the

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// to "FOO@plt".  This is used for calls and jumps to external functions
     /// and for PIC calls on 32-bit ELF systems.
     MO_PLT = 1,
 
     /// MO_PIC_FLAG - If this bit is set, the symbol reference is relative to
     /// the function's picbase, e.g. lo16(symbol-picbase).
     MO_PIC_FLAG = 2,
 
+    /// MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to
+    /// the current instruction address(pc), e.g., var@pcrel. Fixup is VK_PCREL.
+    MO_PCREL_FLAG = 16,
+
     /// The next are not flags but distinct values.
-    MO_ACCESS_MASK = 0xf0,
+    MO_ACCESS_MASK = 0xf00,
 
     /// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
-    MO_LO = 1 << 4,
-    MO_HA = 2 << 4,
+    MO_LO = 1 << 8,
+    MO_HA = 2 << 8,
 
-    MO_TPREL_LO = 4 << 4,
-    MO_TPREL_HA = 3 << 4,
+    MO_TPREL_LO = 4 << 8,
+    MO_TPREL_HA = 3 << 8,
 
     /// These values identify relocations on immediates folded
     /// into memory operations.
-    MO_DTPREL_LO = 5 << 4,
-    MO_TLSLD_LO = 6 << 4,
-    MO_TOC_LO = 7 << 4,
+    MO_DTPREL_LO = 5 << 8,
+    MO_TLSLD_LO = 6 << 8,
+    MO_TOC_LO = 7 << 8,
 
     // Symbol for VK_PPC_TLS fixup attached to an ADD instruction
-    MO_TLS = 8 << 4
+    MO_TLS = 8 << 8
   };
   } // end namespace PPCII
 
 } // end namespace llvm;
 
 #endif

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
     }
 
     // Select an address into a single register.
     bool SelectAddr(SDValue N, SDValue &Base) {
       Base = N;
       return true;
     }
 
+    bool SelectAddrPCRel(SDValue N, SDValue &Base) {
+      return PPCLowering->SelectAddressPCRel(N, Base);
+    }
+
     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     /// inline asm expressions.  It is always correct to compute the value into
     /// a register.  The case of adding a (possibly relocatable) constant to a
     /// register can be improved, but it is wrong to substitute Reg+Reg for
     /// Reg in an asm, because the load or store opcode would have to change.
     bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                       unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override {

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// QBFLT = Access the underlying QPX floating-point boolean
     /// representation.
     QBFLT,
 
     /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
     /// lower (IDX=1) half of v4f32 to v2f64.
     FP_EXTEND_HALF,
 
+    /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
+    /// either through an add like PADDI or through a PC Relative load like
+    /// PLD.
+    MAT_PCREL_ADDR,
+
     /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
     /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
     /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
     /// i32.
     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 
     /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
     /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
                              SelectionDAG &DAG,
                              unsigned EncodingAlignment) const;
 
     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
     /// represented as an indexed [r+r] operation.
     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
                                  SelectionDAG &DAG) const;
 
+    /// SelectAddressPCRel - Represent the specified address as pc relative to
+    /// be represented as [pc+imm]
+    bool SelectAddressPCRel(SDValue N, SDValue &Base) const;
+
     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// ReplaceNodeResults - Replace the results of node with an illegal result
     /// type with new values built out of custom code.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::QBFLT:           return "PPCISD::QBFLT";
   case PPCISD::QVLFSb:          return "PPCISD::QVLFSb";
   case PPCISD::BUILD_FP128:     return "PPCISD::BUILD_FP128";
   case PPCISD::BUILD_SPE64:     return "PPCISD::BUILD_SPE64";
   case PPCISD::EXTRACT_SPE:     return "PPCISD::EXTRACT_SPE";
   case PPCISD::EXTSWSLI:        return "PPCISD::EXTSWSLI";
   case PPCISD::LD_VSX_LH:       return "PPCISD::LD_VSX_LH";
   case PPCISD::FP_EXTEND_HALF:  return "PPCISD::FP_EXTEND_HALF";
+  case PPCISD::MAT_PCREL_ADDR:  return "PPCISD::MAT_PCREL_ADDR";
   case PPCISD::LD_SPLAT:        return "PPCISD::LD_SPLAT";
   }
   return nullptr;
 }
 
 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
                                           EVT VT) const {
   if (!VT.isVector())

 /// can be represented as an indexed [r+r] operation.  Returns false if it
 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
 /// non-zero and N can be represented by a base register plus a signed 16-bit
 /// displacement, make a more precise judgement by checking (displacement % \p
 /// EncodingAlignment).
 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
                                             SDValue &Index, SelectionDAG &DAG,
                                             unsigned EncodingAlignment) const {
+  // If we have a PC Relative target flag don't select as [reg+reg]. It will be
+  // a [pc+imm].
+  if (SelectAddressPCRel(N, Base))
+    return false;
+
   int16_t imm = 0;
   if (N.getOpcode() == ISD::ADD) {
     // Is there any SPE load/store (f64), which can't handle 16bit offset?
     // SPE load/store can only handle 8-bit offsets.
     if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
         return true;
     if (isIntS16Immediate(N.getOperand(1), imm) &&
         (!EncodingAlignment || !(imm % EncodingAlignment)))
if (Align >= 4)
     return;
 
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   FuncInfo->setHasNonRISpills();
 }
 
 /// Returns true if the address N can be represented by a base register plus
 /// a signed 16-bit displacement [r+imm], and if it is not better
 /// represented as reg+reg.  If \p EncodingAlignment is non-zero, only accept
 /// displacements that are multiples of that value.
 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
                                             SDValue &Base,
                                             SelectionDAG &DAG,
                                             unsigned EncodingAlignment) const {
   // FIXME dl should come from parent load or store, not from address
   SDLoc dl(N);
+
+  // If we have a PC Relative target flag don't select as [reg+imm]. It will be
+  // a [pc+imm].
+  if (SelectAddressPCRel(N, Base))
+    return false;
+
   // If this can be more profitably realized as r+r, fail.
   if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
     return false;
 
   if (N.getOpcode() == ISD::ADD) {
     int16_t imm = 0;
     if (isIntS16Immediate(N.getOperand(1), imm) &&
         (!EncodingAlignment || (imm % EncodingAlignment) == 0)) {
bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
 
   // Otherwise, do it the hard way, using R0 as the base register.
   Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
                          N.getValueType());
   Index = N;
   return true;
 }
 
+/// Returns true if this address is a PC Relative address.
+/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG.
+bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
+  ConstantPoolSDNode *ConstPoolNode =
+      dyn_cast<ConstantPoolSDNode>(N.getNode());
+  bool HasFlag = ConstPoolNode &&
+                 ConstPoolNode->getTargetFlags() == PPCII::MO_PCREL_FLAG;
+  bool HasNode = N.getOpcode() == PPCISD::MAT_PCREL_ADDR;
+  if (HasFlag || HasNode) {
+    Base = N;
+    return true;
+  }
+  return false;
+}
+
 /// Returns true if we should use a direct load into vector instruction
 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
 static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
 
   // If there are any other uses other than scalar to vector, then we should
   // keep it as a scalar load -> direct move pattern to prevent multiple
   // loads.
   LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
   const Constant *C = CP->getConstVal();
 
   // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
+    if (Subtarget.hasPCRelativeMemops()) {
+      SDLoc DL(CP);
+      EVT Ty = getPointerTy(DAG.getDataLayout());
+      SDValue ConstPool = DAG.getTargetConstantPool(C, Ty,
+                                                    CP->getAlignment(),
+                                                    CP->getOffset(),
+                                                    PPCII::MO_PCREL_FLAG);
+      SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
+      return MatAddr;
+    }
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
     return getTOCEntry(DAG, SDLoc(CP), GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_TLS, "ppc-tls"}};
   return makeArrayRef(TargetFlags);
 }
 
 ArrayRef<std::pair<unsigned, const char *>>
 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace PPCII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
-      {MO_PLT, "ppc-plt"}, {MO_PIC_FLAG, "ppc-pic"}};
+      {MO_PLT, "ppc-plt"},
+      {MO_PIC_FLAG, "ppc-pic"},
+      {MO_PCREL_FLAG, "ppc-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas
 // the FP ones have the advantage of lower latency and higher throughput. So
 // what we are after is using the faster instructions in low register pressure
 // situations and using the larger register file in high register pressure

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 // Instructions to support dynamic alloca.
 def SDTDynOp  : SDTypeProfile<1, 2, []>;
 def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
 def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
 def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
 
+// PC Relative Specific Nodes
+def MATpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.
 //
 
 def SHL32 : SDNodeXForm<imm, [{
   // Transformation function: 31 - imm
   return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
 }]>;

 }
 def PPCS34ImmAsmOperand : AsmOperandClass {
   let Name = "S34Imm";
   let PredicateMethod = "isS34Imm";
   let RenderMethod = "addImmOperands";
 }
 def s34imm : Operand<i64> {
   let PrintMethod = "printS34ImmOperand";
+  let EncoderMethod = "getImm34Encoding";
   let ParserMatchClass = PPCS34ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<34>";
 }
 def PPCImmZeroAsmOperand : AsmOperandClass {
   let Name = "ImmZero";
   let PredicateMethod = "isImmZero";
   let RenderMethod = "addImmOperands";
 }

 
 // The address in a single register. This is used with the SjLj
 // pseudo-instructions.
 def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
 
 /// This is just the offset part of iaddr, used for preinc.
 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
 
+// PC Relative Address
+def pcreladdr : ComplexPattern<iPTR, 1, "SelectAddrPCRel", [], []>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Predicate Definitions.
 def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
 def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
 def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
 def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
 def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

defm PSTW :
                              "pstw $RS, $D_RA", IIC_LdStLFD>;
     defm PSTD :
       8LS_DForm_R_D34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
                              (ins g8rc:$RS, memri34_pcrel:$D_RA),
                              "pstd $RS, $D_RA", IIC_LdStLFD>;
   }
 }
 
+// TODO: We have an added complexity of 500 here. This is only a temporatry
+// solution to have tablegen consider these patterns first. The way we do
+// addressing for PowerPC is complex depending on available D form, X form, or
+// aligned D form loads/stores like DS and DQ forms. The prefixed
+// instructions in this file also add additional PC Relative loads/stores
+// and D form loads/stores with 34 bit immediates. It is very difficult to force
+// instruction selection to consistently pick these first without the current
+// added complexity. For the future we should refactor the addessing selection
+// on PowerPC so that this AddedComplexity=500 will not be required.
+let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
+  // Load f32
+  def : Pat<(f32 (load (MATpcreladdr pcreladdr:$cp))), (PLFSpc $cp, 0)>;
+
+  // Load f64
+  def : Pat<(f64 (extloadf32 (MATpcreladdr pcreladdr:$cp))),
+              (COPY_TO_REGCLASS (PLFSpc $cp, 0), VSFRC)>;
+  def : Pat<(f64 (load (MATpcreladdr pcreladdr:$cp))), (PLFDpc $cp, 0)>;
+
+  // Load f128
+  def : Pat<(f128 (load (MATpcreladdr pcreladdr:$cp))),
+            (COPY_TO_REGCLASS (PLXVpc $cp, 0), VRRC)>;
+
+  // Load v4i32
+  def : Pat<(v4i32 (load (MATpcreladdr pcreladdr:$cp))), (PLXVpc $cp, 0)>;
+
+  // Load v2i64
+  def : Pat<(v2i64 (load (MATpcreladdr pcreladdr:$cp))), (PLXVpc $cp, 0)>;
+
+  // Load v4f32
+  def : Pat<(v4f32 (load (MATpcreladdr pcreladdr:$cp))), (PLXVpc $cp, 0)>;
+
+  // Load v2f64
+  def : Pat<(v2f64 (load (MATpcreladdr pcreladdr:$cp))), (PLXVpc $cp, 0)>;
+
+  // If the MATpcreladdr node is not caught by any other pattern it should be
+  // caught here and turned into a paddi instruction to materialize the address.
+  def : Pat<(MATpcreladdr pcreladdr:$cp), (PADDI8pc 0, $cp)>;
+}
+

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

switch (access) {
     case PPCII::MO_TOC_LO:
       RefKind = MCSymbolRefExpr::VK_PPC_TOC_LO;
       break;
     case PPCII::MO_TLS:
       RefKind = MCSymbolRefExpr::VK_PPC_TLS;
       break;
   }
 
   if (MO.getTargetFlags() == PPCII::MO_PLT)
     RefKind = MCSymbolRefExpr::VK_PLT;
+  else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
+    RefKind = MCSymbolRefExpr::VK_PCREL;
 
   const MachineFunction *MF = MO.getParent()->getParent()->getParent();
   const Module *M = MF->getFunction().getParent();
   const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
   const TargetMachine &TM = Printer.TM;
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, RefKind, Ctx);
   // If -msecure-plt -fPIC, add 32768 to symbol.
   if (Subtarget->isSecurePlt() && TM.isPositionIndependent() &&

llvm/test/CodeGen/PowerPC/constant-pool.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
+; RUN:   < %s | FileCheck %s
+
+ define float @FloatConstantPool() {
+; CHECK-LABEL: FloatConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plfs f1, .LCPI0_0@PCREL(0), 1
+entry:
+  ret float 0x380FFFF840000000
+}
+
+ define double @DoubleConstantPool() {
+; CHECK-LABEL: DoubleConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plfd f1, .LCPI1_0@PCREL(0), 1
+entry:
+  ret double 2.225070e-308
+}
+
+ define ppc_fp128 @LongDoubleConstantPool() {
+; CHECK-LABEL: LongDoubleConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plfd f1, .LCPI2_0@PCREL(0), 1
+; CHECK-NEXT:    plfd f2, .LCPI2_1@PCREL(0), 1
+entry:
+  ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B
+}
+
+ define fp128 @__Float128ConstantPool() {
+; CHECK-LABEL: __Float128ConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI3_0@PCREL(0), 1
+entry:
+  ret fp128 0xL00000000000000003C00FFFFC5D02B3A
+}
+
+ define <16 x i8> @VectorCharConstantPool() {
+; CHECK-LABEL: VectorCharConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI4_0@PCREL(0), 1
+entry:
+  ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
+}
+
+ define <8 x i16> @VectorShortConstantPool() {
+; CHECK-LABEL: VectorShortConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI5_0@PCREL(0), 1
+entry:
+  ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
+}
+
+ define <4 x i32> @VectorIntConstantPool() {
+; CHECK-LABEL: VectorIntConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI6_0@PCREL(0), 1
+entry:
+  ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
+}
+
+ define <2 x i64> @VectorLongLongConstantPool() {
+; CHECK-LABEL: VectorLongLongConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI7_0@PCREL(0), 1
+entry:
+  ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
+}
+
+ define <1 x i128> @VectorInt128ConstantPool() {
+; CHECK-LABEL: VectorInt128ConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI8_0@PCREL(0), 1
+entry:
+  ret <1 x i128> <i128 -27670116110564327424>
+}
+
+ define <4 x float> @VectorFloatConstantPool() {
+; CHECK-LABEL: VectorFloatConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI9_0@PCREL(0), 1
+entry:
+  ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
+}
+
+ define <2 x double> @VectorDoubleConstantPool() {
+; CHECK-LABEL: VectorDoubleConstantPool:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI10_0@PCREL(0), 1
+entry:
+  ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
+}

llvm/test/CodeGen/PowerPC/csr-split.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs  -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mcpu=future < %s | FileCheck %s --check-prefix=CHECK-FUTURE
+; RUN: llc -verify-machineinstrs  -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-PWR9
 ; RUN: llc -verify-machineinstrs  -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
 ; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 
 ; Check CSR split can work properly for tests below.
 
 @a = dso_local local_unnamed_addr global i32 0, align 4
 
 define dso_local signext i32 @test1(i32* %b) local_unnamed_addr  {
+; CHECK-FUTURE-LABEL: test1:
+; CHECK-FUTURE:       # %bb.0: # %entry
+; CHECK-FUTURE-NEXT:    mflr r0
+; CHECK-FUTURE-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-FUTURE-NEXT:    .cfi_offset lr, 16
+; CHECK-FUTURE-NEXT:    .cfi_offset r30, -16
+; CHECK-FUTURE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-FUTURE-NEXT:    std r0, 16(r1)
+; CHECK-FUTURE-NEXT:    stdu r1, -48(r1)
+; CHECK-FUTURE-NEXT:    addis r4, r2, a@toc@ha
+; CHECK-FUTURE-NEXT:    lwa r4, a@toc@l(r4)
+; CHECK-FUTURE-NEXT:    mr r30, r3
+; CHECK-FUTURE-NEXT:    cmpld r4, r3
+; CHECK-FUTURE-NEXT:    # implicit-def: $r3
+; CHECK-FUTURE-NEXT:    bne cr0, .LBB0_2
+; CHECK-FUTURE-NEXT:  # %bb.1: # %if.then
+; CHECK-FUTURE-NEXT:    bl callVoid
+; CHECK-FUTURE-NEXT:    nop
+; CHECK-FUTURE-NEXT:    mr r3, r30
+; CHECK-FUTURE-NEXT:    bl callNonVoid@notoc
+; CHECK-FUTURE-NEXT:  .LBB0_2: # %if.end
+; CHECK-FUTURE-NEXT:    extsw r3, r3
+; CHECK-FUTURE-NEXT:    addi r1, r1, 48
+; CHECK-FUTURE-NEXT:    ld r0, 16(r1)
+; CHECK-FUTURE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-FUTURE-NEXT:    mtlr r0
+; CHECK-FUTURE-NEXT:    blr
+;
 ; CHECK-PWR9-LABEL: test1:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR9-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)
if.end:                                           ; preds = %if.then, %entry
   ret i32 %retval.0
 }
 
 declare signext i32 @callVoid(...) local_unnamed_addr
 
 declare signext i32 @callNonVoid(i32*) local_unnamed_addr
 
 define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr  {
+; CHECK-FUTURE-LABEL: test2:
+; CHECK-FUTURE:       # %bb.0: # %entry
+; CHECK-FUTURE-NEXT:    mflr r0
+; CHECK-FUTURE-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-FUTURE-NEXT:    .cfi_offset lr, 16
+; CHECK-FUTURE-NEXT:    .cfi_offset r30, -16
+; CHECK-FUTURE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-FUTURE-NEXT:    std r0, 16(r1)
+; CHECK-FUTURE-NEXT:    stdu r1, -48(r1)
+; CHECK-FUTURE-NEXT:    mr r30, r3
+; CHECK-FUTURE-NEXT:    cmpldi r3, 0
+; CHECK-FUTURE-NEXT:    li r3, 0
+; CHECK-FUTURE-NEXT:    beq cr0, .LBB1_3
+; CHECK-FUTURE-NEXT:  # %bb.1: # %if.end
+; CHECK-FUTURE-NEXT:    addis r4, r2, a@toc@ha
+; CHECK-FUTURE-NEXT:    lwa r4, a@toc@l(r4)
+; CHECK-FUTURE-NEXT:    cmpld r4, r30
+; CHECK-FUTURE-NEXT:    bne cr0, .LBB1_3
+; CHECK-FUTURE-NEXT:  # %bb.2: # %if.then2
+; CHECK-FUTURE-NEXT:    bl callVoid
+; CHECK-FUTURE-NEXT:    nop
+; CHECK-FUTURE-NEXT:    mr r3, r30
+; CHECK-FUTURE-NEXT:    bl callNonVoid@notoc
+; CHECK-FUTURE-NEXT:  .LBB1_3: # %return
+; CHECK-FUTURE-NEXT:    extsw r3, r3
+; CHECK-FUTURE-NEXT:    addi r1, r1, 48
+; CHECK-FUTURE-NEXT:    ld r0, 16(r1)
+; CHECK-FUTURE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-FUTURE-NEXT:    mtlr r0
+; CHECK-FUTURE-NEXT:    blr
+;
 ; CHECK-PWR9-LABEL: test2:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR9-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-PWR9-NEXT:    std r0, 16(r1)

 
 return:                                           ; preds = %if.end, %entry, %if.then2
   %retval.0 = phi i32 [ %call3, %if.then2 ], [ 0, %entry ], [ 0, %if.end ]
   ret i32 %retval.0
 }
 
 
 define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_addr  {
+; CHECK-FUTURE-LABEL: test3:
+; CHECK-FUTURE:         .localentry test3, 1
+; CHECK-FUTURE-NEXT:  # %bb.0: # %entry
+; CHECK-FUTURE-NEXT:    mflr r0
+; CHECK-FUTURE-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-FUTURE-NEXT:    .cfi_offset lr, 16
+; CHECK-FUTURE-NEXT:    .cfi_offset r29, -24
+; CHECK-FUTURE-NEXT:    .cfi_offset r30, -16
+; CHECK-FUTURE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-FUTURE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-FUTURE-NEXT:    std r0, 16(r1)
+; CHECK-FUTURE-NEXT:    stdu r1, -64(r1)
+; CHECK-FUTURE-NEXT:    ld r30, 0(r3)
+; CHECK-FUTURE-NEXT:    cmpldi r30, 0
+; CHECK-FUTURE-NEXT:    beq cr0, .LBB2_2
+; CHECK-FUTURE-NEXT:  # %bb.1: # %land.rhs
+; CHECK-FUTURE-NEXT:    mr r29, r3
+; CHECK-FUTURE-NEXT:    clrldi r4, r4, 32
+; CHECK-FUTURE-NEXT:    mr r3, r30
+; CHECK-FUTURE-NEXT:    bl bar@notoc
+; CHECK-FUTURE-NEXT:    std r3, 0(r29)
+; CHECK-FUTURE-NEXT:  .LBB2_2: # %land.end
+; CHECK-FUTURE-NEXT:    mr r3, r30
+; CHECK-FUTURE-NEXT:    addi r1, r1, 64
+; CHECK-FUTURE-NEXT:    ld r0, 16(r1)
+; CHECK-FUTURE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-FUTURE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-FUTURE-NEXT:    mtlr r0
+; CHECK-FUTURE-NEXT:    blr
+;
 ; CHECK-PWR9-LABEL: test3:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    mflr r0
 ; CHECK-PWR9-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-PWR9-NEXT:    .cfi_offset lr, 16
 ; CHECK-PWR9-NEXT:    .cfi_offset r29, -24
 ; CHECK-PWR9-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR9-NEXT:    std r29, -24(r1) # 8-byte Folded Spill

llvm/test/CodeGen/PowerPC/pcrel.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-S
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   --filetype=obj < %s | \
+; RUN:   llvm-objdump -mcpu=future -dr - | FileCheck %s --check-prefix=CHECK-O
+
+; Constant Pool Index.
+; CHECK-S-LABEL: ConstPool
+; CHECK-S:       plfd f1, .LCPI0_0@PCREL(0), 1
+; CHECK-S:       blr
+
+; CHECK-O-LABEL: ConstPool
+; CHECK-O:       plfd 1, 0(0), 1
+; CHECK-O-NEXT:  R_PPC64_PCREL34  .rodata.cst8
+; CHECK-O:       blr
+define dso_local double @ConstPool() local_unnamed_addr {
+  entry:
+    ret double 0x406ECAB439581062
+}
+
+