[PowerPC][Future] Add prefixed instruction paddi to future CPU

[NeHuang]

Summary

Future CPU will include support for prefixed instructions. These prefixed instructions are formed by a 4 byte prefix immediately followed by a 4 byte instruction effectively making an 8 byte instruction. The new instruction paddi is a prefixed form of addi.

This patch adds paddi and all of the support required for that instruction. The majority of the patch deals with supporting the new prefixed instructions. The addition of paddi is mainly to allow for testing.

[nemanjai]

Missing context on this review. Please produce the diff with -U99999 or arc to ensure full context is available.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

72

The definition above hard codes the prefix. I don't see a reason for this one to be any different.

[stefanp]

Added full context.

[stefanp]

Addressed review comment by hard coding the prefix for MLS_DForm2_r0.

[jsji]

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

360

Do we have relocation similar to @l? Do we need to make this as ContextImmediate?

llvm/lib/Target/PowerPC/PPC.td

217

Shouldn't this be in https://reviews.llvm.org/D72574 instead?

llvm/lib/Target/PowerPC/PPCInstrFormats.td

45

As mentioned in comments in line 33 above, we should add the enum in PPCInstrInfo.h as well.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

34

It would be better to put these before TSFlags{8} so that they are in order and easier to check.

[nemanjai]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

367

I think that according to Daniel's comment in https://reviews.llvm.org/D72574, we should be able to safely give Inst the type uint64_t in all paths and simply avoid having the template instantiated with a 32-bit integer altogether. This would allow us to not need the changes in TblGen.

[kamaub]

This patch looks ready to land (once the other comments are addressed), I only have two of NFC request that can be done pre-commit for readability.

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

336

nit: Is it possible to use that actually type here instead of auto? I get that its hard to define because it's a template within a template but as far as i can tell in this use it would be uint32_t (*ReadFunc) = this would make the code a more readable I think, selecting which function to use base on the target is more clear this way to me with this way.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

83

should this be let Inst{11} = PCRel; to match the definition in MLS_DForm_R_SI34_RTA5 since PI sets it to zero and only isPCRel sets it to 1

[NeHuang]

Commandeer this patch.

[NeHuang]

Addressed Nemanja and Daniel's comment to give Inst type uint64_t

[nemanjai]

A few more comments need to be addressed for this to proceed.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

360

I believe that all pc-relative relocations have only a single possible interpretation so we probably don't need a ContextImmediate. However, once the ABI is finalized we might want to revisit/reevaluate that. Perhaps just a FIXME in the code noting that?

// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
// ContextImmediate is needed.

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

336

I think auto is preferable here as it does not restrict future changes to the interface of the functions themselves. For example, if at some point another parameter needed to be added with a default argument, hard-coding the function type here would cause compilation errors without a particularly good reason.

llvm/lib/Target/PowerPC/PPC.td

217

Agreed.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

45

Yup!

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

34

+1

83

I think this one is explicitly not PC-Rel so that's why it's set to zero.

llvm/lib/Target/PowerPC/PPCSubtarget.h

109

This of course also needs to go into the other patch. Also, both of these need to be initialized (to false) in the .cpp file.

267

Same as above, please move to other patch.

[nemanjai]

Forgot to select request changes.

[NeHuang]

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

360

Will do.

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

336

+1

llvm/lib/Target/PowerPC/PPC.td

217

Will do.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

45

Thanks @jsji, will do.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

34

Will do

83

Agree, PC-Rel is not used in PLI8 and PLI, should set zero here to avoid confusion.

llvm/lib/Target/PowerPC/PPCSubtarget.h

109

Will do.

267

Will do

[amyk]

llvm/lib/Target/PowerPC/PPCInstrFormats.td

48

s/Inidicate/Indicate

llvm/lib/Target/PowerPC/PPCScheduleP9.td

44

Perhaps we should also update the comment to include PrefixInstrs.

[NeHuang]

Addressed comments above.

[nemanjai]

LGTM. Thanks for addressing the comments.

[jsji]

FYI. Needs rebase to pick up https://reviews.llvm.org/D72649. Thanks.

[Yi-Hong.Lyu]

llvm/lib/Target/PowerPC/PPCInstrFormats.td

45

Do we really need this flag? I think it is the flag that should be removed with removing UseVSXReg flag work in https://reviews.llvm.org/D58685.

[NeHuang]

Addressed review comments to pick up D72649 and remove the unused flag.
@Yi-Hong.Lyu

[Yi-Hong.Lyu]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

198

Two things:

1. There is no test that execute this line. Tests doesn't have enough coverage in this patch.
2. For paddi 1, 2, 8589934591, 1, it is disassemblable but invalid on hardware. I imagine we should use SoftFail instead of Fail here. Please see https://llvm.org/doxygen/classllvm_1_1MCDisassembler.html#a8eb822283e8f3200ca4b2a1ba0174e6a

[nemanjai]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

198

I am not sure what your intent here is. The instruction as you wrote it is illegal. It will cause a SIGILL not some kind of undefined behaviour or anything like that.
What would be the advantage of disassembling object code into invalid instruction forms?

[Yi-Hong.Lyu]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

198

Got it. Please add MC/Disassembler/PowerPC/future-invalid.txt in other pull request in this patch, otherwise this line is not tested. Other LGTM.

[NeHuang]

Thanks @Yi-Hong.Lyu @nemanjai. That test case was in https://reviews.llvm.org/D72574 and I have moved it to this patch.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

bool isS16Imm() const {
     }
   }
   bool isS16ImmX4() const { return Kind == Expression ||
                                    (Kind == Immediate && isInt<16>(getImm()) &&
                                     (getImm() & 3) == 0); }
   bool isS16ImmX16() const { return Kind == Expression ||
                                     (Kind == Immediate && isInt<16>(getImm()) &&
                                      (getImm() & 15) == 0); }
+  bool isS34Imm() const {
+    return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
+  }
+
   bool isS17Imm() const {
     switch (Kind) {
       case Expression:
         return true;
       case Immediate:
       case ContextImmediate:
         return isInt<17>(getImmS16Context());
       default:
if (!IsPPC64) {
       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
         return true;
     }
     return false;
   }
   bool isCondBr() const { return Kind == Expression ||
                                  (Kind == Immediate && isInt<16>(getImm()) &&
                                   (getImm() & 3) == 0); }
+  bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
   bool isVSRegNumber() const {
     return Kind == Immediate && isUInt<6>(getImm());
   }
   bool isCCRegNumber() const { return (Kind == Expression
                                        && isUInt<3>(getExprCRVal())) ||
                                       (Kind == Immediate
                                        && isUInt<3>(getImm())); }

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

 template<unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address, const void *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
+                                         int64_t Address, const void *Decoder) {
+  if (Imm != 0)
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
                                         int64_t Address, const void *Decoder) {
   // Decode the memri field (imm, reg), which has the low 16-bits as the
   // displacement and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 16;
   uint64_t Disp = Imm & 0xFFFF;
 

 }
 
 #include "PPCGenDisassemblerTables.inc"
 
 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                              ArrayRef<uint8_t> Bytes,
                                              uint64_t Address, raw_ostream &OS,
                                              raw_ostream &CS) const {
+  auto *ReadFunc = IsLittleEndian ? support::endian::read32le
+                                  : support::endian::read32be;
+
+  // If this is an 8-byte prefixed instruction, handle it here.
+  // Note: prefixed instructions aren't technically 8-byte entities - the prefix
+  //       appears in memory at an address 4 bytes prior to that of the base
+  //       instruction regardless of endianness. So we read the two pieces and
+  //       rebuild the 8-byte instruction.
+  // TODO: In this function we call decodeInstruction several times with
+  //       different decoder tables. It may be possible to only call once by
+  //       looking at the top 6 bits of the instruction.
+  if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
+    uint32_t Prefix = ReadFunc(Bytes.data());
+    uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
+    uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
+    DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
+                                            this, STI);
+    if (result != MCDisassembler::Fail) {
+      Size = 8;
+      return result;
+    }
+  }
+
   // Get the four bytes of the instruction.
   Size = 4;
   if (Bytes.size() < 4) {
     Size = 0;
     return MCDisassembler::Fail;
   }
 
   // Read the instruction in the proper endianness.
-  uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data())
-                                 : support::endian::read32be(Bytes.data());
+  uint32_t Inst = ReadFunc(Bytes.data());
 
   if (STI.getFeatureBits()[PPC::FeatureQPX]) {
     DecodeStatus result =
       decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
     if (result != MCDisassembler::Fail)
       return result;
   } else if (STI.getFeatureBits()[PPC::FeatureSPE]) {
     DecodeStatus result =
       decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
     if (result != MCDisassembler::Fail)
       return result;
   }
 
   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
 }
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h

public:
   void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printS34ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printImmZeroOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

 
 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   int Value = MI->getOperand(OpNo).getImm();
   Value = SignExtend32<5>(Value);
   O << (int)Value;
 }
 
+void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
+                                         raw_ostream &O) {
+  unsigned int Value = MI->getOperand(OpNo).getImm();
+  assert(Value == 0 && "Operand must be zero");
+  O << (unsigned int)Value;
+}
+
 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned int Value = MI->getOperand(OpNo).getImm();
   assert(Value <= 31 && "Invalid u5imm argument!");
   O << (unsigned int)Value;
 }
 
 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,

 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   if (MI->getOperand(OpNo).isImm())
     O << (short)MI->getOperand(OpNo).getImm();
   else
     printOperand(MI, OpNo, O);
 }
 
+void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
+                                        raw_ostream &O) {
+  long long Value = MI->getOperand(OpNo).getImm();
+  assert(isInt<34>(Value) && "Invalid s34imm argument!");
+  O << (long long)Value;
+}
+
 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   if (MI->getOperand(OpNo).isImm())
     O << (unsigned short)MI->getOperand(OpNo).getImm();
   else
     printOperand(MI, OpNo, O);
 }
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h

unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
 
   /// getMachineOpValue - Return binary encoding of operand. If the machine
   /// operand requires relocation, record the relocation and return zero.
-  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

for (unsigned i = 0; i < MI.getNumOperands(); i++) {
     const MCOperand &Op = MI.getOperand(i);
     if (&Op == &MO)
       return i;
   }
   llvm_unreachable("This operand is not part of this instruction");
   return ~0U; // Silence any warnings about no return.
 }
 
-unsigned PPCMCCodeEmitter::
+uint64_t PPCMCCodeEmitter::
 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
   if (MO.isReg()) {
     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
     // The GPR operand should come through here though.
     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||

llvm/lib/Target/PowerPC/PPC.td

def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
                                          FeatureP9Altivec]>;
 // A separate feature for this even though it is equivalent to P9Vector
 // because this is a feature of the implementation rather than the architecture
 // and may go away with future CPU's.
 def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
                                                  "VectorsUseTwoUnits",
                                                  "true",
                                                  "Vectors use two units">;
+def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
+                                           "true",
+                                           "Enable prefixed instructions",
+                                           [FeatureISA3_0, FeatureP8Vector,
+                                            FeatureP9Altivec]>;
+def FeaturePCRelativeMemops :
+  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
+                   "Enable PC relative Memory Ops",
+                   [FeatureISA3_0]>;
+
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
 // Namely:
 //     list<SubtargetFeature> P8InheritableFeatures = ...
 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 //         [ features that Power8 does not support but inheritable ]
list<SubtargetFeature> P9InheritableFeatures =
     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
   list<SubtargetFeature> P9Features =
     !listconcat(P9InheritableFeatures, P9SpecificFeatures);
 
   // Future
   // For future CPU we assume that all of the existing features from Power 9
   // still exist with the exception of those we know are Power 9 specific.
   list<SubtargetFeature> FutureAdditionalFeatures = [];
-  list<SubtargetFeature> FutureSpecificFeatures = [];
+  list<SubtargetFeature> FutureSpecificFeatures =
+      [FeaturePrefixInstrs, FeaturePCRelativeMemops];
   list<SubtargetFeature> FutureInheritableFeatures =
     !listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
   list<SubtargetFeature> FutureFeatures =
     !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
 }
 
 // Note: Future features to add when support is extended to more
 // recent ISA levels:

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
   let TSFlags{1}   = PPC970_Single;
   let TSFlags{2}   = PPC970_Cracked;
   let TSFlags{5-3} = PPC970_Unit;
 
   // Indicate that this instruction is of type X-Form Load or Store
   bits<1> XFormMemOp = 0;
   let TSFlags{7}  = XFormMemOp;
 
+  // Indicate that this instruction does not use the default register numbering.
+  bits<1> UseCustomRegNumbering = 0;
+  let TSFlags{8}  = UseCustomRegNumbering;
+
+  // Inidicate that this instruction is prefixed.
+  bits<1> Prefixed = 0;
+  let TSFlags{9}  = Prefixed;
+
   // Fields used for relation models.
   string BaseName = "";
 
   // For cases where multiple instruction definitions really represent the
   // same underlying instruction but with one definition for 64-bit arguments
   // and one for 32-bit arguments, this bit breaks the degeneracy between
   // the two forms and allows TableGen to generate mapping tables.
   bit Interpretation64Bit = 0;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def s17imm  : Operand<i32> {
   // This operand type is used for addis/lis to allow the assembler parser
   // to accept immediates in the range -65536..65535 for compatibility with
   // the GNU assembler.  The operand is treated as 16-bit otherwise.
   let PrintMethod = "printS16ImmOperand";
   let EncoderMethod = "getImm16Encoding";
   let ParserMatchClass = PPCS17ImmAsmOperand;
   let DecoderMethod = "decodeSImmOperand<16>";
 }
+def PPCS34ImmAsmOperand : AsmOperandClass {
+  let Name = "S34Imm";
+  let PredicateMethod = "isS34Imm";
+  let RenderMethod = "addImmOperands";
+}
+def s34imm : Operand<i64> {
+  let PrintMethod = "printS34ImmOperand";
+  let ParserMatchClass = PPCS34ImmAsmOperand;
+  let DecoderMethod = "decodeSImmOperand<34>";
+}
+def PPCImmZeroAsmOperand : AsmOperandClass {
+  let Name = "ImmZero";
+  let PredicateMethod = "isImmZero";
+  let RenderMethod = "addImmOperands";
+}
+def immZero : Operand<i32> {
+  let PrintMethod = "printImmZeroOperand";
+  let ParserMatchClass = PPCImmZeroAsmOperand;
+  let DecoderMethod = "decodeImmZeroOperand";
+}
 
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 
 def PPCDirectBrAsmOperand : AsmOperandClass {
   let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
   let RenderMethod = "addBranchTargetOperands";
 }
 def directbrtarget : Operand<OtherVT> {

 include "PPCInstrQPX.td"
 include "PPCInstrHTM.td"
 
 def crnot : OutPatFrag<(ops node:$in),
                        (CRNOR $in, $in)>;
 def       : Pat<(not i1:$in),
                 (crnot $in)>;
 
+// Prefixed instructions may requre access to the above defs at a later
+// time so we include this after the def.
+include "PPCInstrPrefix.td"
+
 // Patterns for arithmetic i1 operations.
 def : Pat<(add i1:$a, i1:$b),
           (CRXOR $a, $b)>;
 def : Pat<(sub i1:$a, i1:$b),
           (CRXOR $a, $b)>;
 def : Pat<(mul i1:$a, i1:$b),
           (CRAND $a, $b)>;
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

+// PC Relative flag (for instructions that use the address of the prefix for
+// address computations).
+class isPCRel { bit PCRel = 1; }
+
+// Top-level class for prefixed instructions.
+class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
+         InstrItinClass itin> : Instruction {
+  field bits<64> Inst;
+  field bits<64> SoftFail = 0;
+  bit PCRel = 0; // Default value, set by isPCRel.
+  let Size = 8;
+
+  let Namespace = "PPC";
+  let OutOperandList = OOL;
+  let InOperandList = IOL;
+  let AsmString = asmstr;
+  let Itinerary = itin;
+  let Inst{0-5} = pref;
+  let Inst{32-37} = opcode;
+
+  bits<1> PPC970_First = 0;
+  bits<1> PPC970_Single = 0;
+  bits<1> PPC970_Cracked = 0;
+  bits<3> PPC970_Unit = 0;
+
+  bits<1> UseCustomRegNumbering = 0;
+  let TSFlags{8} = UseCustomRegNumbering;
+
+  bits<1> Prefixed = 1;  // This is a prefixed instruction.
+  let TSFlags{9}  = Prefixed;
+
+  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
+  /// these must be reflected there!  See comments there for what these are.
+  let TSFlags{0}   = PPC970_First;
+  let TSFlags{1}   = PPC970_Single;
+  let TSFlags{2}   = PPC970_Cracked;
+  let TSFlags{5-3} = PPC970_Unit;
+
+  // For cases where multiple instruction definitions really represent the
+  // same underlying instruction but with one definition for 64-bit arguments
+  // and one for 32-bit arguments, this bit breaks the degeneracy between
+  // the two forms and allows TableGen to generate mapping tables.
+  bit Interpretation64Bit = 0;
+
+  // Fields used for relation models.
+  string BaseName = "";
+}
+
+class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+                            InstrItinClass itin, list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<5> RA;
+  bits<34> SI;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 2;
+  let Inst{8-10} = 0;
+  let Inst{11} = PCRel;
+  let Inst{12-13} = 0;
+  let Inst{14-31} = SI{33-16};
+
+  // The instruction.
+  let Inst{38-42} = RT;
+  let Inst{43-47} = RA;
+  let Inst{48-63} = SI{15-0};
+}
+
+class MLS_DForm2_r0<bits<6> pref, bits<6> opcode, dag OOL, dag IOL,
+                    string asmstr, InstrItinClass itin, list<dag> pattern>
+  : PI<pref, opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<34> SI;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 2;
+  let Inst{8-10} = 0;
+  let Inst{11} = 0;
+  let Inst{12-13} = 0;
+  let Inst{14-31} = SI{33-16};
+
+  // The instruction.
+  let Inst{38-42} = RT;
+  let Inst{43-47} = 0;
+  let Inst{48-63} = SI{15-0};
+}
+
+multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
+                                   dag PCRel_IOL, string asmstr,
+                                   InstrItinClass itin> {
+  def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
+                                   !strconcat(asmstr, ", 0"), itin, []>;
+  def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
+                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
+}
+
+
+def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
+
+let Predicates = [PrefixInstrs] in {
+  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+    defm PADDI8 :
+      MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
+                              (ins immZero:$RA, s34imm:$SI),
+                              "paddi $RT, $RA, $SI", IIC_LdStLFD>;
+    let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
+      def PLI8 : MLS_DForm2_r0<1, 14, (outs g8rc:$RT),
+                               (ins s34imm:$SI),
+                               "pli $RT, $SI", IIC_IntSimple, []>;
+    }
+  }
+  defm PADDI :
+    MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
+                            (ins immZero:$RA, s34imm:$SI),
+                            "paddi $RT, $RA, $SI", IIC_LdStLFD>;
+  let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
+    def PLI : MLS_DForm2_r0<1, 14, (outs gprc:$RT),
+                            (ins s34imm:$SI),
+                            "pli $RT, $SI", IIC_IntSimple, []>;
+  }
+}
+

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9Model : SchedMachineModel {
   // issue queue until all register sources and other dependencies have been
   // resolved and they can be issued. Each of four execution slices has an
   // 11-entry iop issue queue.
   let MicroOpBufferSize = 44;
 
   let CompleteModel = 1;
 
   // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
   // Engine) on Power 9.
-  let UnsupportedFeatures = [HasQPX, HasSPE];
+  let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs];
 
 }
 
 let SchedModel = P9Model in {
 
   // ***************** Processor Resources *****************
 
   // Dispatcher slots:

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool HasQPX;
   bool HasVSX;
   bool NeedsTwoConstNR;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
+  bool HasPrefixInstrs;
+  bool HasPCRelativeMemops;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
public:
   bool hasQPX() const { return HasQPX; }
   bool hasVSX() const { return HasVSX; }
   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
+  bool hasPrefixInstrs() const { return HasPrefixInstrs; }
+  bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }
   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }

llvm/test/CodeGen/PowerPC/future-check-features.ll

+; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
+; RUN:   -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
+; RUN:   %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
+; RUN:   -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
+; RUN:   %s -o - 2>&1 | FileCheck %s
+
+define dso_local signext i32 @f() {
+entry:
+  ret i32 0
+}
+
+; Make sure that all of the features listed are recognized.
+; CHECK-NOT:    is not a recognized feature for this target
+
+; Make sure that the test was actually compiled.
+; CHECK:        li r3, 0
+; CHECK-NEXT:   blr
+

llvm/test/MC/Disassembler/PowerPC/futureinsts.txt

+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
+# RUN:   -mcpu=future | FileCheck %s
+
+# CHECK: paddi 1, 2, 8589934591, 0
+0x06 0x01 0xff 0xff 0x38 0x22 0xff 0xff
+
+# CHECK: paddi 1, 0, -8589934592, 1
+0x06 0x12 0x00 0x00 0x38 0x20 0x00 0x00
+

llvm/test/MC/PowerPC/future.s

+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
+# RUN:   FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
+# RUN:   FileCheck -check-prefix=CHECK-LE %s
+
+# CHECK-BE: paddi 1, 2, 8589934591, 0             # encoding: [0x06,0x01,0xff,0xff
+# CHECK-BE-SAME:                                               0x38,0x22,0xff,0xff]
+# CHECK-LE: paddi 1, 2, 8589934591, 0             # encoding: [0xff,0xff,0x01,0x06
+# CHECK-LE-SAME:                                               0xff,0xff,0x22,0x38]
+            paddi 1, 2, 8589934591, 0
+# CHECK-BE: paddi 1, 0, -8589934592, 1            # encoding: [0x06,0x12,0x00,0x00
+# CHECK-BE-SAME:                                               0x38,0x20,0x00,0x00]
+# CHECK-LE: paddi 1, 0, -8589934592, 1            # encoding: [0x00,0x00,0x12,0x06
+# CHECK-LE-SAME:                                               0x00,0x00,0x20,0x38]
+            paddi 1, 0, -8589934592, 1
+# CHECK-BE: pli 1, -8589934592                    # encoding: [0x06,0x02,0x00,0x00
+# CHECK-BE-SAME:                                               0x38,0x20,0x00,0x00]
+# CHECK-LE: pli 1, -8589934592                    # encoding: [0x00,0x00,0x02,0x06
+# CHECK-LE-SAME:                                               0x00,0x00,0x20,0x38]
+            pli 1, -8589934592
+# CHECK-BE: pli 1, 8589934591                     # encoding: [0x06,0x01,0xff,0xff
+# CHECK-BE-SAME:                                               0x38,0x20,0xff,0xff]
+# CHECK-LE: pli 1, 8589934591                     # encoding: [0xff,0xff,0x01,0x06
+# CHECK-LE-SAME:                                               0xff,0xff,0x20,0x38]
+            pli 1, 8589934591
+
+