[GlobalISel][RFC] Importing insert/extract vector element patterns

[Petar.Avramovic]

Summary

I am trying to import insert/extract vector element isel patterns. The important first question is what to GINodeEquiv ?
Here's prototype that is able to selectimpl some basic insert/extract vector patterns for MIPS:

• Generic vector_insert def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>; is used for both same and different "vector scalar" and "inserted/extracted elt scalar" size
• Generic vector_extract def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; is used only for floating point vector extract (same "vector scalar" and "inserted/extracted elt scalar" size)
• MipsVExtractSExt and MipsVExtractZExt are used for both same and different "vector scalar" and "inserted/extracted elt scalar" size, although same element size for MipsVExtractZExt gets selected like MipsVExtractSExt (the "same 32-bit element size" on 32-bit machine is extending when executed on 64-bit machine, and this type of extending has to be signextending).

@rovka, could neon use generic G_SEXT_EXTRACT_VECTOR_ELT and G_ZEXT_EXTRACT_VECTOR_ELT since it has similar target specific extending vector extract isd nodes? Probably something like this:
def : GINodeEquiv<G_SEXT_EXTRACT_VECTOR_ELT, ARMvgetlanes>;
def : GINodeEquiv<G_ZEXT_EXTRACT_VECTOR_ELT, ARMvgetlaneu>;
They cant't be imported yet because they have SDNodeXForm (like DSubReg_i8_reg) for subindex.

I think that MIPS has to GINodeEquiv globalisel opcodes without the:
"vector scalar size" has to be the same as "inserted/extracted elt scalar size"
constraint to match patterns from td files.

Is this a right direction or I need to GINodeEquiv something else ?
There are some size constraints in MachineIRBuilder for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT, G_BUILD_VECTOR_TRUNC also exists, but I don't see what are their GINodeEquiv SDAG-nodes.

Some additional information about the implementation:
Combiner for extract vector is copy of zextload/sextload combiner.
For MIPS imm index for all insert/extract vector element opcodes is iptr, but that is scalar of pointer size, added ScalarOfPtrSizeMatcher.
Importing EXTRACT_SUBREG patterns:
when EXTRACT_SUBREG is in the middle there is a subregister copy to tmp register, added TempSubRegRenderer.
Figuring out classes for constraints of subreg copy operands.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

583

I think this should assert isPointer. Using 0 address space if it's not a pointer is nonsensical

llvm/include/llvm/Target/GenericOpcodes.td

1060–1061

Adding these is a separate patch

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

125

I think there should be no compatibility for vector_insert/vector_extract see this comment:
vector_extract/vector_insert are deprecated. extractelt/insertelt
are preferred.

Really we should migrate all the uses away from the old relaxed nodes

[Petar.Avramovic]

Attempt to switch to insertelt and extractelt for mips. Simplified a few lines.

[Petar.Avramovic]

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

583

vector_insert has index operand of pointer type, but G_INSERT_VECTOR_ELT has most likely scalar index (G_CONSTANT or value in vreg).
That line was most probably wrong. I wanted to get pointer size but it is unlikely to find LLT pointer type in G_INSERT_VECTOR_ELT and ask for address space.

llvm/include/llvm/Target/GenericOpcodes.td

1042

If we def : GINodeEquiv<G_INSERT_VECTOR_ELT, insertelt>;
the we also need some dependency between type0 and type1 here (type0 = vNtype1)

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

101

There were no regression tests for this.

llvm/lib/Target/Mips/MipsMSAInstrInfo.td

2279

It is fine to migrate from vector_insert to insertelt/extractelt as long as there is register class that can hold scalar size of vector. However there are no register classes of sizes 8 and 16 for mips (I think it is the same situation on arm).

Then maybe introduce another generic opcode G_INSERT_VECTOR_ELT_TRUNC. It appears when we widen scalar of element type only for G_INSERT_VECTOR_ELT. It shares remaining legalization rules with G_INSERT_VECTOR_ELT.
def : GINodeEquiv<G_INSERT_VECTOR_ELT_TRUNC, vector_insert>;

[Petar.Avramovic]

Rebase and ping.

[Petar.Avramovic]

Ping.

[Petar.Avramovic]

Rebase and update.

Enforce same type of vector scalar and elt scalar in MachineVerifier for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT.
Introducing two new similar opcodes without type constraint G_INSERT_VECTOR_ELT_TRUNC and G_ANYEXT_EXTRACT_VECTOR_ELT.
These opcodes have no corresponding llvm-IR opcodes and targets that have extending vector extract and truncating vector insert can generate them from G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT using minVectorInsOrExtScalar (minScalar respects MachineVerifier constraints for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT).
Mips has only sign and zero extending vector extracts thus G_ANYEXT_EXTRACT_VECTOR_ELT is not selectable and is replaced with default extending vector extract instruction G_SEXT_EXTRACT_VECTOR_ELT in custom legalize.
Updated tests.

[arsenm]

llvm/include/llvm/Support/TargetOpcodes.def

570

Can you split out the new opcode handling into a separate patch?

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

60–65

Why is a new legalize action needed? Why can't this just specify the existing action on the scalar operand?

llvm/utils/TableGen/CodeGenRegisters.cpp

1011–1014

I have a different workaround for this in D72771

1057–1078

This all looks like more workaround for D72771. I think the mips register definitions should just be fixed to not have aliases

llvm/utils/TableGen/GlobalISelEmitter.cpp

2569

I reproduced approximately the same thing in D72788

[Petar.Avramovic]

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

60–65

I thought that targets might need different widen scalar of elt operand in vector insert extract. Now that I think of it custom should do just fine since it is action of only 2 opcodes. Did you have other existing action in mind ?

llvm/include/llvm/Support/TargetOpcodes.def

570

Sure, will wait for your patches in emitter first.

llvm/utils/TableGen/CodeGenRegisters.cpp

1011–1014

Looks great.

llvm/utils/TableGen/GlobalISelEmitter.cpp

2569

I see, then iptr immediate index is all that is left in this patch concerning emitter.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

96–103

This belongs in a separate patch

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

598–604

This is too ugly and needs to be broken up

655–659

Ditto

664

use_nodbg?

675

No reference

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

105–108

return the logical expression

114–115

Ditto

122–125

Ditto x3 more

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
   bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
 
   /// If \p MI is extend that consumes the result of a load, try to combine it.
   /// Returns true if MI changed.
   bool tryCombineExtendingLoads(MachineInstr &MI);
   bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
   void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
 
+  /// If \p MI is extend that consumes the result of a extract_vector_elt,
+  /// try to combine it. Returns true if MI changed.
+  bool tryCombineExtendingVectorExtracts(MachineInstr &MI);
+  bool matchCombineExtendingVectorExtracts(MachineInstr &MI,
+                                           PreferredTuple &MatchInfo);
+  void applyCombineExtendingVectorExtracts(MachineInstr &MI,
+                                           PreferredTuple &MatchInfo);
+
   /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
   /// legal and the surrounding code makes it useful.
   bool tryCombineIndexedLoadStore(MachineInstr &MI);
   bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
   void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
 
   bool matchElideBrByInvertingCond(MachineInstr &MI);
   void applyElideBrByInvertingCond(MachineInstr &MI);

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h

enum {
   /// - OpIdx - Operand index
   /// - Expected type
   GIM_CheckType,
   /// Check the type of a pointer to any address space.
   /// - InsnID - Instruction ID
   /// - OpIdx - Operand index
   /// - SizeInBits - The size of the pointer value in bits.
   GIM_CheckPointerToAny,
+  /// Check the type of a pointer to any address space.
+  /// - InsnID - Instruction ID
+  /// - OpIdx - Operand index
+  /// - SizeInBits - The size of the pointer value in bits.
+  GIM_CheckScalarOfPtrSize,
   /// Check the register bank for the specified operand
   /// - InsnID - Instruction ID
   /// - OpIdx - Operand index
   /// - Expected register bank (specified as a register class)
   GIM_CheckRegBankForClass,
 
   /// Check the operand matches a complex predicate
   /// - InsnID - Instruction ID
enum {
   /// - ZeroReg - The zero register to use
   GIR_CopyOrAddZeroReg,
   /// Copy an operand to the specified instruction
   /// - NewInsnID - Instruction ID to modify
   /// - OldInsnID - Instruction ID to copy from
   /// - OpIdx - The operand to copy
   /// - SubRegIdx - The subregister to copy
   GIR_CopySubReg,
+  /// Copy an operand to the specified instruction
+  /// - NewInsnID - Instruction ID to modify
+  /// - TempRegID - The temporary register ID to to copy from
+  /// - SubRegIdx - The subregister to copy
+  GIR_CopyTmpSubReg,
 
   /// Add an implicit register def to the specified instruction
   /// - InsnID - Instruction ID to modify
   /// - RegNum - The register to add
   GIR_AddImplicitDef,
   /// Add an implicit register use to the specified instruction
   /// - InsnID - Instruction ID to modify
   /// - RegNum - The register to add

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

case GIM_CheckPointerToAny: {
         if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
           if (handleReject() == RejectAndGiveUp)
             return false;
       } else if (handleReject() == RejectAndGiveUp)
         return false;
 
       break;
     }
+    case GIM_CheckScalarOfPtrSize: {
+      int64_t InsnID = MatchTable[CurrentIdx++];
+      int64_t OpIdx = MatchTable[CurrentIdx++];
+      int64_t SizeInBits = MatchTable[CurrentIdx++];
+
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << CurrentIdx << ": GIM_CheckScalarOfPtrSize(MIs["
+                             << InsnID << "]->getOperand(" << OpIdx
+                             << ")");
+
+      assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+      MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
+      const LLT Ty = MRI.getType(MO.getReg());
+
+      // iPTR must be looked up in the target.
+      if (SizeInBits == 0) {
+        MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
+        SizeInBits = MF->getDataLayout().getPointerSizeInBits();
+      }
+
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << ", SizeInBits=" << SizeInBits << ")\n");
+      assert(SizeInBits != 0 && "Pointer size must be known");
+
+      if (MO.isReg()) {
+        if (!Ty.isScalar() || Ty.getSizeInBits() != SizeInBits)
+          if (handleReject() == RejectAndGiveUp)
+            return false;
+      } else if (handleReject() == RejectAndGiveUp)
+        return false;
+
+      break;
+    }
     case GIM_CheckRegBankForClass: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RCEnum = MatchTable[CurrentIdx++];
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), RCEnum=" << RCEnum << ")\n");
case GIR_CopySubReg: {
       OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
                                0, SubRegIdx);
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
                       dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
                              << NewInsnID << "], MIs[" << OldInsnID << "], "
                              << OpIdx << ", " << SubRegIdx << ")\n");
       break;
     }
-
+    case GIR_CopyTmpSubReg: {
+      int64_t InsnID = MatchTable[CurrentIdx++];
+      int64_t TempRegID = MatchTable[CurrentIdx++];
+      uint64_t SubRegIdx = MatchTable[CurrentIdx++];
+      assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
+      OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], 0, SubRegIdx);
+      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+                      dbgs() << "Whatever ... \n");
+      break;
+    }
     case GIR_AddImplicitDef: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RegNum = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
                       dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
                              << InsnID << "], " << RegNum << ")\n");

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

public:
   /// type.
   LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
 
   /// Legalize an instruction by performing the operation on a wider scalar type
   /// (for example a 16-bit addition can be safely performed at 32-bits
   /// precision, ignoring the unused bits).
   LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
 
+  /// Changes Opcode.
+  LegalizeResult widenVectorInsOrExtScalar(MachineInstr &MI, unsigned TypeIdx,
+                                           LLT WideTy);
+
   /// Legalize an instruction by splitting it into simpler parts, hopefully
   /// understood by the target.
   LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
 
   /// Legalize a vector instruction by splitting into multiple components, each
   /// acting on the same scalar type as the original but with fewer elements.
   LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
                                      LLT NarrowTy);

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

enum LegalizeAction : std::uint8_t {
   /// implemented in terms of 32-bit add-with-carry.
   NarrowScalar,
 
   /// The operation should be implemented in terms of a wider scalar
   /// base-type. For example a <2 x s8> add could be implemented as a <2
   /// x s32> add (ignoring the high bits).
   WidenScalar,
 
+  /// The operation should be implemented in terms of a wider scalar
+  /// base-type. Used for vector truncating insert or extending extract.
+  /// Changes opcode.
+  WidenVectorInsOrExtScalar,
+
   /// The (vector) operation should be implemented by splitting it into
   /// sub-vectors where the operation is legal. For example a <8 x s64> add
   /// might be implemented as 4 separate <2 x s64> adds.
   FewerElements,
 
   /// The (vector) operation should be implemented by widening the input
   /// vector and ignoring the lanes added by doing so. For example <2 x i8> is
   /// rarely legal, but you might perform an <8 x i8> and then only look at
   /// the first two results.
public:
   LegalizeRuleSet &minScalar(unsigned TypeIdx, const LLT &Ty) {
     using namespace LegalityPredicates;
     using namespace LegalizeMutations;
     return actionIf(LegalizeAction::WidenScalar,
                     narrowerThan(TypeIdx, Ty.getSizeInBits()),
                     changeTo(typeIdx(TypeIdx), Ty));
   }
 
+  /// Ensure the scalar is at least as wide as Ty. Also changes Opcode
+  /// G_INSERT_VECTOR_ELT -> G_INSERT_VECTOR_ELT_TRUNC
+  /// G_EXTRACT_VECTOR_ELT -> G_ANYEXT_EXTRACT_VECTOR_ELT
+  LegalizeRuleSet &minVectorInsOrExtScalar(unsigned TypeIdx, const LLT &Ty) {
+    using namespace LegalityPredicates;
+    using namespace LegalizeMutations;
+    return actionIf(LegalizeAction::WidenVectorInsOrExtScalar,
+                    narrowerThan(TypeIdx, Ty.getSizeInBits()),
+                    changeTo(typeIdx(TypeIdx), Ty));
+  }
+
   /// Ensure the scalar is at most as wide as Ty.
   LegalizeRuleSet &maxScalarOrElt(unsigned TypeIdx, const LLT &Ty) {
     using namespace LegalityPredicates;
     using namespace LegalizeMutations;
     return actionIf(LegalizeAction::NarrowScalar,
                     scalarOrEltWiderThan(TypeIdx, Ty.getScalarSizeInBits()),
                     changeElementTo(typeIdx(TypeIdx), Ty));
   }

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_BR)
 
 /// Generic branch to jump table entry.
 HANDLE_TARGET_OPCODE(G_BRJT)
 
 /// Generic insertelement.
 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
 
+// Generic insertelement. Inserts 'scalar size of vector type0' bits from type1.
+HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT_TRUNC)
+
 /// Generic extractelement.
 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
 
+/// Generic extractelement with signextend.
+HANDLE_TARGET_OPCODE(G_SEXT_EXTRACT_VECTOR_ELT)
+
+/// Generic extractelement with zeroextend.
+HANDLE_TARGET_OPCODE(G_ZEXT_EXTRACT_VECTOR_ELT)
+
+/// Generic extractelement with anyextend.
+HANDLE_TARGET_OPCODE(G_ANYEXT_EXTRACT_VECTOR_ELT)
+
 /// Generic shufflevector.
 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
 
 /// Generic count trailing zeroes.
 HANDLE_TARGET_OPCODE(G_CTTZ)
 
 /// Same as above, undefined for zero inputs.
 HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF)

llvm/include/llvm/Target/GenericOpcodes.td

 
 //------------------------------------------------------------------------------
 // Vector ops
 //------------------------------------------------------------------------------
 
 // Generic insertelement.
 def G_INSERT_VECTOR_ELT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src, type1:$elt, type2:$idx);
   let hasSideEffects = 0;
 }
 
+// Generic insertelement. Inserts 'scalar size of vector type0' bits from type1.
+def G_INSERT_VECTOR_ELT_TRUNC : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src, type1:$elt, type2:$idx);
+  let hasSideEffects = 0;
+}
+
 // Generic extractelement.
 def G_EXTRACT_VECTOR_ELT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src, type2:$idx);
   let hasSideEffects = 0;
 }
 
+// Generic extractelement with signextend.
+def G_SEXT_EXTRACT_VECTOR_ELT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src, type2:$idx);
+  let hasSideEffects = 0;
+}
+
+// Generic extractelement with zeroextend.
+def G_ZEXT_EXTRACT_VECTOR_ELT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src, type2:$idx);
+  let hasSideEffects = 0;
+}
+
+// Generic extractelement with anyextend.
+def G_ANYEXT_EXTRACT_VECTOR_ELT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src, type2:$idx);
+  let hasSideEffects = 0;
+}
+
 // Generic shufflevector.
 //
 // The mask operand should be an IR Constant which exactly matches the
 // corresponding mask for the IR shufflevector instruction.
 def G_SHUFFLE_VECTOR: GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$v1, type1:$v2, unknown:$mask);
   let hasSideEffects = 0;
 }
 
 // TODO: Add the other generic opcodes.

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

 def : GINodeEquiv<G_BR, br>;
 def : GINodeEquiv<G_BSWAP, bswap>;
 def : GINodeEquiv<G_BITREVERSE, bitreverse>;
 def : GINodeEquiv<G_CTLZ, ctlz>;
 def : GINodeEquiv<G_CTTZ, cttz>;
 def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
 def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
 def : GINodeEquiv<G_CTPOP, ctpop>;
-def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
+def : GINodeEquiv<G_INSERT_VECTOR_ELT_TRUNC, vector_insert>;
+def : GINodeEquiv<G_INSERT_VECTOR_ELT, insertelt>;
 def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
 def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
 def : GINodeEquiv<G_FCEIL, fceil>;
 def : GINodeEquiv<G_FCOS, fcos>;
 def : GINodeEquiv<G_FSIN, fsin>;
 def : GINodeEquiv<G_FABS, fabs>;
 def : GINodeEquiv<G_FSQRT, fsqrt>;
 def : GINodeEquiv<G_FFLOOR, ffloor>;
 def : GINodeEquiv<G_FRINT, frint>;
 def : GINodeEquiv<G_FNEARBYINT, fnearbyint>;
 def : GINodeEquiv<G_INTRINSIC_TRUNC, ftrunc>;
 def : GINodeEquiv<G_INTRINSIC_ROUND, fround>;
 def : GINodeEquiv<G_FCOPYSIGN, fcopysign>;
 def : GINodeEquiv<G_SMIN, smin>;
 def : GINodeEquiv<G_SMAX, smax>;
 def : GINodeEquiv<G_UMIN, umin>;
 def : GINodeEquiv<G_UMAX, umax>;
 def : GINodeEquiv<G_FMINNUM, fminnum>;
 def : GINodeEquiv<G_FMAXNUM, fmaxnum>;
 def : GINodeEquiv<G_FMINNUM_IEEE, fminnum_ieee>;
 def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
 def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
 
 // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
 // complications that tablegen must take care of. For example, Predicates such
 // as isSignExtLoad require that this is not a perfect 1:1 mapping since a
 // sign-extending load is (G_SEXTLOAD x) in GlobalISel. Additionally,
 // G_LOAD handles both atomic and non-atomic loads where as SelectionDAG had
 // separate nodes for them. This GINodeEquiv maps the non-atomic loads to
 // G_LOAD with a non-atomic MachineMemOperand.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

for (auto *UseMO : Uses) {
     // This is free on many targets.
     InsertInsnsWithoutSideEffectsBeforeUse(Builder, MI, *UseMO, InsertTruncAt);
   }
 
   MI.getOperand(0).setReg(ChosenDstReg);
   Observer.changedInstr(MI);
 }
 
+bool CombinerHelper::tryCombineExtendingVectorExtracts(MachineInstr &MI) {
+  PreferredTuple Preferred;
+  if (matchCombineExtendingVectorExtracts(MI, Preferred)) {
+    applyCombineExtendingVectorExtracts(MI, Preferred);
+    return true;
+  }
+  return false;
+}
+
+bool CombinerHelper::matchCombineExtendingVectorExtracts(
+    MachineInstr &MI, PreferredTuple &Preferred) {
+  // We match the loads and follow the uses to the extend instead of matching
+  // the extends and following the def to the load. This is because the load
+  // must remain in the same position for correctness (unless we also add code
+  // to find a safe place to sink it) whereas the extend is freely movable.
+  // It also prevents us from duplicating the load for the volatile case or just
+  // for performance.
+
+  if (MI.getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT &&
+      MI.getOpcode() != TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT &&
+      MI.getOpcode() != TargetOpcode::G_ZEXT_EXTRACT_VECTOR_ELT &&
+      MI.getOpcode() != TargetOpcode::G_ANYEXT_EXTRACT_VECTOR_ELT)
+    return false;
+
+  auto &ExtractValue = MI.getOperand(0);
+  assert(ExtractValue.isReg() && "Result wasn't a register?");
+
+  LLT ExtractValueTy = MRI.getType(ExtractValue.getReg());
+  if (!ExtractValueTy.isScalar())
+    return false;
+
+  // Find the preferred type aside from the any-extends (unless it's the only
+  // one) and non-extending ops. We'll emit an extending Extract to that type
+  // and and emit a variant of (extend (trunc X)) for the others according to
+  // the relative type sizes. At the same time, pick an extend to use based on
+  // the extend involved in the chosen type.
+  unsigned PreferredOpcode =
+     (MI.getOpcode() == TargetOpcode::G_ANYEXT_EXTRACT_VECTOR_ELT ||
+       MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT)
+          ? TargetOpcode::G_ANYEXT
+          : MI.getOpcode() == TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT
+                ? TargetOpcode::G_SEXT
+                : TargetOpcode::G_ZEXT;
+  Preferred = {LLT(), PreferredOpcode, nullptr};
+  for (auto &UseMI : MRI.use_instructions(ExtractValue.getReg())) {
+    if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
+        UseMI.getOpcode() == TargetOpcode::G_ZEXT ||
+        UseMI.getOpcode() == TargetOpcode::G_ANYEXT) {
+      Preferred = ChoosePreferredUse(Preferred,
+                                     MRI.getType(UseMI.getOperand(0).getReg()),
+                                     UseMI.getOpcode(), &UseMI);
+    }
+  }
+
+  // There were no extends
+  if (!Preferred.MI)
+    return false;
+  // It should be impossible to chose an extend without selecting a different
+  // type since by definition the result of an extend is larger.
+  assert(Preferred.Ty != ExtractValueTy && "Extending to same type?");
+
+  LLVM_DEBUG(dbgs() << "Preferred use is: " << *Preferred.MI);
+  return true;
+}
+
+void CombinerHelper::applyCombineExtendingVectorExtracts(
+    MachineInstr &MI, PreferredTuple &Preferred) {
+  // Rewrite the extract to the chosen extending extract.
+  Register ChosenDstReg = Preferred.MI->getOperand(0).getReg();
+
+  // Inserter to insert a truncate back to the original type at a given point
+  // with some basic CSE to limit truncate duplication to one per BB.
+  DenseMap<MachineBasicBlock *, MachineInstr *> EmittedInsns;
+  auto InsertTruncAt = [&](MachineBasicBlock *InsertIntoBB,
+                           MachineBasicBlock::iterator InsertBefore,
+                           MachineOperand &UseMO) {
+    MachineInstr *PreviouslyEmitted = EmittedInsns.lookup(InsertIntoBB);
+    if (PreviouslyEmitted) {
+      Observer.changingInstr(*UseMO.getParent());
+      UseMO.setReg(PreviouslyEmitted->getOperand(0).getReg());
+      Observer.changedInstr(*UseMO.getParent());
+      return;
+    }
+
+    Builder.setInsertPt(*InsertIntoBB, InsertBefore);
+    Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
+    MachineInstr *NewMI = Builder.buildTrunc(NewDstReg, ChosenDstReg);
+    EmittedInsns[InsertIntoBB] = NewMI;
+    replaceRegOpWith(MRI, UseMO, NewDstReg);
+  };
+
+  Observer.changingInstr(MI);
+  MI.setDesc(Builder.getTII().get(
+      Preferred.ExtendOpcode == TargetOpcode::G_SEXT
+          ? TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT
+          : Preferred.ExtendOpcode == TargetOpcode::G_ZEXT
+                ? TargetOpcode::G_ZEXT_EXTRACT_VECTOR_ELT
+                : TargetOpcode::G_ANYEXT_EXTRACT_VECTOR_ELT));
+
+  // Rewrite all the uses to fix up the types.
+  auto &ExtractValue = MI.getOperand(0);
+  SmallVector<MachineOperand *, 4> Uses;
+  for (auto &UseMO : MRI.use_operands(ExtractValue.getReg()))
+    Uses.push_back(&UseMO);
+
+  for (auto *UseMO : Uses) {
+    MachineInstr *UseMI = UseMO->getParent();
+
+    // If the extend is compatible with the preferred extend then we should fix
+    // up the type and extend so that it uses the preferred use.
+    if (UseMI->getOpcode() == Preferred.ExtendOpcode ||
+        UseMI->getOpcode() == TargetOpcode::G_ANYEXT) {
+      Register UseDstReg = UseMI->getOperand(0).getReg();
+      MachineOperand &UseSrcMO = UseMI->getOperand(1);
+      const LLT &UseDstTy = MRI.getType(UseDstReg);
+      if (UseDstReg != ChosenDstReg) {
+        if (Preferred.Ty == UseDstTy) {
+          replaceRegWith(MRI, UseDstReg, ChosenDstReg);
+          Observer.erasingInstr(*UseMO->getParent());
+          UseMO->getParent()->eraseFromParent();
+        } else if (Preferred.Ty.getSizeInBits() < UseDstTy.getSizeInBits()) {
+          replaceRegOpWith(MRI, UseSrcMO, ChosenDstReg);
+        } else {
+          InsertInsnsWithoutSideEffectsBeforeUse(Builder, MI, *UseMO,
+                                                 InsertTruncAt);
+        }
+        continue;
+      }
+      // The use is (one of) the uses of the preferred use we chose earlier.
+      // We're going to update the load to def this value later so just erase
+      // the old extend.
+      Observer.erasingInstr(*UseMO->getParent());
+      UseMO->getParent()->eraseFromParent();
+      continue;
+    }
+
+    // The use isn't an extend. Truncate back to the type we originally loaded.
+    // This is free on many targets.
+    InsertInsnsWithoutSideEffectsBeforeUse(Builder, MI, *UseMO, InsertTruncAt);
+  }
+
+  MI.getOperand(0).setReg(ChosenDstReg);
+  Observer.changedInstr(MI);
+}
+
 bool CombinerHelper::isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI) {
   assert(DefMI.getParent() == UseMI.getParent());
   if (&DefMI == &UseMI)
     return false;
 
   // Loop through the basic block until we find one of the instructions.
   MachineBasicBlock::const_iterator I = DefMI.getParent()->begin();
   for (; &*I != &DefMI && &*I != &UseMI; ++I)

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case Libcall:
     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
     return libcall(MI);
   case NarrowScalar:
     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
   case WidenScalar:
     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
     return widenScalar(MI, Step.TypeIdx, Step.NewType);
+  case WidenVectorInsOrExtScalar:
+    LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
+    return widenVectorInsOrExtScalar(MI, Step.TypeIdx, Step.NewType);
   case Lower:
     LLVM_DEBUG(dbgs() << ".. Lower\n");
     return lower(MI, Step.TypeIdx, Step.NewType);
   case FewerElements:
     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
   case MoreElements:
     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
if (DstTy.isVector() && !SrcTy.isVector()) {
     MI.eraseFromParent();
     return Legalized;
   }
 
   return UnableToLegalize;
 }
 
 LegalizerHelper::LegalizeResult
+LegalizerHelper::widenVectorInsOrExtScalar(MachineInstr &MI, unsigned TypeIdx,
+                                           LLT WideTy) {
+  MIRBuilder.setInstr(MI);
+  auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
+
+  switch (MI.getOpcode()) {
+  default:
+  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
+    assert(TypeIdx == 0 && "Unsupported Index");
+    Observer.changingInstr(MI);
+    widenScalarDst(MI, WideTy, 0);
+    MI.setDesc(TII.get(TargetOpcode::G_ANYEXT_EXTRACT_VECTOR_ELT));
+    Observer.changedInstr(MI);
+    return Legalized;
+  }
+  case TargetOpcode::G_INSERT_VECTOR_ELT: {
+
+    assert(TypeIdx == 1 && "Unsupported Index");
+    Observer.changingInstr(MI);
+    widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
+    MI.setDesc(TII.get(TargetOpcode::G_INSERT_VECTOR_ELT_TRUNC));
+    Observer.changedInstr(MI);
+    return Legalized;
+  }
+    return UnableToLegalize;
+  }
+}
+
+LegalizerHelper::LegalizeResult
 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   using namespace TargetOpcode;
   MIRBuilder.setInstr(MI);
 
   switch(MI.getOpcode()) {
   default:
     return UnableToLegalize;
   case TargetOpcode::G_BITCAST:

llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp

case Legal:
     OS << "Legal";
     break;
   case NarrowScalar:
     OS << "NarrowScalar";
     break;
   case WidenScalar:
     OS << "WidenScalar";
     break;
+  case WidenVectorInsOrExtScalar:
+    OS << "WidenVectorInsOrExtScalar";
+    break;
   case FewerElements:
     OS << "FewerElements";
     break;
   case MoreElements:
     OS << "MoreElements";
     break;
   case Lower:
     OS << "Lower";
case NarrowScalar: {
     // "Unsupported" unless at the ends of the vector.
     for (int i = VecIdx - 1; i >= 0; --i)
       if (!needsLegalizingToDifferentSize(Vec[i].second) &&
           Vec[i].second != Unsupported)
         return {Vec[i].first, Action};
     llvm_unreachable("");
   }
   case WidenScalar:
+  case WidenVectorInsOrExtScalar:
   case MoreElements: {
     // See above, the following needs to be a loop, at least for now.
     for (std::size_t i = VecIdx + 1; i < Vec.size(); ++i)
       if (!needsLegalizingToDifferentSize(Vec[i].second) &&
           Vec[i].second != Unsupported)
         return {Vec[i].first, Action};
     llvm_unreachable("");
   }

llvm/lib/CodeGen/MachineVerifier.cpp

for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
                MI);
     }
     if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
       report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
              "dest elt type",
              MI);
     break;
   }
+  case TargetOpcode::G_INSERT_VECTOR_ELT:
+  case TargetOpcode::G_INSERT_VECTOR_ELT_TRUNC: {
+    // Source types must be scalars, dest type a vector. Scalar types must be
+    // larger than the dest vector elt type, as this is a truncating operation.
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
+    LLT SrcEltTy = MRI->getType(MI->getOperand(2).getReg());
+    LLT IndexTy = MRI->getType(MI->getOperand(3).getReg());
+
+    if (!DstTy.isVector() || !SrcTy.isVector())
+      report("G_INSERT_VECTOR_ELT operands 0 and 1 (dst and src vector) must "
+             "be vectors",
+             MI);
+    if (DstTy != SrcTy)
+      report("G_INSERT_VECTOR_ELT operands 0 and 1 (dst and src vector) have "
+             "different types",
+             MI);
+    if (!SrcEltTy.isScalar() && !SrcEltTy.isPointer())
+      report("G_INSERT_VECTOR_ELT operand 2 (elt) must be scalar or pointer",
+             MI);
+    if (!IndexTy.isScalar())
+      report("G_INSERT_VECTOR_ELT operand 3 (index) must be a scalar", MI);
+
+    if (MI->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT)
+      if (SrcEltTy.getSizeInBits() != DstTy.getElementType().getSizeInBits())
+        report("G_INSERT_VECTOR_ELT elt type and vector scalar have different "
+               "types, try G_INSERT_VECTOR_ELT_TRUNC",
+               MI);
+    break;
+  }
+  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
+  case TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT:
+  case TargetOpcode::G_ZEXT_EXTRACT_VECTOR_ELT:
+  case TargetOpcode::G_ANYEXT_EXTRACT_VECTOR_ELT: {
+    // Source types must be scalars, dest type a vector. Scalar types must be
+    // larger than the dest vector elt type, as this is a truncating operation.
+    LLT DstEltTy = MRI->getType(MI->getOperand(0).getReg());
+    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
+    LLT IndexTy = MRI->getType(MI->getOperand(2).getReg());
+
+    if (!SrcTy.isVector())
+      report("G_EXTRACT_VECTOR_ELT operands 1 (src vector) must be a vector",
+             MI);
+    if (!DstEltTy.isScalar() && !DstEltTy.isPointer())
+      report("G_EXTRACT_VECTOR_ELT operand 0 (elt) must be scalar or pointer",
+             MI);
+    if (!IndexTy.isScalar())
+      report("G_EXTRACT_VECTOR_ELT operand 2 (index) must be a scalar", MI);
+
+    if (MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT)
+      if (DstEltTy.getSizeInBits() != SrcTy.getElementType().getSizeInBits())
+        report("G_EXTRACT_VECTOR_ELT elt type and vector scalar have different "
+               "types",
+               MI);
+    break;
+  }
   case TargetOpcode::G_CONCAT_VECTORS: {
     // Source types should be vectors, and total size should match the dest
     // vector size.
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
     if (!DstTy.isVector() || !SrcTy.isVector())
       report("G_CONCAT_VECTOR requires vector source and destination operands",
              MI);

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

getActionDefinitionsBuilder({G_LOAD, G_STORE})
           return true;
         return false;
       })
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
       .legalFor({s32, s64});
 
+  getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
+      .legalIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}) &&
+            CheckTyN(1, Query, {s32, s64}) && CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      })
+      .minVectorInsOrExtScalar(1, s32);
+
+  getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT_TRUNC)
+      .legalIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16}) &&
+            CheckTyN(1, Query, {s32}) && CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      });
+
+  getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
+      .legalIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {s32, s64}) &&
+            CheckTyN(1, Query, {v16s8, v8s16, v4s32, v2s64}) &&
+            CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      })
+      .minVectorInsOrExtScalar(0, s32);
+
+  getActionDefinitionsBuilder(
+      {G_SEXT_EXTRACT_VECTOR_ELT, G_ZEXT_EXTRACT_VECTOR_ELT})
+      .legalIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {s32, s64}) &&
+            CheckTyN(1, Query, {v16s8, v8s16, v4s32, v2s64}) &&
+            CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      });
+
+  getActionDefinitionsBuilder(G_ANYEXT_EXTRACT_VECTOR_ELT)
+      .customIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {s32}) &&
+            CheckTyN(1, Query, {v16s8, v8s16}) &&
+            CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      });
+
   getActionDefinitionsBuilder(G_UNMERGE_VALUES)
      .legalFor({{s32, s64}});
 
   getActionDefinitionsBuilder(G_MERGE_VALUES)
      .legalFor({{s64, s32}});
 
   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
case G_UITOFP: {
     else {
       MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
       MIRBuilder.buildFPTrunc(Dst, ResF64);
     }
 
     MI.eraseFromParent();
     break;
   }
+  case G_ANYEXT_EXTRACT_VECTOR_ELT: {
+    unsigned VectorScalarSize =
+        MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits();
+    assert((VectorScalarSize == 8 || VectorScalarSize == 16) &&
+           "Unsupported operand size for G_ANYEXT_EXTRACT_VECTOR_ELT");
+    MIRBuilder.buildInstr(
+        G_SEXT_EXTRACT_VECTOR_ELT, {MI.getOperand(0).getReg()},
+        {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
+    MI.eraseFromParent();
+    break;
+  }
   default:
     return false;
   }
 
   return true;
 }
 
 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,

llvm/lib/Target/Mips/MipsMSAInstrInfo.td

 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
 def MipsFMS   : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
 
 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
 
 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
-    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
+    SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
-    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
+    SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
+
+def : GINodeEquiv<G_SEXT_EXTRACT_VECTOR_ELT, MipsVExtractSExt>;
+def : GINodeEquiv<G_ZEXT_EXTRACT_VECTOR_ELT, MipsVExtractZExt>;
 
 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
 def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
 
 def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
 def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
 def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
 def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
 
 // Operands
 
 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
 
 // Pattern fragments
 def vextract_sext_i8  : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractSExt node:$vec, node:$idx, i8)>;
+                                (MipsVExtractSExt node:$vec, node:$idx)>;
 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractSExt node:$vec, node:$idx, i16)>;
+                                (MipsVExtractSExt node:$vec, node:$idx)>;
 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractSExt node:$vec, node:$idx, i32)>;
+                                (MipsVExtractSExt node:$vec, node:$idx)>;
 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractSExt node:$vec, node:$idx, i64)>;
+                                (MipsVExtractSExt node:$vec, node:$idx)>;
 
 def vextract_zext_i8  : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractZExt node:$vec, node:$idx, i8)>;
+                                (MipsVExtractZExt node:$vec, node:$idx)>;
 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractZExt node:$vec, node:$idx, i16)>;
+                                (MipsVExtractZExt node:$vec, node:$idx)>;
 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractZExt node:$vec, node:$idx, i32)>;
+                                (MipsVExtractZExt node:$vec, node:$idx)>;
 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
-                                (MipsVExtractZExt node:$vec, node:$idx, i64)>;
+                                (MipsVExtractZExt node:$vec, node:$idx)>;
 
 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
     (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
     (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
-    (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
+    (v4i32 (insertelt node:$vec, node:$val, node:$idx))>;
 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
-    (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
+    (v2i64 (insertelt node:$vec, node:$val, node:$idx))>;
 
 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
     (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
     (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
     (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8,  v16i8,
                                          MSA128BOpnd>;
 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
                                          uimm3_ptr, immZExt3Ptr, GPR32Opnd,
                                          MSA128HOpnd>;
 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
                                          uimm2_ptr, immZExt2Ptr, GPR32Opnd,
                                          MSA128WOpnd>;
 
-class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
+class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<extractelt, v4f32,
                                                  uimm2_ptr, immZExt2Ptr, FGR32,
                                                  MSA128W>;
-class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
+class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<extractelt, v2f64,
                                                  uimm1_ptr, immZExt1Ptr, FGR64,
                                                  MSA128D>;
 
 class CTCMSA_DESC {
   dag OutOperandList = (outs);
   dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
   string AsmString = "ctcmsa\t$cd, $rs";
   InstrItinClass Itinerary = NoItinerary;

 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
                                            immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
                                            immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
 
 class INSERT_B_VIDX_PSEUDO_DESC :
     MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
 class INSERT_H_VIDX_PSEUDO_DESC :
     MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
 class INSERT_W_VIDX_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
 class INSERT_D_VIDX_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
 
-class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
+class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<insertelt, v4f32,
                                                      uimm2, immZExt2Ptr,
                                                      MSA128WOpnd, FGR32Opnd>;
-class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
+class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<insertelt, v2f64,
                                                      uimm1, immZExt1Ptr,
                                                      MSA128DOpnd, FGR64Opnd>;
 
 class INSERT_FW_VIDX_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
 class INSERT_FD_VIDX_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
 
 class INSERT_B_VIDX64_PSEUDO_DESC :
     MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
 class INSERT_H_VIDX64_PSEUDO_DESC :
     MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
 class INSERT_W_VIDX64_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
 class INSERT_D_VIDX64_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
 
 class INSERT_FW_VIDX64_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
 class INSERT_FD_VIDX64_PSEUDO_DESC :
-    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
+    MSA_INSERT_VIDX_PSEUDO_BASE<insertelt, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
 
 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4,
                                          MSA128BOpnd>;
 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3,
                                          MSA128HOpnd>;
 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2,
                                          MSA128WOpnd>;
 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1,
def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
                                                     sub_lo)),
                                GPR32)>;
 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
              (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
                                                              i32:$idx),
                                                     sub_64)),
                                GPR64), [HasMSA, IsGP64bit]>;
 
-def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
+def : MSAPat<(f32 (extractelt v4f32:$ws, i32:$idx)),
              (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
                                            i32:$idx),
                                   sub_lo))>;
-def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
+def : MSAPat<(f64 (extractelt v2f64:$ws, i32:$idx)),
              (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
                                            i32:$idx),
                                   sub_64))>;
 
 // Vector extraction with variable index (N64 ABI)
 def : MSAPat<
   (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
   (SRA (COPY_TO_REGCLASS
(COPY_TO_REGCLASS
     (i64 (EXTRACT_SUBREG
            (SPLAT_D v2i64:$ws,
              (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
            sub_64)),
     GPR64),
   [HasMSA, IsGP64bit]>;
 
 def : MSAPat<
-  (f32 (vector_extract v4f32:$ws, i64:$idx)),
+  (f32 (extractelt v4f32:$ws, i64:$idx)),
   (f32 (EXTRACT_SUBREG
          (SPLAT_W v4f32:$ws,
            (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
          sub_lo))>;
 def : MSAPat<
-  (f64 (vector_extract v2f64:$ws, i64:$idx)),
+  (f64 (extractelt v2f64:$ws, i64:$idx)),
   (f64 (EXTRACT_SUBREG
          (SPLAT_D v2f64:$ws,
            (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
          sub_64))>;
 
 def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
              (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
 def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),

llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp

bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
 
   switch (MI.getOpcode()) {
   default:
     return false;
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
     return Helper.tryCombineExtendingLoads(MI);
+  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
+  case TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT:
+  case TargetOpcode::G_ZEXT_EXTRACT_VECTOR_ELT:
+    return Helper.tryCombineExtendingVectorExtracts(MI);
   }
   return false;
 }
 
 // Pass boilerplate
 // ================
 
 class MipsPreLegalizerCombiner : public MachineFunctionPass {

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case Mips::FGR32RegClassID:
   case Mips::FGR64RegClassID:
   case Mips::AFGR64RegClassID:
   case Mips::MSA128BRegClassID:
   case Mips::MSA128HRegClassID:
   case Mips::MSA128WRegClassID:
   case Mips::MSA128DRegClassID:
     return getRegBank(Mips::FPRBRegBankID);
+  case Mips::GPR64RegClassID:
+    return getRegBank(Mips::InvalidBRegBankID);
   default:
     llvm_unreachable("Register class not supported");
   }
 }
 
 // Instructions where all register operands are floating point.
 static bool isFloatingPointOpcode(unsigned Opc) {
   switch (Opc) {

 
 static bool isAmbiguous(unsigned Opc) {
   switch (Opc) {
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_PHI:
   case TargetOpcode::G_SELECT:
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_INSERT_VECTOR_ELT:
+  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
     return true;
   default:
     return false;
   }
 }
 
 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
     Register Reg, const MachineRegisterInfo &MRI) {
MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
     const MachineInstr *MI) {
   assert(isAmbiguous(MI->getOpcode()) &&
          "Not implemented for non Ambiguous opcode.\n");
 
   const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
 
   if (MI->getOpcode() == TargetOpcode::G_LOAD)
     addDefUses(MI->getOperand(0).getReg(), MRI);
+  if (MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT)
+    addDefUses(MI->getOperand(0).getReg(), MRI);
 
   if (MI->getOpcode() == TargetOpcode::G_STORE)
     addUseDef(MI->getOperand(0).getReg(), MRI);
+  if (MI->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT)
+    addUseDef(MI->getOperand(2).getReg(), MRI);
 
   if (MI->getOpcode() == TargetOpcode::G_PHI) {
     addDefUses(MI->getOperand(0).getReg(), MRI);
 
     for (unsigned i = 1; i < MI->getNumOperands(); i += 2)
       addUseDef(MI->getOperand(i).getReg(), MRI);
   }
 

 }
 
 static const MipsRegisterBankInfo::ValueMapping *getFprbMapping(unsigned Size) {
   return Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
                     : &Mips::ValueMappings[Mips::DPRIdx];
 }
 
 static const unsigned CustomMappingID = 1;
+static const unsigned CustomMappingOpcodeID = 2;
 
 // Only 64 bit mapping is available in fprb and will be marked as custom, i.e.
 // will be split into two 32 bit registers in gprb.
 static const MipsRegisterBankInfo::ValueMapping *
 getGprbOrCustomMapping(unsigned Size, unsigned &MappingID) {
   if (Size == 32)
     return &Mips::ValueMappings[Mips::GPRIdx];
 
if (!Op0Ty.isPointer())
       InstTy = TI.determineInstType(&MI);
 
     if (InstTy == InstType::FloatingPoint)
       OperandsMapping = getFprbMapping(Op0Size);
     else
       OperandsMapping = getGprbOrCustomMapping(Op0Size, MappingID);
 
     break;
+  case G_INSERT_VECTOR_ELT: {
+    const LLT Op2Ty = MRI.getType(MI.getOperand(2).getReg());
+    unsigned Op2Size = Op2Ty.getSizeInBits();
+
+    if (!Op2Ty.isPointer())
+      InstTy = TI.determineInstType(&MI);
+
+    const RegisterBankInfo::ValueMapping *MSABank = getMSAMapping(MF);
+    if (InstTy == InstType::FloatingPoint ||
+        (Op2Size == 64 && InstTy == InstType::Ambiguous))
+      OperandsMapping =
+          getOperandsMapping({MSABank, MSABank, getFprbMapping(Op2Size),
+                              &Mips::ValueMappings[Mips::GPRIdx]});
+    else
+      // Ambiguous 32 bit vector insert will be mapped to gprb to match the
+      // way other ambiguous 32 bit operands are mapped.
+      OperandsMapping = getOperandsMapping(
+          {MSABank, MSABank, getGprbOrCustomMapping(Op2Size, MappingID),
+           &Mips::ValueMappings[Mips::GPRIdx]});
+
+    break;
+  }
+  case G_INSERT_VECTOR_ELT_TRUNC: {
+    const RegisterBankInfo::ValueMapping *MSABank = getMSAMapping(MF);
+    OperandsMapping = getOperandsMapping({MSABank, MSABank,
+                                          &Mips::ValueMappings[Mips::GPRIdx],
+                                          &Mips::ValueMappings[Mips::GPRIdx]});
+    break;
+  }
+  case G_EXTRACT_VECTOR_ELT: {
+    if (!Op0Ty.isPointer())
+      InstTy = TI.determineInstType(&MI);
+
+    const RegisterBankInfo::ValueMapping *MSABank = getMSAMapping(MF);
+    if (InstTy == InstType::FloatingPoint ||
+        (Op0Size == 64 && InstTy == InstType::Ambiguous))
+      OperandsMapping =
+          getOperandsMapping({getFprbMapping(Op0Size), MSABank,
+                              &Mips::ValueMappings[Mips::GPRIdx]});
+    else {
+      // Ambiguous 32 bit vector extract will be mapped to gprb to match the
+      // way other ambiguous 32 bit operands are mapped.
+      OperandsMapping =
+          getOperandsMapping({getGprbOrCustomMapping(Op0Size, MappingID),
+                              MSABank, &Mips::ValueMappings[Mips::GPRIdx]});
+      if (Op0Size == 32 && getGprbOrCustomMapping(Op0Size, MappingID) ==
+                               &Mips::ValueMappings[Mips::GPRIdx])
+        MappingID = CustomMappingOpcodeID;
+    }
+    break;
+  }
+  case G_SEXT_EXTRACT_VECTOR_ELT:
+  case G_ZEXT_EXTRACT_VECTOR_ELT: {
+    OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
+                                          getMSAMapping(MF),
+                                          &Mips::ValueMappings[Mips::GPRIdx]});
+    break;
+  }
   case G_UNMERGE_VALUES:
     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
                                           &Mips::ValueMappings[Mips::GPRIdx],
                                           &Mips::ValueMappings[Mips::DPRIdx]});
     MappingID = CustomMappingID;
     break;
   case G_MERGE_VALUES:
     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
void MipsRegisterBankInfo::applyMappingImpl(
   MachineRegisterInfo &MRI = OpdMapper.getMRI();
   const LegalizerInfo &LegInfo = *MF->getSubtarget().getLegalizerInfo();
 
   InstManager NewInstrObserver(NewInstrs);
   GISelObserverWrapper WrapperObserver(&NewInstrObserver);
   LegalizerHelper Helper(*MF, WrapperObserver, B);
   LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), LegInfo);
 
+  if (OpdMapper.getInstrMapping().getID() == CustomMappingOpcodeID)
+    switch (MI.getOpcode()) {
+    case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
+      MRI.setRegBank(MI.getOperand(0).getReg(),
+                     getRegBank(Mips::GPRBRegBankID));
+      MI.setDesc(MI.getMF()->getSubtarget().getInstrInfo()->get(
+          TargetOpcode::G_SEXT_EXTRACT_VECTOR_ELT));
+      return;
+    }
+    default:
+      break;
+    }
+
+  if(OpdMapper.getInstrMapping().getID() == CustomMappingID)
   switch (MI.getOpcode()) {
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_PHI:
   case TargetOpcode::G_SELECT:
   case TargetOpcode::G_IMPLICIT_DEF: {
     Helper.narrowScalar(MI, 0, LLT::scalar(32));
     // Handle new instructions.

llvm/lib/Target/Mips/MipsRegisterBanks.td

 //===- MipsRegisterBank.td ---------------------------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 //
 //===----------------------------------------------------------------------===//
 
 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
 
 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
+
+def InvalidBRegBank : RegisterBank<"InvalidB", [GPR64]>;

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_BRJT (opcode {{[0-9]+}}): 2 type indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode 154): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_EXTRACT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
+# DEBUG-NEXT: G_INSERT_VECTOR_ELT_TRUNC (opcode 155): 3 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_EXTRACT_VECTOR_ELT (opcode 156): 3 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_SEXT_EXTRACT_VECTOR_ELT (opcode 157): 3 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_ZEXT_EXTRACT_VECTOR_ELT (opcode 158): 3 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_ANYEXT_EXTRACT_VECTOR_ELT (opcode 159): 3 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_CTTZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_imm_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @extract_i8_sext(<16 x i8>* %V, i32 %index) { entry: ret void }
+  define void @extract_i16_sext(<8 x i16>* %V, i32 %index) { entry: ret void }
+  define void @extract_i32_sext(<4 x i32>* %V, i32 %index) { entry: ret void }
+  define void @extract_i8_zext(<16 x i8>* %V, i32 %index) { entry: ret void }
+  define void @extract_i16_zext(<8 x i16>* %V, i32 %index) { entry: ret void }
+  define void @extract_i32_zext(<4 x i32>* %V, i32 %index) { entry: ret void }
+  define void @extract_float_fprb(<4 x float>* %V, i32 %index) { entry: ret void }
+  define void @extract_double(<2 x double>* %V, i32 %index) { entry: ret void }
+
+...
+---
+name:            extract_i8_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i8_sext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_S_B:%[0-9]+]]:gpr32 = COPY_S_B [[LD_B]], 7
+    ; P5600: $v0 = COPY [[COPY_S_B]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 7
+    %1:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %1(<16 x s8>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i16_sext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_S_H:%[0-9]+]]:gpr32 = COPY_S_H [[LD_H]], 5
+    ; P5600: $v0 = COPY [[COPY_S_H]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 5
+    %1:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %1(<8 x s16>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i32_sext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_S_W:%[0-9]+]]:gpr32 = COPY_S_W [[LD_W]], 2
+    ; P5600: $v0 = COPY [[COPY_S_W]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 2
+    %1:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i8_zext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_U_B:%[0-9]+]]:gpr32 = COPY_U_B [[LD_B]], 7
+    ; P5600: $v0 = COPY [[COPY_U_B]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 7
+    %1:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %1(<16 x s8>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i16_zext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_U_H:%[0-9]+]]:gpr32 = COPY_U_H [[LD_H]], 5
+    ; P5600: $v0 = COPY [[COPY_U_H]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 5
+    %1:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %1(<8 x s16>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i32_zext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_S_W:%[0-9]+]]:gpr32 = COPY_S_W [[LD_W]], 2
+    ; P5600: $v0 = COPY [[COPY_S_W]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 2
+    %1:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_float_fprb
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_float_fprb
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_FW:%[0-9]+]]:fgr32 = COPY_FW_PSEUDO [[LD_W]], 3
+    ; P5600: $f0 = COPY [[COPY_FW]]
+    ; P5600: RetRA implicit $f0
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 3
+    %1:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:fprb(s32) = G_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            extract_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_double
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[COPY_FD:%[0-9]+]]:fgr64 = COPY_FD_PSEUDO [[LD_D]], 1
+    ; P5600: $d0_64 = COPY [[COPY_FD]]
+    ; P5600: RetRA implicit $d0_64
+    %0:gprb(p0) = COPY $a0
+    %3:gprb(s32) = G_CONSTANT i32 1
+    %1:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:fprb(s64) = G_EXTRACT_VECTOR_ELT %1(<2 x s64>), %3(s32)
+    $d0_64 = COPY %2(s64)
+    RetRA implicit $d0_64
+
+...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_variable_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @extract_i8_sext(<16 x i8>* %V, i32 %index) { entry: ret void }
+  define void @extract_i16_sext(<8 x i16>* %V, i32 %index) { entry: ret void }
+  define void @extract_i32_sext(<4 x i32>* %V, i32 %index) { entry: ret void }
+  define void @extract_i8_zext(<16 x i8>* %V, i32 %index) { entry: ret void }
+  define void @extract_i16_zext(<8 x i16>* %V, i32 %index) { entry: ret void }
+  define void @extract_i32_zext(<4 x i32>* %V, i32 %index) { entry: ret void }
+  define void @extract_float_fprb(<4 x float>* %V, i32 %index) { entry: ret void }
+  define void @extract_double(<2 x double>* %V, i32 %index) { entry: ret void }
+
+...
+---
+name:            extract_i8_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i8_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_B:%[0-9]+]]:msa128b = SPLAT_B [[LD_B]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_B]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY3]], 24
+    ; P5600: $v0 = COPY [[SRA]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %2(<16 x s8>), %1(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i16_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_H:%[0-9]+]]:msa128h = SPLAT_H [[LD_H]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_H]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY3]], 16
+    ; P5600: $v0 = COPY [[SRA]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %2(<8 x s16>), %1(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32_sext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i32_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_W:%[0-9]+]]:msa128w = SPLAT_W [[LD_W]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_W]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: $v0 = COPY [[COPY3]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT %2(<4 x s32>), %1(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i8_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_B:%[0-9]+]]:msa128b = SPLAT_B [[LD_B]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_B]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY3]], 24
+    ; P5600: $v0 = COPY [[SRL]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %2(<16 x s8>), %1(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i16_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_H:%[0-9]+]]:msa128h = SPLAT_H [[LD_H]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_H]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY3]], 16
+    ; P5600: $v0 = COPY [[SRL]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %2(<8 x s16>), %1(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32_zext
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i32_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_W:%[0-9]+]]:msa128w = SPLAT_W [[LD_W]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_W]].sub_lo
+    ; P5600: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
+    ; P5600: $v0 = COPY [[COPY3]]
+    ; P5600: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %2(<4 x s32>), %1(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_float_fprb
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_float_fprb
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_W:%[0-9]+]]:msa128w = SPLAT_W [[LD_W]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr32 = COPY [[SPLAT_W]].sub_lo
+    ; P5600: $f0 = COPY [[COPY2]]
+    ; P5600: RetRA implicit $f0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:fprb(s32) = G_EXTRACT_VECTOR_ELT %2(<4 x s32>), %1(s32)
+    $f0 = COPY %3(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            extract_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_double
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[SPLAT_D:%[0-9]+]]:msa128d = SPLAT_D [[LD_D]], [[COPY1]]
+    ; P5600: [[COPY2:%[0-9]+]]:fgr64 = COPY [[SPLAT_D]].sub_64
+    ; P5600: $d0_64 = COPY [[COPY2]]
+    ; P5600: RetRA implicit $d0_64
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:fprb(s64) = G_EXTRACT_VECTOR_ELT %2(<2 x s64>), %1(s32)
+    $d0_64 = COPY %3(s64)
+    RetRA implicit $d0_64
+
+...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_imm_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @insert_i8(i8 %val, <16 x i8>* %V) { entry: ret void }
+  define void @insert_i16(i16 %val, <8 x i16>* %V) { entry: ret void }
+  define void @insert_i32(i32 %val, <4 x i32>* %V) { entry: ret void }
+  define void @insert_float_fprb(float %val, <4 x float>* %V) { entry: ret void }
+  define void @insert_double(double %val, <2 x double>* %V) { entry: ret void }
+
+...
+---
+name:            insert_i8
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_B:%[0-9]+]]:msa128b = INSERT_B [[LD_B]], [[COPY]], 7
+    ; P5600: ST_B [[INSERT_B]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %5:gprb(s32) = G_CONSTANT i32 7
+    %3:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %2(s32)
+    %4:fprb(<16 x s8>) = G_INSERT_VECTOR_ELT_TRUNC %3, %6(s32), %5(s32)
+    G_STORE %4(<16 x s8>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_H:%[0-9]+]]:msa128h = INSERT_H [[LD_H]], [[COPY]], 5
+    ; P5600: ST_H [[INSERT_H]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %5:gprb(s32) = G_CONSTANT i32 5
+    %3:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %2(s32)
+    %4:fprb(<8 x s16>) = G_INSERT_VECTOR_ELT_TRUNC %3, %6(s32), %5(s32)
+    G_STORE %4(<8 x s16>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_W:%[0-9]+]]:msa128w = INSERT_W [[LD_W]], [[COPY]], 2
+    ; P5600: ST_W [[INSERT_W]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_CONSTANT i32 2
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_fprb
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; P5600-LABEL: name: insert_float_fprb
+    ; P5600: liveins: $a1, $f12
+    ; P5600: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128w = INSERT_FW_PSEUDO [[LD_W]], 3, [[COPY]]
+    ; P5600: ST_W [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s32) = COPY $f12
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_CONSTANT i32 3
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d12_64
+
+    ; P5600-LABEL: name: insert_double
+    ; P5600: liveins: $a2, $d12_64
+    ; P5600: [[COPY:%[0-9]+]]:fgr64 = COPY $d12_64
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128d = INSERT_FD_PSEUDO [[LD_D]], 1, [[COPY]]
+    ; P5600: ST_D [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s64) = COPY $d12_64
+    %1:gprb(p0) = COPY $a2
+    %4:gprb(s32) = G_CONSTANT i32 1
+    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %4(s32)
+    G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_variable_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @insert_i8(i8 %val, <16 x i8>* %V, i32 %index) { entry: ret void }
+  define void @insert_i16(i16 %val, <8 x i16>* %V, i32 %index) { entry: ret void }
+  define void @insert_i32(i32 %val, <4 x i32>* %V, i32 %index) { entry: ret void }
+  define void @insert_float_fprb(float %val, <4 x float>* %V, i32 %index) { entry: ret void }
+  define void @insert_double(double %val, <2 x double>* %V, i32 %index) { entry: ret void }
+
+...
+---
+name:            insert_i8
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: insert_i8
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128b = INSERT_B_VIDX_PSEUDO [[LD_B]], [[COPY2]], [[COPY]]
+    ; P5600: ST_B [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %3:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %3(s32)
+    %5:fprb(<16 x s8>) = G_INSERT_VECTOR_ELT_TRUNC %4, %6(s32), %2(s32)
+    G_STORE %5(<16 x s8>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: insert_i16
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128h = INSERT_H_VIDX_PSEUDO [[LD_H]], [[COPY2]], [[COPY]]
+    ; P5600: ST_H [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %3:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %3(s32)
+    %5:fprb(<8 x s16>) = G_INSERT_VECTOR_ELT_TRUNC %4, %6(s32), %2(s32)
+    G_STORE %5(<8 x s16>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: insert_i32
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128w = INSERT_W_VIDX_PSEUDO [[LD_W]], [[COPY2]], [[COPY]]
+    ; P5600: ST_W [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %3:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %3, %0(s32), %2(s32)
+    G_STORE %4(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_fprb
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $a2, $f12
+
+    ; P5600-LABEL: name: insert_float_fprb
+    ; P5600: liveins: $a1, $a2, $f12
+    ; P5600: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128w = INSERT_FW_VIDX_PSEUDO [[LD_W]], [[COPY2]], [[COPY]]
+    ; P5600: ST_W [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s32) = COPY $f12
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %3:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %3, %0(s32), %2(s32)
+    G_STORE %4(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $a3, $d12_64
+
+    ; P5600-LABEL: name: insert_double
+    ; P5600: liveins: $a2, $a3, $d12_64
+    ; P5600: [[COPY:%[0-9]+]]:fgr64 = COPY $d12_64
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128d = INSERT_FD_VIDX_PSEUDO [[LD_D]], [[COPY2]], [[COPY]]
+    ; P5600: ST_D [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s64) = COPY $d12_64
+    %1:gprb(p0) = COPY $a2
+    %2:gprb(s32) = COPY $a3
+    %3:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:fprb(<2 x s64>) = G_INSERT_VECTOR_ELT %3, %0(s64), %2(s32)
+    G_STORE %4(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/extract_vector_elt_pre_isel.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @extract_i8_sext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i16_zext(<8 x i16>* %V) { entry: ret void }
+  define void @extract_i8_anyext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i32(<4 x i32>* %V) { entry: ret void }
+  define void @extract_i8_combine_immune(<16 x i8>* %V, i32 %idx, i8* %pc) { entry: ret void }
+
+...
+---
+name:            extract_i8_sext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i8_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[C]](s32)
+    ; P5600: $v0 = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %5:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT %2(<16 x s8>), %4(s32)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_zext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i16_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_ZEXT_EXTRACT_VECTOR_ELT [[LOAD]](<8 x s16>), [[C]](s32)
+    ; P5600: $v0 = COPY [[ZEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %5:_(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %2(<8 x s16>), %4(s32)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_anyext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+  
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 7
+    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:_(s32) = G_ANYEXT_EXTRACT_VECTOR_ELT %1(<16 x s8>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i32
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LOAD]](<4 x s32>), [[C]](s32)
+    ; P5600: $v0 = COPY [[EVEC]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 2
+    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:_(s32) = G_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_combine_immune
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: extract_i8_combine_immune
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[COPY1]](s32)
+    ; P5600: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: G_STORE [[COPY3]](s32), [[COPY2]](p0) :: (store 1 into %ir.pc)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:_(s8) = G_EXTRACT_VECTOR_ELT %3(<16 x s8>), %1(s32)
+    G_STORE %4(s8), %2(p0) :: (store 1 into %ir.pc)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/extract_vector_elt_pre_isel.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+define i32 @extract_i8_sext(<16 x i8>* %V) {
+; P5600-LABEL: extract_i8_sext:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.b $w0, 0($4)
+; P5600-NEXT:    copy_s.b $2, $w0[7]
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 16
+  %vecext = extractelement <16 x i8> %0, i32 7
+  %conv = sext i8 %vecext to i32
+  ret i32 %conv
+}
+
+define i32 @extract_i16_zext(<8 x i16>* %V) {
+; P5600-LABEL: extract_i16_zext:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.h $w0, 0($4)
+; P5600-NEXT:    copy_u.h $2, $w0[7]
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %V, align 16
+  %vecext = extractelement <8 x i16> %0, i32 7
+  %conv = zext i16 %vecext to i32
+  ret i32 %conv
+}
+
+define i8 @extract_i8_anyext(<16 x i8>* %V) {
+; P5600-LABEL: extract_i8_anyext:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.b $w0, 0($4)
+; P5600-NEXT:    copy_s.b $2, $w0[7]
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 16
+  %vecext = extractelement <16 x i8> %0, i32 7
+  ret i8 %vecext
+}
+
+define i32 @extract_i32(<4 x i32>* %V) {
+; P5600-LABEL: extract_i32:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.w $w0, 0($4)
+; P5600-NEXT:    copy_s.w $2, $w0[2]
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %V, align 16
+  %vecext = extractelement <4 x i32> %0, i32 2
+  ret i32 %vecext
+}
+
+define void @extract_i8_combine_immune(<16 x i8>* %V, i32 %idx, i8* %pc) {
+; P5600-LABEL: extract_i8_combine_immune:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.b $w0, 0($4)
+; P5600-NEXT:    splat.b $w0, $w0[$5]
+; P5600-NEXT:    # kill: def $f0 killed $f0 killed $w0
+; P5600-NEXT:    mfc1 $1, $f0
+; P5600-NEXT:    sra $1, $1, 24
+; P5600-NEXT:    sb $1, 0($6)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 16
+  %vecext = extractelement <16 x i8> %0, i32 %idx
+  store i8 %vecext, i8* %pc, align 1
+  ret void
+}

llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/extract_vector_elt_pre_isel.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @extract_i8_sext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i16_zext(<8 x i16>* %V) { entry: ret void }
+  define void @extract_i8_anyext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i32(<4 x i32>* %V) { entry: ret void }
+  define void @extract_i8_combine_immune(<16 x i8>* %V, i32 %idx, i8* %pc) { entry: ret void }
+
+...
+---
+name:            extract_i8_sext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i8_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[C]](s32)
+    ; P5600: $v0 = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:_(s8) = G_EXTRACT_VECTOR_ELT %2(<16 x s8>), %4(s32)
+    %5:_(s32) = G_SEXT %3(s8)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_zext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i16_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_ZEXT_EXTRACT_VECTOR_ELT [[LOAD]](<8 x s16>), [[C]](s32)
+    ; P5600: $v0 = COPY [[ZEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2(<8 x s16>), %4(s32)
+    %5:_(s32) = G_ZEXT %3(s16)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_anyext
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i8_anyext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[ANYEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_ANYEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[C]](s32)
+    ; P5600: $v0 = COPY [[ANYEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 7
+    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:_(s8) = G_EXTRACT_VECTOR_ELT %1(<16 x s8>), %3(s32)
+    %4:_(s32) = G_ANYEXT %2(s8)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i32
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LOAD]](<4 x s32>), [[C]](s32)
+    ; P5600: $v0 = COPY [[EVEC]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 2
+    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:_(s32) = G_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_combine_immune
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: extract_i8_combine_immune
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[COPY1]](s32)
+    ; P5600: G_STORE [[EVEC]](s8), [[COPY2]](p0) :: (store 1 into %ir.pc)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:_(s8) = G_EXTRACT_VECTOR_ELT %3(<16 x s8>), %1(s32)
+    G_STORE %4(s8), %2(p0) :: (store 1 into %ir.pc)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/extract_vector_elt_pre_isel.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @extract_i8_sext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i16_zext(<8 x i16>* %V) { entry: ret void }
+  define void @extract_i8_anyext(<16 x i8>* %V) { entry: ret void }
+  define void @extract_i32(<4 x i32>* %V) { entry: ret void }
+  define void @extract_i8_combine_immune(<16 x i8>* %V, i32 %idx, i8* %pc) { entry: ret void }
+
+...
+---
+name:            extract_i8_sext
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i8_sext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[C]](s32)
+    ; P5600: $v0 = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %5:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT %2(<16 x s8>), %4(s32)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i16_zext
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: extract_i16_zext
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[ZEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:gprb(s32) = G_ZEXT_EXTRACT_VECTOR_ELT [[LOAD]](<8 x s16>), [[C]](s32)
+    ; P5600: $v0 = COPY [[ZEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %4:_(s32) = G_CONSTANT i32 7
+    %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %5:_(s32) = G_ZEXT_EXTRACT_VECTOR_ELT %2(<8 x s16>), %4(s32)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_anyext
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i8_anyext
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[C]](s32)
+    ; P5600: $v0 = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 7
+    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %4:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT %1(<16 x s8>), %3(s32)
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i32
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; P5600-LABEL: name: extract_i32
+    ; P5600: liveins: $a0
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<4 x s32>), [[C]](s32)
+    ; P5600: $v0 = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %3:_(s32) = G_CONSTANT i32 2
+    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %2:_(s32) = G_EXTRACT_VECTOR_ELT %1(<4 x s32>), %3(s32)
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            extract_i8_combine_immune
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; P5600-LABEL: name: extract_i8_combine_immune
+    ; P5600: liveins: $a0, $a1, $a2
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:gprb(s32) = G_SEXT_EXTRACT_VECTOR_ELT [[LOAD]](<16 x s8>), [[COPY1]](s32)
+    ; P5600: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[SEXT_EXTRACT_VECTOR_ELT]](s32)
+    ; P5600: G_STORE [[COPY3]](s32), [[COPY2]](p0) :: (store 1 into %ir.pc)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.V)
+    %6:_(s32) = G_SEXT_EXTRACT_VECTOR_ELT %3(<16 x s8>), %1(s32)
+    %5:_(s32) = COPY %6(s32)
+    G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pc)
+    RetRA
+
+...

llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp

 namespace llvm {
 std::ostream &
 operator<<(std::ostream &OS, const LegalizeAction Act) {
   switch (Act) {
   case Lower: OS << "Lower"; break;
   case Legal: OS << "Legal"; break;
   case NarrowScalar: OS << "NarrowScalar"; break;
   case WidenScalar:  OS << "WidenScalar"; break;
+  case WidenVectorInsOrExtScalar:  OS << "WidenVectorInsOrExtScalar"; break;
   case FewerElements:  OS << "FewerElements"; break;
   case MoreElements:  OS << "MoreElements"; break;
   case Libcall: OS << "Libcall"; break;
   case Custom: OS << "Custom"; break;
   case Unsupported: OS << "Unsupported"; break;
   case NotFound: OS << "NotFound"; break;
   case UseLegacyRules: OS << "UseLegacyRules"; break;
   }

llvm/utils/TableGen/CodeGenRegisters.cpp

CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   if (!BiggestSuperRegRC)
     return None;
   BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
   std::vector<CodeGenRegisterClass *> SuperRegRCs;
   for (auto &RC : RegClasses)
     if (SuperRegRCsBV[RC.EnumValue])
       SuperRegRCs.emplace_back(&RC);
   llvm::sort(SuperRegRCs, SizeOrder);
-  assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first");
+  // It's ok to have a few classes with same size as BiggestSuperRegRC.
+  assert(SuperRegRCs.front()->getMembers().size() ==
+             BiggestSuperRegRC->getMembers().size() &&
+         "Biggest class wasn't first");
 
   // Find all the subreg classes and order them by size too.
   std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
   for (auto &RC: RegClasses) {
     BitVector SuperRegClassesBV(RegClasses.size());
     RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
     if (SuperRegClassesBV.any())
       SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
for (const auto &SuperRegClassPair : SuperRegClasses) {
         // SubRegRC that don't have super registers via SubIdx. Keep looking to
         // find a better fit and fall back on this one if there isn't one.
         //
         // This is intended to prevent X86 from making odd choices such as
         // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above.
         // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that
         // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
         // mapping.
+
+        // Mips aliases same physical registers on a few diffent classes for
+        // vectors. They hold different vector types of same total size in bits.
+        // They all have same subclassess, and we want to return
+        // std::make_pair(BiggestSuperRegRC, fgr32)
+        if ((ChosenSuperRegClass->getMembers().size() ==
+             BiggestSuperRegRC->getMembers().size()) &&
+            (ChosenSuperRegClass != BiggestSuperRegRC))
+          continue;
+
         if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
           return std::make_pair(ChosenSuperRegClass, SubRegRC);
       }
     }
 
+    if (ChosenSuperRegClass)
+      if ((ChosenSuperRegClass->getMembers().size() ==
+           BiggestSuperRegRC->getMembers().size()) &&
+          (ChosenSuperRegClass != BiggestSuperRegRC))
+        continue;
+
     // If we found a fit but it wasn't quite ideal because SubRegRC had excess
     // registers, then we're done.
     if (ChosenSuperRegClass)
       return std::make_pair(ChosenSuperRegClass, SubRegRC);
   }
 
   return None;
 }
 

llvm/utils/TableGen/GlobalISelEmitter.cpp

void emitPredicateOpcodes(MatchTable &Table,
     Table << MatchTable::Opcode("GIM_CheckPointerToAny")
           << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
           << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
           << MatchTable::Comment("SizeInBits")
           << MatchTable::IntValue(SizeInBits) << MatchTable::LineBreak;
   }
 };
 
+class ScalarOfPtrSizeMatcher : public OperandPredicateMatcher {
+protected:
+  unsigned SizeInBits;
+
+public:
+  ScalarOfPtrSizeMatcher(unsigned InsnVarID, unsigned OpIdx,
+                             unsigned SizeInBits)
+      : OperandPredicateMatcher(OPM_PointerToAny, InsnVarID, OpIdx),
+        SizeInBits(SizeInBits) {}
+
+  static bool classof(const OperandPredicateMatcher *P) {
+    return P->getKind() == OPM_PointerToAny;
+  }
+
+  void emitPredicateOpcodes(MatchTable &Table,
+                            RuleMatcher &Rule) const override {
+    Table << MatchTable::Opcode("GIM_CheckScalarOfPtrSize")
+          << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
+          << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
+          << MatchTable::Comment("SizeInBits")
+          << MatchTable::IntValue(SizeInBits) << MatchTable::LineBreak;
+  }
+};
+
 /// Generates code to check that an operand is a particular target constant.
 class ComplexPatternOperandMatcher : public OperandPredicateMatcher {
 protected:
   const OperandMatcher &Operand;
   const Record &TheDef;
 
   unsigned getAllocatedTemporariesBaseID() const;
 
public:
   }
 };
 
 Error OperandMatcher::addTypeCheckPredicate(const TypeSetByHwMode &VTy,
                                             bool OperandIsAPointer) {
   if (!VTy.isMachineValueType())
     return failedImport("unsupported typeset");
 
-  if (VTy.getMachineValueType() == MVT::iPTR && OperandIsAPointer) {
+  if (VTy.getMachineValueType() == MVT::iPTR) {
+    if (OperandIsAPointer)
       addPredicate<PointerToAnyOperandMatcher>(0);
+    else
+      addPredicate<ScalarOfPtrSizeMatcher>(0);
        return Error::success();
   }
 
   auto OpTyOrNone = MVTToLLT(VTy.getMachineValueType().SimpleTy);
   if (!OpTyOrNone)
     return failedImport("unsupported type");
 
   if (OperandIsAPointer)
     addPredicate<PointerToAnyOperandMatcher>(OpTyOrNone->get().getSizeInBits());
Table << MatchTable::Opcode("GIR_CopySubReg")
           << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx")
           << MatchTable::IntValue(Operand.getOpIdx())
           << MatchTable::Comment("SubRegIdx")
           << MatchTable::IntValue(SubReg->EnumValue)
           << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak;
   }
 };
 
+class TempSubRegRenderer : public OperandRenderer {
+protected:
+  unsigned InsnID;
+  unsigned TempRegID;
+  const CodeGenSubRegIndex *SRI;
+
+public:
+  TempSubRegRenderer(unsigned InsnID, unsigned TempRegID,
+                     const CodeGenSubRegIndex *SRI)
+      : OperandRenderer(OR_Register), InsnID(InsnID), TempRegID(TempRegID),
+        SRI(SRI) {}
+
+  static bool classof(const OperandRenderer *R) {
+    return R->getKind() == OR_TempRegister;
+  }
+
+  void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override {
+    Table << MatchTable::Opcode("GIR_CopyTmpSubReg")
+          << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
+          << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID)
+          << MatchTable::Comment("SubRegIdx")
+          << MatchTable::IntValue(SRI->EnumValue);
+    Table << MatchTable::LineBreak;
+  }
+};
 /// Adds a specific physical register to the instruction being built.
 /// This is typically useful for WZR/XZR on AArch64.
 class AddRegisterRenderer : public OperandRenderer {
 protected:
   unsigned InsnID;
   const Record *RegisterDef;
   bool IsDef;
 
Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
   const CodeGenInstruction *DstI = DstMIBuilder.getCGI();
   CodeGenInstruction *OrigDstI = &Target.getInstruction(Dst->getOperator());
 
   StringRef Name = OrigDstI->TheDef->getName();
   unsigned ExpectedDstINumUses = Dst->getNumChildren();
 
   // EXTRACT_SUBREG needs to use a subregister COPY.
   if (Name == "EXTRACT_SUBREG") {
-    if (!Dst->getChild(0)->isLeaf())
-      return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
+    if (!Dst->getChild(1)->isLeaf())
+      return failedImport("EXTRACT_SUBREG child #2?(the one with subindex) is "
+                          "not a leaf, SDNodeXForm?");
 
     if (DefInit *SubRegInit =
             dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue())) {
-      Record *RCDef = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
+      if (Dst->getChild(0)->isLeaf()) {
+        Record *RCDef =
+            getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
         if (!RCDef)
           return failedImport("EXTRACT_SUBREG child #0 could not "
                               "be coerced to a register class");
 
         CodeGenRegisterClass *RC = CGRegs.getRegClass(RCDef);
         CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
 
-      const auto SrcRCDstRCPair =
+        const auto &SrcRCDstRCPair =
             RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
         if (SrcRCDstRCPair.hasValue()) {
           assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
           if (SrcRCDstRCPair->first != RC)
             return failedImport("EXTRACT_SUBREG requires an additional COPY");
         }
 
-      DstMIBuilder.addRenderer<CopySubRegRenderer>(Dst->getChild(0)->getName(),
-                                                   SubIdx);
+        DstMIBuilder.addRenderer<CopySubRegRenderer>(
+            Dst->getChild(0)->getName(), SubIdx);
         return InsertPt;
+      } else {
+        Record *RCDef = nullptr;
+        const RecordVal *Outs =
+            Dst->getChild(0)->getOperator()->getValue("OutOperandList");
+        DagInit *OutsInit = static_cast<DagInit *>(Outs->getValue());
+        if (OutsInit->getNumArgs() != 1)
+          return failedImport("EXTRACT_SUBREG has more then 1 outs");
+        if (DefInit *VDefInit = dyn_cast<DefInit>(OutsInit->getArg(0)))
+          if (VDefInit->getDef()->isSubClassOf("RegisterOperand"))
+            RCDef = VDefInit->getDef()->getValueAsDef("RegClass");
+
+        if (!RCDef)
+          return failedImport("EXTRACT_SUBREG child #0 could not "
+                              "be coerced to a register class");
+
+        CodeGenRegisterClass *RC = CGRegs.getRegClass(RCDef);
+        CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
+        const auto &SrcRCDstRCPair =
+            RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
+        if (SrcRCDstRCPair.hasValue()) {
+          assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
+          if (SrcRCDstRCPair->first != RC)
+            return failedImport(
+                "EXTRACT_SUBREG requires an additional COPY, but it's more "
+                "likely that we got wrong class...");
         }
 
+        ArrayRef<TypeSetByHwMode> ChildTypes = Dst->getChild(0)->getExtTypes();
+        if (ChildTypes.size() != 1)
+          return failedImport("Dst pattern child has multiple results");
+
+        Optional<LLTCodeGen> OpTyOrNone = None;
+        if (ChildTypes.front().isMachineValueType())
+          OpTyOrNone =
+              MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
+        if (!OpTyOrNone)
+          return failedImport("Dst operand has an unsupported type");
+
+        unsigned TempRegID = M.allocateTempRegID();
+        InsertPt = M.insertAction<MakeTempRegisterAction>(
+            InsertPt, OpTyOrNone.getValue(), TempRegID);
+        DstMIBuilder.addRenderer<TempSubRegRenderer>(TempRegID, SubIdx);
+
+        auto InsertPtOrError = createAndImportSubInstructionRenderer(
+            ++InsertPt, M, Dst->getChild(0), TempRegID);
+        if (auto Error = InsertPtOrError.takeError())
+          return std::move(Error);
+        return InsertPtOrError.get();
+      }
+    }
     return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
   }
 
   if (Name == "REG_SEQUENCE") {
     if (!Dst->getChild(0)->isLeaf())
       return failedImport("REG_SEQUENCE child #0 is not a leaf");
 
     Record *RCDef = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
if (DstIName == "COPY_TO_REGCLASS") {
       if (DstIOpRec == nullptr)
         return failedImport(
             "COPY_TO_REGCLASS operand #1 isn't a register class");
     } else if (DstIName == "REG_SEQUENCE") {
       DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
       if (DstIOpRec == nullptr)
         return failedImport("REG_SEQUENCE operand #0 isn't a register class");
     } else if (DstIName == "EXTRACT_SUBREG") {
-      if (!Dst->getChild(0)->isLeaf())
-        return failedImport("EXTRACT_SUBREG operand #0 isn't a leaf");
-
+      if (!Dst->getChild(0)->isLeaf()) {
+        DstIOpRec = nullptr;
+        const RecordVal *Outs =
+            Dst->getChild(0)->getOperator()->getValue("OutOperandList");
+        DagInit *OutsInit = static_cast<DagInit *>(Outs->getValue());
+        if (OutsInit->getNumArgs() != 1)
+          return failedImport("EXTRACT_SUBREG has more then 1 outs");
+        if (DefInit *VDefInit = dyn_cast<DefInit>(OutsInit->getArg(0)))
+          if (VDefInit->getDef()->isSubClassOf("RegisterOperand"))
+            DstIOpRec = VDefInit->getDef()->getValueAsDef("RegClass");
+      } else
         // We can assume that a subregister is in the same bank as it's super
         // register.
         DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
 
       if (DstIOpRec == nullptr)
         return failedImport("EXTRACT_SUBREG operand #0 isn't a register class");
     } else if (DstIName == "INSERT_SUBREG") {
       auto MaybeSuperClass = inferSuperRegisterClassForNode(
           VTy, Dst->getChild(0), Dst->getChild(2));
       if (!MaybeSuperClass)
         return failedImport(
if (DstIName == "EXTRACT_SUBREG") {
     //
     // FIXME: This may introduce an extra copy if the chosen class doesn't
     //        actually contain the subregisters.
     assert(Src->getExtTypes().size() == 1 &&
              "Expected Src of EXTRACT_SUBREG to have one result type");
 
     const auto SrcRCDstRCPair =
       (*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
+    if (!SrcRCDstRCPair.hasValue())
+      return failedImport(
+          "EXTRACT_SUBREG didn't find classes for constraints?\n");
     assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
     M.addAction<ConstrainOperandToRegClassAction>(0, 0, *SrcRCDstRCPair->second);
     M.addAction<ConstrainOperandToRegClassAction>(0, 1, *SrcRCDstRCPair->first);
 
     // We're done with this pattern!  It's eligible for GISel emission; return
     // it.
     ++NumPatternImported;
     return std::move(M);