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TableGen: Work around assert on Mips register definitions
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Authored by arsenm on Jan 15 2020, 8:40 AM.

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Summary

This would hit the "Biggest class wasn't first" assert in
getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG
handling.

Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW,
MSA128D). These have the same set of registers, and only differ by the
isel type. I believe this is an ill formed way of defining registers,
that probably is just to work around the inconvenience of mixing
different types in a single register class in DAG patterns.

Since these all have the same size, they would all sort to the
beginning, but you would not necessarily get the same super register
at the front as the assert enforces. Breaking the ambiguity by also
sorting by name doesn't work, since each of these register classes all
want to be first. Force sorting of the original register class if the
size is the same.

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Event Timeline

arsenm created this revision.Jan 15 2020, 8:40 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2020, 8:40 AM
atanasyan accepted this revision.Jan 16 2020, 4:06 AM

LGTM

I'll take a look on MIPS vector register definitions. Four register classes looks really ill formed.

This revision is now accepted and ready to land.Jan 16 2020, 4:06 AM