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[Aarch64][SVE] Add intrinsics for gather loads (vector + imm)
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Authored by andwar on Nov 28 2019, 2:07 AM.

Details

Summary

This patch adds intrinsics for SVE gather loads from memory addresses generated by a vector base plus immediate index:

  • @llvm.aarch64.sve.ld1.gather.imm

This intrinsics maps 1-1 to the corresponding SVE instruction (example for half-words):

  • ld1h { z0.d }, p0/z, [z0.d, #16]

Diff Detail

Event Timeline

andwar created this revision.Nov 28 2019, 2:07 AM
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andwar marked an inline comment as done.Nov 28 2019, 2:45 AM
andwar added inline comments.
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
458

This should remain as uimm5s2. I will fix this in the following patch.

andwar updated this revision to Diff 231713.Dec 2 2019, 8:01 AM
  • Reverted one incorrect (introduced by mistake) change in a TableGen pattern ( uimm5s2 vs uimm5s4)
  • Created a TableGen class for the intrinsics introduced here - for consistency with the other patches for gather loads
sdesmalen accepted this revision.Dec 2 2019, 9:22 AM

LGTM!

This revision is now accepted and ready to land.Dec 2 2019, 9:22 AM
This revision was automatically updated to reflect the committed changes.