[ARM][Thumb2] Fix ADD/SUB invalid writes to SP

[dnsampaio]

Summary

This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80".
The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable.
To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP).
Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations.
When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant )
It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt).

[dnsampaio]

Refactored emitT2RegPlusImmediate

[dnsampaio]

Fixed adr.w decoding

[dnsampaio]

Cleared some bits
Added bug test

[dnsampaio]

Re-inserted missing t2SUBri disassemble

[dnsampaio]

llvm/test/MC/ARM/invalid-addsub.s

17–20

Ups, missing ones. Will fix.

[dnsampaio]

Returned tests of invalid sub sp

[ostannard]

This looks like multiple bug-fixes in one patch, could they be split up?

[dnsampaio]

In D70680#1765493, @ostannard wrote:

This looks like multiple bug-fixes in one patch, could they be split up?

Not that trivial, the adr bug only appears after splitting t2(sub|add)ri. And the hardcoded emission of t2 register +/- immediate needs to be fixed once we split the instructions for not emitting invalid instructions. As well the disassembly part fails if done apart.

[efriedma]

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

1173

I'm a little surprised the ri12 variants were missing here. I guess the frame setup code doesn't use them. Still fine to add, though.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

3266

Do we need to care about the source register here? t2ADDrr doesn't restrict it. (I guess that might also be a bug?)

llvm/lib/Target/ARM/ARMFrameLowering.cpp

1531 ↗

(On Diff #231443)

We can't generate t2ADDspImm with a frame index; that wouldn't make any sense.

llvm/lib/Target/ARM/ARMInstrThumb2.td

2854

This pattern is dead code. Same for the other new patterns.

4838

Need testcases for all these aliases.

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

711

Not your patch, but the way Thumb1 is handling SP here doesn't make any sense. Maybe add a FIXME?

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7750

Is this Error actually reachable? If it is, please add a testcase.

9809

Please don't copy-paste code.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

Please don't copy-paste code.

llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

108–109

This test should probably be using CHECK-next to make it clear what's happening. (Please commit separately.)

Is it necessary to change the instruction sequence in this patch? I'd prefer to split the optimization into a separate patch.

llvm/test/MC/Disassembler/ARM/thumb-tests.txt

285

Why does this need to change?

llvm/test/MC/Disassembler/ARM/thumb2.txt

93

What part of the patch changes the preferred disassembly here? Can it be split into a separate patch?

[john.brawn]

llvm/lib/Target/ARM/ARMInstrThumb2.td

926–939

This duplicates a lot of what's in T2sTwoRegImm, and also incorrectly forces bit 20 (which encodes the 's' bit) to 0 causing adds to be encoded as add.

I think what should be here is the same as the ri variant, but with "let Rn = 13; let Rd = 13;" at the top.

981

Should comment that this is the S bit, for consistency with ri12 variant above.

[dnsampaio]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

3266

From my tests, rr does block writing to SP and not reading from it:

./llvm-mc --assemble  -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9 --show-encoding <<< "add.w sp, r0, r1"
        .section        __TEXT,__text,regular,pure_instructions
<stdin>:1:7: error: source register must be sp if destination is sp
add.w sp, r0, r1

In that case, just checking that the destination is SP is enough.

llvm/lib/Target/ARM/ARMInstrThumb2.td

926–939

Is there a special way to do those let? From the ones I managed to compile, using

let Rn = 13 in
let Rd = 13 in
def spImm...

I kept getting error: Duplicate predicate in FastISel table!. So I reduced as much as possible, fixing not setting the S bit (20).

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

9809

I'm guessing you are speaking about the ADD and SUB joining in a single case statement, right?

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

Again, not quite sure, but guessing I can reduce the if/else common parts.

llvm/test/MC/Disassembler/ARM/thumb-tests.txt

285

That was just a mistake in submitting this patch, wanted to investigate why this test keeps warning, as this (and printing a instruction of different encoding):

llvm-mc --disassemble --show-encoding -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9 <<< "0x1 0xea 0xfa 0x95"
<stdin>:1:1: warning: potentially undefined instruction encoding
0x1 0xea 0xfa 0x95
^
        and.w   r5, r1, r10, ror #7     @ encoding: [0x01,0xea,0xfa,0x15]

llvm/test/MC/Disassembler/ARM/thumb2.txt

93

These broke as soon as I've changed the table-gen, will try to pin-point what change it and see if can be done into other patch. Most unlikely, as the adr disassembly part was never used.

[dnsampaio]

llvm/lib/Target/ARM/ARMInstrThumb2.td

926–939

Never-mind, I just did set them inside the definition and it works.

[efriedma]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

3266

We might need to split t2ADDrr eventually, but I guess this is fine for now.

[efriedma]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

9809

I was more thinking that the t2ADDri12 and t2ADDspImm12 handling are basically identical. But I guess add/sub are also almost identical.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

Nevermind; I assumed you copy-pasted this without really checking.

Why do we need a C++ DecoderMethod for t2ADDspImm, when we don't need one for t2ADDri?

[dnsampaio]

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

711

What do you mean with the SP handling of thumb1? There is a section just below handling if (BaseOpc == ARM::tADDrSPi).

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7750

Indeed it does not make any sense. Getting rid of it.

9809

Fair enough. Will join all 4 in a single case.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

If I don't use a custom decoder, the disassembly of the instruction 0x0d 0xf1 0x00 0x0d (should disassemble as add.w sp, sp, #0) is matched as a ADR, t2ADR in the generated build/lib/Target/ARM/ARMGenAsmWriter.inc. I'm not fully aware of why yet, probably the same reason why ADR was being decoded as SUB?
The ADR instruction seems to have less operands and the disassembler dies with the below error when printing the cc_out operand,:

/work/bf/LLVM/build/bin/llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble < /tmp/a
        .section        __TEXT,__text,regular,pure_instructions
        adds.w  r1, r2, #496
        addllvm-mc: /work/bf/LLVM/src/llvm/include/llvm/ADT/SmallVector.h:153: const T& llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) const [with T = llvm::MCOperand; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::const_reference = const llvm::MCOperand&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed.
Stack dump:
0.      Program arguments: /work/bf/LLVM/build/bin/llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble 
 #0 0x00007f342f10611d llvm::sys::PrintStackTrace(llvm::raw_ostream&) /work/bf/LLVM/src/llvm/lib/Support/Unix/Signals.inc:548:22
 #1 0x00007f342f1061b0 PrintStackTraceSignalHandler(void*) /work/bf/LLVM/src/llvm/lib/Support/Unix/Signals.inc:609:1
 #2 0x00007f342f103fe0 llvm::sys::RunSignalHandlers() /work/bf/LLVM/src/llvm/lib/Support/Signals.cpp:68:20
 #3 0x00007f342f105a9c SignalHandler(int) /work/bf/LLVM/src/llvm/lib/Support/Unix/Signals.inc:390:1
 #4 0x00007f342e5b14b0 (/lib/x86_64-linux-gnu/libc.so.6+0x354b0)
 #5 0x00007f342e5b1428 raise /build/glibc-LK5gWL/glibc-2.23/signal/../sysdeps/unix/sysv/linux/raise.c:54:0
 #6 0x00007f342e5b302a abort /build/glibc-LK5gWL/glibc-2.23/stdlib/abort.c:91:0
 #7 0x00007f342e5a9bd7 __assert_fail_base /build/glibc-LK5gWL/glibc-2.23/assert/assert.c:92:0
 #8 0x00007f342e5a9c82 (/lib/x86_64-linux-gnu/libc.so.6+0x2dc82)
 #9 0x00007f343641da0f llvm::SmallVectorTemplateCommon<llvm::MCOperand, void>::operator[](unsigned long) const /work/bf/LLVM/src/llvm/include/llvm/ADT/SmallVector.h:154:19
#10 0x00007f343641d851 llvm::MCInst::getOperand(unsigned int) const /work/bf/LLVM/src/llvm/include/llvm/MC/MCInst.h:180:71
#11 0x00007f34364199e0 llvm::ARMInstPrinter::printSBitModifierOperand(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) /work/bf/LLVM/src/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp:997:35
#12 0x00007f3436408771 llvm::ARMInstPrinter::printInstruction(llvm::MCInst const*, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) /work/bf/LLVM/build/lib/Target/ARM/ARMGenAsmWriter.inc:9164:26
#13 0x00007f34364164ba llvm::ARMInstPrinter::printInst(llvm::MCInst const*, llvm::raw_ostream&, llvm::StringRef, llvm::MCSubtargetInfo const&) /work/bf/LLVM/src/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp:307:18
#14 0x00007f342f913b4c llvm::MCTargetStreamer::prettyPrintAsm(llvm::MCInstPrinter&, llvm::raw_ostream&, llvm::MCInst const&, llvm::MCSubtargetInfo const&) /work/bf/LLVM/src/llvm/lib/MC/MCStreamer.cpp:983:1
#15 0x00007f342f8933a9 (anonymous namespace)::MCAsmStreamer::EmitInstruction(llvm::MCInst const&, llvm::MCSubtargetInfo const&) /work/bf/LLVM/src/llvm/lib/MC/MCAsmStreamer.cpp:1947:40
#16 0x0000000000431159 PrintInsts(llvm::MCDisassembler const&, std::pair<std::vector<unsigned char, std::allocator<unsigned char> >, std::vector<char const*, std::allocator<char const*> > > const&, llvm::SourceMgr&, llvm::raw_ostream&, llvm::MCStreamer&, bool, llvm::MCSubtargetInfo const&) /work/bf/LLVM/src/llvm/tools/llvm-mc/Disassembler.cpp:73:7
#17 0x0000000000431a62 llvm::Disassembler::disassemble(llvm::Target const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, llvm::MCSubtargetInfo&, llvm::MCStreamer&, llvm::MemoryBuffer&, llvm::SourceMgr&, llvm::MCContext&, llvm::raw_ostream&, llvm::MCTargetOptions const&) /work/bf/LLVM/src/llvm/tools/llvm-mc/Disassembler.cpp:197:34
#18 0x00000000004190fd main /work/bf/LLVM/src/llvm/tools/llvm-mc/llvm-mc.cpp:521:36
#19 0x00007f342e59c830 __libc_start_main /build/glibc-LK5gWL/glibc-2.23/csu/../csu/libc-start.c:325:0
#20 0x0000000000416f29 _start (/work/bf/LLVM/build/bin/llvm-mc+0x416f29)
Aborted (core dumped)

[efriedma]

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

711

I mean that we try to use tSUBi8 on SP.

But I guess that can't actually happen. If "Offset < 0" is true, we can't be in Thumb1 mode because there aren't any load/store instructions with negative offsets. So the "Base != ARM::SP" check here is unnecessary.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

I don't follow why it's crashing; if it matched adr, it would be trying to print an adr, not an add. The immediate cause of the crash is that the printer is expecting an operand to represent the "s" bit, and isn't finding it. But ARM::t2ADDspImm should have an operand to represent the "s" bit.

I guess there's a sort of weird overlap here; DecoderGPRRegisterClass returns SoftFail where it should actually be hard-failing. So the ri/ri12 variants actually match in cases where we don't want them to. I would have expected that to mean you need a decoder for the ri/ri12 variants, not the sp variants, though, and I don't think it would cause a crash.

[dnsampaio]

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

711

Got it. Adding a FIXME here for it.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6622

Changing DecoderGPRRegisterClass to return a MCDisassembler::Fail breaks some tests. Would it be ok if I keep the custom decoder for now, and add a FIXME to the DecoderGPRRegisterClass?

[dnsampaio]

Added fixme to ARMLoadStoreOptimizer due negative offset
Added test-cases for all added (and fixed existing) thumb2 add/sub alias

[dnsampaio]

• undo some clang-format-diff changes

[dnsampaio]

Removed dead/wrong tablegen t2InstSubst, defining a t2ADDri12 using t2_so_imm_neg instead of imm0_4095_neg

[efriedma]

llvm/lib/Target/ARM/ARMInstrThumb2.td

2353

These patterns are unreachable.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

9851

Is this new behavior? Or was this handled elsewhere before, somehow?

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

5606

I assume this is supposed to reject adr sp, #label etc. Is this new behavior? If it is, can you split it into a separate patch?

Not sure what the Inst.getNumOperands() check is supposed to be doing.

5611

This could probably use a comment. It looks like it's handling sub r0, pc, #0? (That should actually be a valid instruction, as far as I know.)

[dnsampaio]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

9851

It is not a new behavior, it was handled elsewhere. The only reference I can find about such conversions is in Thumb2SizeReduce::ReduceSpecial

running llvm-mc -triple=thumbv7 -show-encoding <<< "add sp, #508"

llvm_currently

add     sp, #508                @ encoding: [0x7f,0xb0]

this_patch_without_this_part

add.w   sp, sp, #508            @ encoding: [0x0d,0xf5,0xfe,0x7d]

the_entire_patch

add     sp, #508                @ encoding: [0x7f,0xb0]

Perhaps we might lose the optimization when we obtain a node that is a t2ADDspImm that could be converted to t1, but I prefer to leave that to another patch.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

5606

About the Inst.getNumOperands(), I was confused if Inst was empty here or not, as some case statements create new instructions instead of using this one. I replaced it by an assert that Inst should be empty.

Yes indeed it is a change of behavior. It will fail to accept sp to thumbv7.

Currently we have the same warning for both thumbv7 and thumbv8 when doing:
llvm-mc-9 --disassemble -triple=thumbv8 -show-encoding <<< "0x0f,0xf2,0x08,0x0d"
we obtain:

<stdin>:1:1: warning: potentially undefined instruction encoding
0x0f,0xf2,0x08,0x0d
^
        addw    sp, pc, #8              @ encoding: [0x0f,0xf2,0x08,0x0d]

After the patch, it will stop warning for thumbv8 and will hard-fail for thumbv7. (indeed, it should not accept the softfail given by DecoderGPRRegisterClass ).

I can't move this changes to a distinct patch, as this code is not even executed currently. When I create the spImm variants in table-gen is when this decoder is actually used. Before, the instructions are either decoded as addw or subw, never as adr.w.

5611

Indeed it is a perfectly valid instruction. Is the singular case where (following the ARMv7-M Architecture Reference Manual) that the ADR.w Encoding T2 with offset zero is decoded as a sub. Here we add the pc operand to the operation. Indeed, it should use the function DecodeGPRRegisterClass, not DecoderGPRRegisterClass.

So we will preserve the current behavior when doing:
llvm-mc --disassemble -triple=thumbv7 -mcpu=cortex-a8 -show-encoding <<< "0xaf 0xf2 0x00 0x00"
giving:
subw r0, pc, #0 @ encoding: [0xaf,0xf2,0x00,0x00]

The changes appear when the offset is not zero, such as: "0xaf 0xf2 0x01 0x00"

currently

subw    r0, pc, #1              @ encoding: [0xaf,0xf2,0x01,0x00]

will_be

adr.w   r0, #-1                 @ encoding: [0xaf,0xf2,0x01,0x00]

[dnsampaio]

Requested fixes:

• Removed unreachable patterns
• Added v8 and v7 tests showing different decoder behavior of adr.w writting to sp ( and fixed the code by rejecting softfail )
• Added comment that adr.w with negative zero offset is decoded as subw .. pc, 0

[efriedma]

llvm/lib/Target/ARM/ARMInstrThumb2.td

930

"let Inst{26} = imm{11};"

This looks suspicious.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

5603

Extra parentheses.

5606

Okay, makes sense.

Not sure why you need to hard-fail instead of soft-fail here for thumbv7; does something else break? (Please add a brief comment explaining.)

llvm/test/MC/Disassembler/ARM/thumb2-v8.txt

43

Whitespace.

[dnsampaio]

Requested fixes

[dnsampaio]

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

5606

Indeed it won't break, is just that I didn't realize that the standard was to emit a warning, instead of an error. Fixing it.

[efriedma]

LGTM

[dnsampaio]

Looking into CodeGen/Thumb2/thumb2-mov.ll test failure.

[dnsampaio]

In D70680#1813841, @dnsampaio wrote:

Looking into CodeGen/Thumb2/thumb2-mov.ll test failure.

Seems like a peephole optimizer inverting the two operands, without validating their register types.

[dnsampaio]

• Fixed the destination register class when converting ADDrr to ADDri or ADDspImm. Added test
• Fixed the number of arguments when converting t2SUBspImm to tSUBspi by adding a register at the end. Else, it would break llvm-mca that expects the number of operands to follow the table-gen, even when not used by the instruction.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

if (SrcReg == ARM::SP) {
         MI->print(errs());
         llvm_unreachable("Unsupported opcode for unwinding information");
       case ARM::MOVr:
       case ARM::tMOVr:
         Offset = 0;
         break;
       case ARM::ADDri:
       case ARM::t2ADDri:
       case ARM::t2ADDri12:
+      case ARM::t2ADDspImm:
+      case ARM::t2ADDspImm12:
         Offset = -MI->getOperand(2).getImm();
         break;
       case ARM::SUBri:
       case ARM::t2SUBri:
       case ARM::t2SUBri12:
+      case ARM::t2SUBspImm:
+      case ARM::t2SUBspImm12:
         Offset = MI->getOperand(2).getImm();
         break;
       case ARM::tSUBspi:
         Offset = MI->getOperand(2).getImm()*4;
         break;
       case ARM::tADDspi:
       case ARM::tADDrSPi:
         Offset = -MI->getOperand(2).getImm()*4;

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

case ARM::EORrr:
       SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
       switch (UseOpc) {
       default: break;
       case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
       case ARM::EORrr: NewUseOpc = ARM::EORri; break;
       }
       break;
     case ARM::t2ADDrr:
-    case ARM::t2SUBrr:
+    case ARM::t2SUBrr: {
       if (UseOpc == ARM::t2SUBrr && Commute)
         return false;
 
       // ADD/SUB are special because they're essentially the same operation, so
       // we can handle a larger range of immediates.
+      const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP;
+      const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
+      const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
       if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
-        NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
+        NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
       else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
         ImmVal = -ImmVal;
-        NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
+        NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
       } else
         return false;
       SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
       SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
       break;
+    }
     case ARM::t2ORRrr:
     case ARM::t2EORrr:
       if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
         return false;
       SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
       SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
       switch (UseOpc) {
       default: break;
       case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
       case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
       }
       break;
     }
   }
   }
 
   unsigned OpIdx = Commute ? 2 : 1;
   Register Reg1 = UseMI.getOperand(OpIdx).getReg();
   bool isKill = UseMI.getOperand(OpIdx).isKill();
-  Register NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
+  const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
+  Register NewReg = MRI->createVirtualRegister(TRC);
   BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
           NewReg)
       .addReg(Reg1, getKillRegState(isKill))
       .addImm(SOImmValV1)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
   UseMI.setDesc(get(NewUseOpc));
   UseMI.getOperand(1).setReg(NewReg);
   UseMI.getOperand(1).setIsKill();
   UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
   DefMI.eraseFromParent();
+  // FIXME: t2ADDrr should be split, as different rulles apply when writing to SP.
+  // Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm].
+  // Then the below code will not be needed, as the input/output register
+  // classes will be rgpr or gprSP.
+  // For now, we fix the UseMI operand explicitly here:
+  switch(NewUseOpc){
+    case ARM::t2ADDspImm:
+    case ARM::t2SUBspImm:
+    case ARM::t2ADDri:
+    case ARM::t2SUBri:
+      MRI->setRegClass(UseMI.getOperand(0).getReg(), TRC);
+  }
   return true;
 }
 
 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
                                         const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: {
     const MCInstrDesc &Desc = MI.getDesc();

llvm/lib/Target/ARM/ARMInstrThumb2.td

 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
 /// patterns for a binary operation that produces a value.
 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
                           bit Commutable = 0> {
    // shifted imm
    // The register-immediate version is re-materializable. This is useful
    // in particular for taking the address of a local.
    let isReMaterializable = 1 in {
+    def spImm : T2sTwoRegImm<
+              (outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi,
+              opc, ".w\t$Rd, $Rn, $imm",
+              []>,
+              Sched<[WriteALU, ReadALU]> {
+    let  Rn = 13;
+    let  Rd = 13;
+
+    let Inst{31-27} = 0b11110;
+    let Inst{25-24} = 0b01;
+    let Inst{23-21} = op23_21;
+    let Inst{15}    = 0;
+
+    let DecoderMethod = "DecodeT2AddSubSPImm";
+   }
+
    def ri : T2sTwoRegImm<
-               (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
+               (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
                opc, ".w\t$Rd, $Rn, $imm",
-               [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
+               [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
                Sched<[WriteALU, ReadALU]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24} = 1;
      let Inst{23-21} = op23_21;
      let Inst{15} = 0;
    }
    }
    // 12-bit imm
    def ri12 : T2I<
-                  (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
+                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
                   !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
-                  [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
+                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
                   Sched<[WriteALU, ReadALU]> {
      bits<4> Rd;
      bits<4> Rn;
      bits<12> imm;
      let Inst{31-27} = 0b11110;
      let Inst{26} = imm{11};
      let Inst{25-24} = 0b10;
      let Inst{23-21} = op23_21;
      let Inst{20} = 0; // The S bit.
      let Inst{19-16} = Rn;
      let Inst{15} = 0;
      let Inst{14-12} = imm{10-8};
      let Inst{11-8} = Rd;
      let Inst{7-0} = imm{7-0};
    }
+     def spImm12 : T2I<
+                    (outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi,
+                    !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
+                    []>,
+                    Sched<[WriteALU, ReadALU]> {
+       bits<4> Rd = 13;
+       bits<4> Rn = 13;
+       bits<12> imm;
+       let Inst{31-27} = 0b11110;
+       let Inst{26} = imm{11};
+       let Inst{25-24} = 0b10;
+       let Inst{23-21} = op23_21;
+       let Inst{20} = 0; // The S bit.
+       let Inst{19-16} = Rn;
+       let Inst{15} = 0;
+       let Inst{14-12} = imm{10-8};
+       let Inst{11-8} = Rd;
+       let Inst{7-0} = imm{7-0};
+       let DecoderMethod = "DecodeT2AddSubSPImm";
+     }
    // register
    def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
                  IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
                  [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
                  Sched<[WriteALU, ReadALU, ReadALU]> {
      let isCommutable = Commutable;
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;

 }
 
 def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",
                  (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",
                  (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
 
 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
-                 (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
-def : t2InstSubst<"addw${p} $rd, $rn, $imm",
-                 (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
+                 (t2SUBri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
-                 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
-def : t2InstSubst<"subw${p} $rd, $rn, $imm",
-                 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
+                 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
-                 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+                 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
 def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
-                 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
+                 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
 def : t2InstSubst<"sub${p} $rd, $rn, $imm",
-                 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
+                 (t2ADDri12 rGPR:$rd, GPR:$rn, imm0_4095_neg:$imm, pred:$p)>;
+
+// SP to SP alike
+def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
+                 (t2SUBspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
+                 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
+                 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
+                 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
+def : t2InstSubst<"sub${p} $rd, $rn, $imm",
+                 (t2ADDspImm12 GPRsp:$rd, GPRsp:$rn, imm0_4095_neg:$imm, pred:$p)>;
+
+
 // RSB
 defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb", sub>;
 
 // FIXME: Eliminate them if we can write def : Pat patterns which defines
 // CPSR and the implicit def of CPSR is not needed.
 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
 // The assume-no-carry-in form uses the negation of the input since add/sub
 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
 // details.
 // The AddedComplexity preferences the first variant over the others since
 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
 let AddedComplexity = 1 in
-def : T2Pat<(add        GPR:$src, imm1_255_neg:$imm),
-            (t2SUBri    GPR:$src, imm1_255_neg:$imm)>;
-def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
-            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
-def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
-            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
+def : T2Pat<(add        rGPR:$src, imm1_255_neg:$imm),
+            (t2SUBri    rGPR:$src, imm1_255_neg:$imm)>;
+def : T2Pat<(add        rGPR:$src, t2_so_imm_neg:$imm),
+            (t2SUBri    rGPR:$src, t2_so_imm_neg:$imm)>;
+def : T2Pat<(add        rGPR:$src, imm0_4095_neg:$imm),
+            (t2SUBri12  rGPR:$src, imm0_4095_neg:$imm)>;
 def : T2Pat<(add        GPR:$src, imm0_65535_neg:$imm),
             (t2SUBrr    GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
 
 // Do the same for v8m targets since they support movw with a 16-bit value.
 def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
              (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>,
              Requires<[HasV8MBaseline]>;
 
 let AddedComplexity = 1 in
 def : T2Pat<(ARMaddc    rGPR:$src, imm1_255_neg:$imm),
             (t2SUBSri   rGPR:$src, imm1_255_neg:$imm)>;
 def : T2Pat<(ARMaddc    rGPR:$src, t2_so_imm_neg:$imm),

 
 def : T2Pat<(t2_so_imm_not:$src),
             (t2MVNi t2_so_imm_not:$src)>;
 
 // There are shorter Thumb encodings for ADD than ORR, so to increase
 // Thumb2SizeReduction's chances later on we select a t2ADD for an or where
 // possible.
 def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),
-            (t2ADDri $Rn, t2_so_imm:$imm)>;
+            (t2ADDri rGPR:$Rn, t2_so_imm:$imm)>;
 
 def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),
-            (t2ADDri12 $Rn, imm0_4095:$Rm)>;
+            (t2ADDri12 rGPR:$Rn, imm0_4095:$Rm)>;
 
 def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),
             (t2ADDrr $Rn, $Rm)>;
 
 //===----------------------------------------------------------------------===//
 //  Multiply Instructions.
 //
 let isCommutable = 1 in
 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
                 "mul", "\t$Rd, $Rn, $Rm",
                 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,

 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
                   (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 
 // Aliases for ADD without the ".w" optional width specifier.
 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
-        (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
+        (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
          cc_out:$s)>;
 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
-           (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
+           (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
               (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 // ... and with the destination and source register combined.
 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
-      (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+      (t2ADDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"add${p} $Rdn, $imm",
-           (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
+           (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;
+def : t2InstAlias<"addw${p} $Rdn, $imm",
+           (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;
 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
             (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
                   (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 
 // add w/ negative immediates is just a sub.
 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
-        (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
+        (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
                  cc_out:$s)>;
 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
-           (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
 def : t2InstSubst<"add${s}${p} $Rdn, $imm",
-      (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
+      (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p,
                cc_out:$s)>;
 def : t2InstSubst<"add${p} $Rdn, $imm",
-           (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
 
 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
-        (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
+        (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
                  cc_out:$s)>;
 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
-           (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rd, rGPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
-      (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
+      (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p,
                cc_out:$s)>;
 def : t2InstSubst<"addw${p} $Rdn, $imm",
-           (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
 
 
 // Aliases for SUB without the ".w" optional width specifier.
 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
-        (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+        (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
-           (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
               (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 // ... and with the destination and source register combined.
 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
-      (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+      (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sub${p} $Rdn, $imm",
-           (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
+           (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;
+def : t2InstAlias<"subw${p} $Rdn, $imm",
+           (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;
 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
             (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
             (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
                   (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
 
+// SP to SP alike aliases
+// Aliases for ADD without the ".w" optional width specifier.
+def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
+        (t2ADDspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p,
+         cc_out:$s)>;
+def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
+           (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
+// ... and with the destination and source register combined.
+def : t2InstAlias<"add${s}${p} $Rdn, $imm",
+      (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+
+def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
+      (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+
+def : t2InstAlias<"add${p} $Rdn, $imm",
+           (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;
+
+def : t2InstAlias<"addw${p} $Rdn, $imm",
+           (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;
+
+// add w/ negative immediates is just a sub.
+def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
+        (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
+                 cc_out:$s)>;
+def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
+           (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+def : t2InstSubst<"add${s}${p} $Rdn, $imm",
+      (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p,
+               cc_out:$s)>;
+def : t2InstSubst<"add${p} $Rdn, $imm",
+           (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
+
+def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
+        (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
+                 cc_out:$s)>;
+def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
+           (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
+def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
+      (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p,
+               cc_out:$s)>;
+def : t2InstSubst<"addw${p} $Rdn, $imm",
+           (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
+
+
+// Aliases for SUB without the ".w" optional width specifier.
+def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
+        (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
+           (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
+// ... and with the destination and source register combined.
+def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
+      (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"sub${s}${p}.w $Rdn, $imm",
+      (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"sub${p} $Rdn, $imm",
+           (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;
+def : t2InstAlias<"subw${p} $Rdn, $imm",
+           (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;
+
 // Alias for compares without the ".w" optional width specifier.
 def : t2InstAlias<"cmn${p} $Rn, $Rm",
                   (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
 def : t2InstAlias<"teq${p} $Rn, $Rm",
                   (t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
 def : t2InstAlias<"tst${p} $Rn, $Rm",
                   (t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
 

 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",
                   (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"orr${s}${p} $Rdn, $imm",
                   (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
                            pred:$p, cc_out:$s)>;
 // Likewise, "add Rd, t2_so_imm_neg" -> sub
 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
-                  (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
+                  (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
+def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
+                  (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm,
+                           pred:$p, cc_out:$s)>;
+def : t2InstSubst<"add${s}${p} $Rd, $imm",
+                  (t2SUBri rGPR:$Rd, rGPR:$Rd, t2_so_imm_neg:$imm,
                            pred:$p, cc_out:$s)>;
 def : t2InstSubst<"add${s}${p} $Rd, $imm",
-                  (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
+                  (t2SUBspImm GPRsp:$Rd, GPRsp:$Rd, t2_so_imm_neg:$imm,
                            pred:$p, cc_out:$s)>;
 // Same for CMP <--> CMN via t2_so_imm_neg
 def : t2InstSubst<"cmp${p} $Rd, $imm",
                   (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
 def : t2InstSubst<"cmn${p} $Rd, $imm",
                   (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
 
 

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

if (isi32Load(Opcode)) {
         for (const std::pair<unsigned, bool> &R : Regs)
           LiveRegs.addReg(R.first);
 
       NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);
       if (NewBase == 0)
         return nullptr;
     }
 
-    int BaseOpc =
-      isThumb2 ? ARM::t2ADDri :
-      (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi :
-      (isThumb1 && Offset < 8) ? ARM::tADDi3 :
-      isThumb1 ? ARM::tADDi8  : ARM::ADDri;
+    int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
+                                                          : ARM::t2ADDri)
+                           : (isThumb1 && Base == ARM::SP)
+                                 ? ARM::tADDrSPi
+                                 : (isThumb1 && Offset < 8)
+                                       ? ARM::tADDi3
+                                       : isThumb1 ? ARM::tADDi8 : ARM::ADDri;
 
     if (Offset < 0) {
-      Offset = - Offset;
-      BaseOpc =
-        isThumb2 ? ARM::t2SUBri :
-        (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 :
-        isThumb1 ? ARM::tSUBi8  : ARM::SUBri;
+      // FIXME: There are no Thumb1 load/store instructions with negative
+      // offsets. So the Base != ARM::SP might be unnecessary.
+      Offset = -Offset;
+      BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
+                                                        : ARM::t2SUBri)
+                         : (isThumb1 && Offset < 8 && Base != ARM::SP)
+                               ? ARM::tSUBi3
+                               : isThumb1 ? ARM::tSUBi8 : ARM::SUBri;
     }
 
     if (!TL->isLegalAddImmediate(Offset))
       // FIXME: Try add with register operand?
       return nullptr; // Probably not worth it then.
 
     // We can only append a kill flag to the add/sub input if the value is not
     // used in the register list of the stm as well.

 static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg,
                                   ARMCC::CondCodes Pred, unsigned PredReg) {
   bool CheckCPSRDef;
   int Scale;
   switch (MI.getOpcode()) {
   case ARM::tADDi8:  Scale =  4; CheckCPSRDef = true; break;
   case ARM::tSUBi8:  Scale = -4; CheckCPSRDef = true; break;
   case ARM::t2SUBri:
+  case ARM::t2SUBspImm:
   case ARM::SUBri:   Scale = -1; CheckCPSRDef = true; break;
   case ARM::t2ADDri:
+  case ARM::t2ADDspImm:
   case ARM::ADDri:   Scale =  1; CheckCPSRDef = true; break;
   case ARM::tADDspi: Scale =  4; CheckCPSRDef = false; break;
   case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break;
   default: return 0;
   }
 
   unsigned MIPredReg;
   if (MI.getOperand(0).getReg() != Reg ||

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
     if (inITBlock() &&
         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
       return false;
     // Check against T3. If the second register is the PC, this is an
     // alternate form of ADR, which uses encoding T4, so check for that too.
     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
-        static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
+        (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() ||
+         static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg()))
       return false;
 
     // Otherwise, we use encoding T4, which does not have a cc_out
     // operand.
     return true;
   }
 
   // The thumb2 multiply instruction doesn't have a CCOut register, so
bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
   // anyway.
   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
       (Operands.size() == 5 || Operands.size() == 6) &&
       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
        (Operands.size() == 6 &&
-        static_cast<ARMOperand &>(*Operands[5]).isImm())))
-    return true;
-
+        static_cast<ARMOperand &>(*Operands[5]).isImm()))) {
+    // Thumb2 (add|sub){s}{p}.w GPRnopc, sp, #{T2SOImm} has cc_out
+    return (!(isThumbTwo() &&
+              (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() ||
+               static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg())));
+  }
+  // Fixme: Should join all the thumb+thumb2 (add|sub) in a single if case
+  // Thumb2 ADD r0, #4095 -> ADDW r0, r0, #4095 (T4)
+  // Thumb2 SUB r0, #4095 -> SUBW r0, r0, #4095
+  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
+      (Operands.size() == 5) &&
+      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
+      static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP &&
+      static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC &&
+      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
+      static_cast<ARMOperand &>(*Operands[4]).isImm()) {
+    const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]);
+    if (IMM.isT2SOImm() || IMM.isT2SOImmNeg())
+      return false; // add.w / sub.w
+    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) {
+      const int64_t Value = CE->getValue();
+      // Thumb1 imm8 sub / add
+      if ((Value < ((1 << 7) - 1) << 2) && inITBlock() && (!(Value & 3)) &&
+          isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()))
+        return false;
+      return true; // Thumb2 T4 addw / subw
+    }
+  }
   return false;
 }
 
 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
                                               OperandVector &Operands) {
   // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
   unsigned RegIdx = 3;
   if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
case ARM::tADDrSP:
     // same, we need thumb2 (for the wide encoding), or we have an error.
     if (!isThumbTwo() &&
         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
       return Error(Operands[4]->getStartLoc(),
                    "source register must be the same as destination");
     }
     break;
 
-  case ARM::t2ADDri:
-  case ARM::t2ADDri12:
   case ARM::t2ADDrr:
   case ARM::t2ADDrs:
-  case ARM::t2SUBri:
-  case ARM::t2SUBri12:
   case ARM::t2SUBrr:
   case ARM::t2SUBrs:
     if (Inst.getOperand(0).getReg() == ARM::SP &&
         Inst.getOperand(1).getReg() != ARM::SP)
       return Error(Operands[4]->getStartLoc(),
                    "source register must be sp if destination is sp");
     break;
 
   // Final range checking for Thumb unconditional branch instructions.
   case ARM::tB:
     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
       return Error(Operands[2]->getStartLoc(), "branch target out of range");
     break;
   case ARM::t2B: {
     int op = (Operands[2]->isImm()) ? 2 : 3;
     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
       return Error(Operands[op]->getStartLoc(), "branch target out of range");
     break;
   }
   // Final range checking for Thumb conditional branch instructions.
   case ARM::tBcc:
if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
       TmpInst.addOperand(MCOperand::createImm(-4));
       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
       TmpInst.addOperand(Inst.getOperand(3));
       Inst = TmpInst;
     }
     break;
   case ARM::t2ADDri12:
-    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
-    // mnemonic was used (not "addw"), encoding T3 is preferred.
-    if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
+  case ARM::t2SUBri12:
+  case ARM::t2ADDspImm12:
+  case ARM::t2SUBspImm12: {
+    // If the immediate fits for encoding T3 and the generic
+    // mnemonic was used, encoding T3 is preferred.
+    const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
+    if ((Token != "add" && Token != "sub") ||
         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
       break;
+    switch (Inst.getOpcode()) {
+    case ARM::t2ADDri12:
       Inst.setOpcode(ARM::t2ADDri);
-    Inst.addOperand(MCOperand::createReg(0)); // cc_out
       break;
     case ARM::t2SUBri12:
-    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
-    // mnemonic was used (not "subw"), encoding T3 is preferred.
-    if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
-        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
-      break;
       Inst.setOpcode(ARM::t2SUBri);
-    Inst.addOperand(MCOperand::createReg(0)); // cc_out
       break;
+    case ARM::t2ADDspImm12:
+      Inst.setOpcode(ARM::t2ADDspImm);
+      break;
+    case ARM::t2SUBspImm12:
+      Inst.setOpcode(ARM::t2SUBspImm);
+      break;
+    }
+
+    Inst.addOperand(MCOperand::createReg(0)); // cc_out
+    return true;
+  }
   case ARM::tADDi8:
     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
     // to encoding T1 if <Rd> is omitted."
     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
       Inst.setOpcode(ARM::tADDi3);
       return true;
     }
     break;
   case ARM::tSUBi8:
     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
     // to encoding T1 if <Rd> is omitted."
     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
case ARM::t2SUBri: {
     TmpInst.addOperand(Inst.getOperand(5));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(Inst.getOperand(3));
     TmpInst.addOperand(Inst.getOperand(4));
     Inst = TmpInst;
     return true;
   }
+  case ARM::t2ADDspImm:
+  case ARM::t2SUBspImm: {
+    // Prefer T1 encoding if possible
+    if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
+      break;
+    unsigned V = Inst.getOperand(2).getImm();
+    if (V & 3 || V > ((1 << 7) - 1) << 2)
+      break;
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi
+                                                          : ARM::tSUBspi);
+    TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg
+    TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg
+    TmpInst.addOperand(MCOperand::createImm(V / 4));   // immediate
+    TmpInst.addOperand(Inst.getOperand(3));            // pred
+    TmpInst.addOperand(Inst.getOperand(4));
+    Inst = TmpInst;
+    return true;
+  }
   case ARM::t2ADDrr: {
     // If the destination and first source operand are the same, and
     // there's no setting of the flags, use encoding T2 instead of T3.
     // Note that this is only for ADD, not SUB. This mirrors the system
     // 'as' behaviour.  Also take advantage of ADD being commutative.
     // Make sure the wide encoding wasn't explicit.
     bool Swap = false;
     auto DestReg = Inst.getOperand(0).getReg();

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder);
 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
                                                   uint64_t Address,
                                                   const void *Decoder);
+static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
+                                        uint64_t Address, const void *Decoder);
+
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
   return new ARMDisassembler(STI, Ctx);
 }
 
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
   if ((RegNo & 1) || RegNo == 0xe)
      S = MCDisassembler::SoftFail;
 
   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
   Inst.addOperand(MCOperand::createReg(RegisterPair));
   return S;
 }
 
+static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+  if (RegNo != 13)
+    return MCDisassembler::Fail;
+
+  unsigned Register = GPRDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   unsigned Register = 0;
   switch (RegNo) {
     case 0:
       Register = ARM::R0;
       break;
     case 1:
DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
   return S;
 }
 
 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
                                 uint64_t Address, const void *Decoder) {
   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
   if (sign1 != sign2) return MCDisassembler::Fail;
+  const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
+  assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
+  DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
 
   unsigned Val = fieldFromInstruction(Insn, 0, 8);
   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
-  Val |= sign1 << 12;
-  Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
-
-  return MCDisassembler::Success;
+  // If sign, then it is decreasing the address.
+  if (sign1) {
+    // Following ARMv7 Architecture Manual, when the offset
+    // is zero, it is decoded as a subw, not as a adr.w
+    if (!Val) {
+      Inst.setOpcode(ARM::t2SUBri12);
+      Inst.addOperand(MCOperand::createReg(ARM::PC));
+    } else
+      Val = -Val;
+  }
+  Inst.addOperand(MCOperand::createImm(Val));
+  return S;
 }
 
 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
                                               uint64_t Address,
                                               const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   // Shift of "asr #32" is not allowed in Thumb2 mode.

 
 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
                                    const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   Inst.addOperand(MCOperand::createReg(ARM::VPR));
   return S;
 }
+
+static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
+                                        uint64_t Address, const void *Decoder) {
+  const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
+  const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
+                         fieldFromInstruction(Insn, 12, 3) << 8 |
+                         fieldFromInstruction(Insn, 0, 8);
+  const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
+  unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
+  unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
+  unsigned S = fieldFromInstruction(Insn, 20, 1);
+  if (sign1 != sign2)
+    return MCDisassembler::Fail;
+
+  // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
+  DecodeStatus DS = MCDisassembler::Success;
+  if ((!Check(DS,
+              DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
+      (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
+    return MCDisassembler::Fail;
+  if (TypeT3) {
+    Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
+    S = 0;
+    Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
+  } else {
+    Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
+    if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
+      return MCDisassembler::Fail;
+  }
+  if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createReg(0)); // pred
+
+  return DS;
+}

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
           .addReg(BaseReg)
           .addImm(ThisVal / 4)
           .setMIFlags(MIFlags)
           .add(predOps(ARMCC::AL));
       break;
     }
     bool HasCCOut = true;
     int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal);
-
-    Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
+    bool ToSP = DestReg == ARM::SP;
+    unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
+    unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
+    unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
+    unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
+    Opc = isSub ? t2SUB : t2ADD;
     // Prefer T2: sub rd, rn, so_imm | sub sp, sp, so_imm
     if (ImmIsT2SO != -1) {
       NumBytes = 0;
     } else if (ThisVal < 4096) {
       // Prefer T3 if can make it in a single go: subw rd, rn, imm12 | subw sp,
       // sp, imm12
-      Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
+      Opc = isSub ? t2SUBi12 : t2ADDi12;
       HasCCOut = false;
       NumBytes = 0;
     } else {
       // Use one T2 instruction to reduce NumBytes
       // FIXME: Move this to ARMAddressingModes.h?
       unsigned RotAmt = countLeadingZeros(ThisVal);
       ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
       NumBytes &= ~ThisVal;
bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
   MachineFunction &MF = *MI.getParent()->getParent();
   const TargetRegisterClass *RegClass =
       TII.getRegClass(Desc, FrameRegIdx, TRI, MF);
 
   // Memory operands in inline assembly always use AddrModeT2_i12.
   if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
     AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
 
-  if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
+  const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
+  if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
     Offset += MI.getOperand(FrameRegIdx+1).getImm();
 
     unsigned PredReg;
     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
         !MI.definesRegister(ARM::CPSR)) {
       // Turn it into a move.
       MI.setDesc(TII.get(ARM::tMOVr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       // Remove offset and remaining explicit predicate operands.
       do MI.RemoveOperand(FrameRegIdx+1);
       while (MI.getNumOperands() > FrameRegIdx+1);
       MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
       MIB.add(predOps(ARMCC::AL));
       return true;
     }
 
-    bool HasCCOut = Opcode != ARM::t2ADDri12;
+    bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
 
     if (Offset < 0) {
       Offset = -Offset;
       isSub = true;
-      MI.setDesc(TII.get(ARM::t2SUBri));
+      MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));
     } else {
-      MI.setDesc(TII.get(ARM::t2ADDri));
+      MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));
     }
 
     // Common case: small offset, fits into instruction.
     if (ARM_AM::getT2SOImmVal(Offset) != -1) {
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
       // Add cc_out operand if the original instruction did not have one.
       if (!HasCCOut)
         MI.addOperand(MachineOperand::CreateReg(0, false));
       Offset = 0;
       return true;
     }
     // Another common case: imm12.
     if (Offset < 4096 &&
         (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
-      unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
+      unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
+                              : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
       MI.setDesc(TII.get(NewOpc));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
       // Remove the cc_out operand.
       if (HasCCOut)
         MI.RemoveOperand(MI.getNumOperands()-1);
       Offset = 0;
       return true;

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir

body:             |
   bb.0:
     liveins: $r0
 
     %0(s32) = COPY $r0
     ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
 
     %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg
 
     $r0 = COPY %2(s32)
     ; CHECK: $r0 = COPY [[VREGRES]]
 
     BX_RET 14, $noreg, implicit $r0
     ; CHECK: BX_RET 14, $noreg, implicit $r0
 ...
 ---
body:             |
   bb.0:
     liveins: $r0
 
     %0(s32) = COPY $r0
     ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
 
     %1(s32) = G_CONSTANT i32 4093
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri12 [[VREGX]], 4093, 14, $noreg
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri12 [[VREGX]], 4093, 14, $noreg
 
     $r0 = COPY %2(s32)
     ; CHECK: $r0 = COPY [[VREGRES]]
 
     BX_RET 14, $noreg, implicit $r0
     ; CHECK: BX_RET 14, $noreg, implicit $r0
 ...
 ---
body:             |
   bb.0:
     liveins: $r0
 
     %0(s32) = COPY $r0
     ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
 
     %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
     %2(s32) = G_SUB %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg
 
     $r0 = COPY %2(s32)
     ; CHECK: $r0 = COPY [[VREGRES]]
 
     BX_RET 14, $noreg, implicit $r0
     ; CHECK: BX_RET 14, $noreg, implicit $r0
 ...
 ---

llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir

fixedStack:
   - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 # CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
 # CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
 body:             |
   bb.0:
     liveins: $r0, $r1, $r2, $r3
 
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
-    ; CHECK: [[FI32VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
+    ; CHECK: [[FI32VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
     ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg
 
     $r0 = COPY %1
     ; CHECK: $r0 = COPY [[LD32VREG]]
 
     %2(p0) = G_FRAME_INDEX %fixed-stack.0
-    ; CHECK: [[FI1VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
+    ; CHECK: [[FI1VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
 
     %3(s1) = G_LOAD %2(p0) :: (load 1)
     ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg
 
     %4(s32) = G_ANYEXT %3(s1)
     ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
 
     $r0 = COPY %4
     ; CHECK: $r0 = COPY [[RES]]
 
     BX_RET 14, $noreg
     ; CHECK: BX_RET 14, $noreg
 ...

llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir

 --- |
   ; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s
   ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
-  ; CHECK-NEXT: $sp = frame-setup t2SUBri12 killed $sp, 4008, 14, $noreg
+  ; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 4008, 14, $noreg
 
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv7-none-none-eabi"
   define void @foo() #0 {
   entry:
     %v = alloca [4000 x i8], align 1
     %s = alloca i8*, align 4
     %0 = bitcast [4000 x i8]* %v to i8*

llvm/test/CodeGen/Thumb2/bug-subw.ll

+; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
+; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
+; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
+; CHECK:     .fnend
+; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32"
+target triple = "thumbv7m-unknown-unknown"
+%B = type {%B*}
+%R = type {i32}
+%U = type {%U*, i8, i8}
+%E = type {%B*, %U*}
+%X = type {i32, i8, i8}
+declare external [0 x i8]* @memalloc(i32, i32, i32)
+declare external void @memfree([0 x i8]*, i32, i32)
+define void @foo(%B* %pb$, %R* %pr$) nounwind {
+L.0:
+  %pb = alloca %B*
+  %pr = alloca %R*
+  store %B* %pb$, %B** %pb
+  store %R* %pr$, %R** %pr
+  %pe = alloca %E*
+  %0 = load %B*, %B** %pb
+  %1 = bitcast %B* %0 to %E*
+  store %E* %1, %E** %pe
+  %2 = load %R*, %R** %pr
+  %3 = getelementptr %R, %R* %2, i32 0, i32 0
+  %4 = load i32, i32* %3
+  switch i32 %4, label %L.1 [
+    i32 1, label %L.3
+  ]
+L.3:
+  %px = alloca %X*
+  %5 = load %R*, %R** %pr
+  %6 = bitcast %R* %5 to %X*
+  store %X* %6, %X** %px
+  %7 = load %X*, %X** %px
+  %8 = getelementptr %X, %X* %7, i32 0, i32 0
+  %9 = load i32, i32* %8
+  %10 = icmp ne i32 %9, 0
+  br i1 %10, label %L.5, label %L.4
+L.5:
+  %pu = alloca %U*
+  %11 = call [0 x i8]* @memalloc(i32 8, i32 4, i32 0)
+  %12 = bitcast [0 x i8]* %11 to %U*
+  store %U* %12, %U** %pu
+  %13 = load %X*, %X** %px
+  %14 = getelementptr %X, %X* %13, i32 0, i32 1
+  %15 = load i8, i8* %14
+  %16 = load %U*, %U** %pu
+  %17 = getelementptr %U, %U* %16, i32 0, i32 1
+  store i8 %15, i8* %17
+  %18 = load %E*, %E** %pe
+  %19 = getelementptr %E, %E* %18, i32 0, i32 1
+  %20 = load %U*, %U** %19
+  %21 = load %U*, %U** %pu
+  %22 = getelementptr %U, %U* %21, i32 0, i32 0
+  store %U* %20, %U** %22
+  %23 = load %U*, %U** %pu
+  %24 = load %E*, %E** %pe
+  %25 = getelementptr %E, %E* %24, i32 0, i32 1
+  store %U* %23, %U** %25
+  br label %L.4
+L.4:
+  %26 = load %X*, %X** %px
+  %27 = bitcast %X* %26 to [0 x i8]*
+  call void @memfree([0 x i8]* %27, i32 8, i32 0)
+  br label %L.2
+L.1:
+  br label %L.2
+L.2:
+  br label %return
+return:
+  ret void
+}

llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir

bb.0:
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
     ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
-    ; CHECK: $sp = frame-setup t2SUBri killed $sp, 1208, 14, $noreg, $noreg
+    ; CHECK: $sp = frame-setup t2SUBspImm killed $sp, 1208, 14, $noreg, $noreg
     ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1244
     ; CHECK: $r0 = IMPLICIT_DEF
     ; CHECK: $r1 = IMPLICIT_DEF
     ; CHECK: $r2 = IMPLICIT_DEF
     ; CHECK: $r3 = IMPLICIT_DEF
     ; CHECK: $r4 = IMPLICIT_DEF
     ; CHECK: $r5 = IMPLICIT_DEF
     ; CHECK: $r6 = IMPLICIT_DEF

llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
       debug-info-location: '' }
   - { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
       debug-info-location: '' }
 body: |
   bb.0:
     ; CHECK-LABEL: name: func1
     ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
     ; CHECK-NEXT: {{  }}
     ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36
-    ; CHECK-NEXT: $sp = frame-setup t2SUBri12 killed $sp, 1220, 14, $noreg
+    ; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg
     ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
     ; CHECK-NEXT: $r0 = IMPLICIT_DEF
     ; CHECK-NEXT: $r1 = IMPLICIT_DEF
     ; CHECK-NEXT: $r2 = IMPLICIT_DEF
     ; CHECK-NEXT: $r3 = IMPLICIT_DEF
     ; CHECK-NEXT: $r4 = IMPLICIT_DEF
     ; CHECK-NEXT: $r5 = IMPLICIT_DEF
     ; CHECK-NEXT: $r6 = IMPLICIT_DEF

llvm/test/CodeGen/Thumb2/peephole-addsub.mir

 body:             |
   bb.0 (%ir-block.0):
     liveins: $r0, $r1
 
     %1:rgpr = COPY $r1
     %0:rgpr = COPY $r0
     %2:rgpr = t2MOVi 1, 14, $noreg, $noreg
     %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
-    %4:gprnopc = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
+    %4:rgpr = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
     t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr
     %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
     $r0 = COPY %5
     tBX_RET 14, $noreg, implicit $r0
 
 # CHECK-LABEL: name: test
 # CHECK:      %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
-# CHECK-NEXT: %4:gprnopc = t2SUBri %3, 0, 14, $noreg, def $cpsr
+# CHECK-NEXT: %4:rgpr = t2SUBri %3, 0, 14, $noreg, def $cpsr
 # CHECK-NEXT: %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
 ...

llvm/test/CodeGen/Thumb2/peephole-cmp.mir

- { id: 0, name: f, type: default, offset: 0, size: 1, alignment: 4,
       local-offset: -4, debug-info-variable: '', debug-info-expression: '',
       debug-info-location: '' }
 body:             |
   bb.0:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0
 
     %0:rgpr = COPY $r0
-    %1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
+    %1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
     t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
     t2Bcc %bb.2, 3, $cpsr
     t2B %bb.1, 14, $noreg
 
   bb.1:
     $r0 = COPY %1
     tBX_RET 14, $noreg
 
   bb.2:
     $r0 = COPY %0
     tBX_RET 14, $noreg
 
 # CHECK-LABEL: name: test_addir_frameindex
-# CHECK:      %1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
+# CHECK:      %1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
 # CHECK-NEXT: t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
 # CHECK-NEXT: t2Bcc %bb.2, 3, $cpsr
 ...

llvm/test/CodeGen/Thumb2/t2peephole-t2ADDrr-to-t2ADDri.ll

+; RUN: llc -mtriple=thumb-eabi --stop-after=peephole-opt -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
+define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
+; CHECK: [[R0:%0|%[1-9][0-9]*]]:gprnopc = COPY $r0
+; CHECK-NEXT: [[R1:%0|%[1-9][0-9]*]]:rgpr = t2ADDri [[R0]], 11206656
+; CHECK-NEXT: [[R2:%0|%[1-9][0-9]*]]:rgpr = t2ADDri killed [[R1]], 187
+; CHECK-NEXT: $r0 = COPY [[R2]]
+  %ret = add i32 %lhs, 11206843 ; 0x00ab00bb
+  ret i32 %ret
+}
+

llvm/test/MC/ARM/basic-thumb2-instructions.s

@------------------------------------------------------------------------------
         add r12, r6, #0x100
         addw r12, r6, #0x100
         adds r1, r2, #0x1f0
   add r2, #1
         add r0, r0, #32
         adds r2, r2, #56
         adds r2, #56
         add r1, r7, #0xcbcbcbcb
-        add sp, sp, #0x1fe0000
 
         adds.w r2, #-16
         adds.w r2, r2, #-16
         addw r2, #-16
         addw r2, #-16
         addw r2, r2, #-16
 
 @ CHECK: itet  eq                      @ encoding: [0x0a,0xbf]
 @ CHECK: addeq  r1, r2, #4              @ encoding: [0x11,0x1d]
 @ CHECK: addwne  r5, r3, #1023           @ encoding: [0x03,0xf2,0xff,0x35]
 @ CHECK: addweq  r4, r5, #293            @ encoding: [0x05,0xf2,0x25,0x14]
 @ CHECK: add.w  r2, sp, #1024           @ encoding: [0x0d,0xf5,0x80,0x62]
 @ CHECK: add.w  r2, r8, #65280          @ encoding: [0x08,0xf5,0x7f,0x42]
 @ CHECK: addw  r2, r3, #257            @ encoding: [0x03,0xf2,0x01,0x12]
 @ CHECK: addw  r2, r3, #257            @ encoding: [0x03,0xf2,0x01,0x12]
 @ CHECK: add.w  r12, r6, #256           @ encoding: [0x06,0xf5,0x80,0x7c]
 @ CHECK: addw  r12, r6, #256           @ encoding: [0x06,0xf2,0x00,0x1c]
 @ CHECK: adds.w  r1, r2, #496            @ encoding: [0x12,0xf5,0xf8,0x71]
 @ CHECK: add.w  r2, r2, #1              @ encoding: [0x02,0xf1,0x01,0x02]
 @ CHECK: add.w  r0, r0, #32             @ encoding: [0x00,0xf1,0x20,0x00]
 @ CHECK: adds  r2, #56                 @ encoding: [0x38,0x32]
 @ CHECK: adds  r2, #56                 @ encoding: [0x38,0x32]
 @ CHECK: add.w  r1, r7, #3419130827     @ encoding: [0x07,0xf1,0xcb,0x31]
-@ CHECK: add.w  sp, sp, #33423360       @ encoding: [0x0d,0xf1,0xff,0x7d]
 
 @ CHECK: subs.w  r2, r2, #16             @ encoding: [0xb2,0xf1,0x10,0x02]
 @ CHECK: subs.w  r2, r2, #16             @ encoding: [0xb2,0xf1,0x10,0x02]
 @ CHECK: subw  r2, r2, #16             @ encoding: [0xa2,0xf2,0x10,0x02]
 @ CHECK: subw  r2, r2, #16             @ encoding: [0xa2,0xf2,0x10,0x02]
 @ CHECK: subw  r2, r2, #16             @ encoding: [0xa2,0xf2,0x10,0x02]
 
 

 @ CHECK: adds.w  r7, sp, #16             @ encoding: [0x1d,0xf1,0x10,0x07]
         add r8, sp, #16              // T3
 @ CHECK: add.w  r8, sp, #16             @ encoding: [0x0d,0xf1,0x10,0x08]
 
         addw r6, sp, #1020           // T4
 @ CHECK: addw  r6, sp, #1020           @ encoding: [0x0d,0xf2,0xfc,0x36]
         add r6, sp, #1019            // T4
 @ CHECK: addw  r6, sp, #1019           @ encoding: [0x0d,0xf2,0xfb,0x36]
-
+        addw    r0, r0, #4095
+        addw    r0, #4095
+        add     r0, r0, #4095
+        add     r0, #4095
+@ CHECK-NEXT: addw    r0, r0, #4095           @ encoding: [0x00,0xf6,0xff,0x70]
+@ CHECK-NEXT: addw    r0, r0, #4095           @ encoding: [0x00,0xf6,0xff,0x70]
+@ CHECK-NEXT: addw    r0, r0, #4095           @ encoding: [0x00,0xf6,0xff,0x70]
+@ CHECK-NEXT: addw    r0, r0, #4095           @ encoding: [0x00,0xf6,0xff,0x70]
+add.w r0, r0, #-4096
+add r0, r0, #-4096
+add.w r0, #-4096
+add r0, #-4096
+@ CHECK-NEXT: sub.w   r0, r0, #4096           @ encoding: [0xa0,0xf5,0x80,0x50]
+@ CHECK-NEXT: sub.w   r0, r0, #4096           @ encoding: [0xa0,0xf5,0x80,0x50]
+@ CHECK-NEXT: sub.w   r0, r0, #4096           @ encoding: [0xa0,0xf5,0x80,0x50]
+@ CHECK-NEXT: sub.w   r0, r0, #4096           @ encoding: [0xa0,0xf5,0x80,0x50]
+adds.w r0, r0, #-4096
+adds r0, r0, #-4096
+adds.w r0, #-4096
+adds r0, #-4096
+@ CHECK-NEXT: subs.w   r0, r0, #4096           @ encoding: [0xb0,0xf5,0x80,0x50]
+@ CHECK-NEXT: subs.w   r0, r0, #4096           @ encoding: [0xb0,0xf5,0x80,0x50]
+@ CHECK-NEXT: subs.w   r0, r0, #4096           @ encoding: [0xb0,0xf5,0x80,0x50]
+@ CHECK-NEXT: subs.w   r0, r0, #4096           @ encoding: [0xb0,0xf5,0x80,0x50]
+@------------------------------------------------------------------------------
+@ ADD (SP plus immediate, writing to SP)
+@------------------------------------------------------------------------------
+        add.w sp, sp, #0x1fe0000 //T3
+        add.w sp, #0x1fe0000
+        add sp, sp, #0x1fe0000
+        add sp, #0x1fe0000
+@ CHECK-NEXT: add.w  sp, sp, #33423360       @ encoding: [0x0d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: add.w  sp, sp, #33423360       @ encoding: [0x0d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: add.w  sp, sp, #33423360       @ encoding: [0x0d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: add.w  sp, sp, #33423360       @ encoding: [0x0d,0xf1,0xff,0x7d]
+        adds.w sp, sp, #0x1fe0000 //T3
+        adds.w sp, #0x1fe0000
+        adds sp, sp, #0x1fe0000
+        adds sp, #0x1fe0000
+@ CHECK-NEXT: adds.w  sp, sp, #33423360       @ encoding: [0x1d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: adds.w  sp, sp, #33423360       @ encoding: [0x1d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: adds.w  sp, sp, #33423360       @ encoding: [0x1d,0xf1,0xff,0x7d]
+@ CHECK-NEXT: adds.w  sp, sp, #33423360       @ encoding: [0x1d,0xf1,0xff,0x7d]
+        addw sp, sp, #4095 //T4
+        add  sp, sp, #4095
+        addw sp, #4095
+        add sp, #4095
+@ CHECK-NEXT:        addw    sp, sp, #4095           @ encoding: [0x0d,0xf6,0xff,0x7d]
+@ CHECK-NEXT:        addw    sp, sp, #4095           @ encoding: [0x0d,0xf6,0xff,0x7d]
+@ CHECK-NEXT:        addw    sp, sp, #4095           @ encoding: [0x0d,0xf6,0xff,0x7d]
+@ CHECK-NEXT:        addw    sp, sp, #4095           @ encoding: [0x0d,0xf6,0xff,0x7d]
+        add     sp, sp, #128 //T2
+        add     sp, #128
+@ CHECK-NEXT: add     sp, #128                @ encoding: [0x20,0xb0]
+@ CHECK-NEXT: add     sp, #128                @ encoding: [0x20,0xb0]
+        adds     sp, sp, #128 //T3
+        adds     sp, #128
+@ CHECK-NEXT: adds.w  sp, sp, #128            @ encoding: [0x1d,0xf1,0x80,0x0d]
+@ CHECK-NEXT: adds.w  sp, sp, #128            @ encoding: [0x1d,0xf1,0x80,0x0d]
+        add     r0, sp, #128 //T1
+@ CHECK-NEXT: add     r0, sp, #128            @ encoding: [0x20,0xa8]
+        adds     r0, sp, #128 //T3
+@ CHECK-NEXT: adds.w  r0, sp, #128            @ encoding: [0x1d,0xf1,0x80,0x00]
+        addw r0, sp, #128
+@ CHECK-NEXT: addw    r0, sp, #128            @ encoding: [0x0d,0xf2,0x80,0x00]
+@------------------------------------------------------------------------------
+@ ADD (SP plus negative immediate, writing to SP)
+@------------------------------------------------------------------------------
+add sp, sp, #-508
+add sp, #-508
+@ CHECK-NEXT: sub     sp, #508                @ encoding: [0xff,0xb0]
+@ CHECK-NEXT: sub     sp, #508                @ encoding: [0xff,0xb0]
+addw sp, sp, #-4095
+add sp, sp, #-4095
+addw sp, #-4095
+add sp, #-4095
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+add.w sp, sp, #-4096
+add sp, sp, #-4096
+add.w sp, #-4096
+add sp, #-4096
+@ CHECK-NEXT: sub.w   sp, sp, #4096           @ encoding: [0xad,0xf5,0x80,0x5d]
+@ CHECK-NEXT: sub.w   sp, sp, #4096           @ encoding: [0xad,0xf5,0x80,0x5d]
+@ CHECK-NEXT: sub.w   sp, sp, #4096           @ encoding: [0xad,0xf5,0x80,0x5d]
+@ CHECK-NEXT: sub.w   sp, sp, #4096           @ encoding: [0xad,0xf5,0x80,0x5d]
+adds.w sp, sp, #-4096
+adds sp, sp, #-4096
+adds.w sp, #-4096
+adds sp, #-4096
+@ CHECK-NEXT: subs.w  sp, sp, #4096           @ encoding: [0xbd,0xf5,0x80,0x5d]
+@ CHECK-NEXT: subs.w  sp, sp, #4096           @ encoding: [0xbd,0xf5,0x80,0x5d]
+@ CHECK-NEXT: subs.w  sp, sp, #4096           @ encoding: [0xbd,0xf5,0x80,0x5d]
+@ CHECK-NEXT: subs.w  sp, sp, #4096           @ encoding: [0xbd,0xf5,0x80,0x5d]
 @------------------------------------------------------------------------------
 @ ADD (SP plus register) A8.8.10
 @------------------------------------------------------------------------------
         it eq
 @ CHECK: it eq                          @ encoding: [0x08,0xbf]
         addeq r8, sp, r8             // T1
 @ CHECK: addeq  r8, sp, r8              @ encoding: [0xe8,0x44]
         it eq
 @ CHECK: it eq                          @ encoding: [0x08,0xbf]
         addeq r8, sp                 // T1
 @ CHECK: addeq  r8, sp                  @ encoding: [0xe8,0x44]
 
         it eq
 @ CHECK: it eq                          @ encoding: [0x08,0xbf]
         addeq sp, r9                 // T2
 @ CHECK: addeq  sp, r9                  @ encoding: [0xcd,0x44]
 
         add r2, sp, ip               // T3
 @ CHECK: add.w r2, sp, r12              @ encoding: [0x0d,0xeb,0x0c,0x02]
         it eq
 @ CHECK: it eq                          @ encoding: [0x08,0xbf]
         addeq r2, sp, ip             // T3
 @ CHECK: addeq.w r2, sp, r12            @ encoding: [0x0d,0xeb,0x0c,0x02]
-
-
+         add.w r0, sp, r0, ror #2
+         add r0, sp, r0, ror #2
+         add sp, r1, lsl #15
+         adds.w r0, sp, r0, ror #2
+         adds r0, sp, r0, ror #2
+         adds.w sp, sp, r0, ror #31
+         adds sp, sp, r0, ror #31
+         adds sp, r0, ror #31
+@ CHECK-NEXT: add.w   r0, sp, r0, ror #2      @ encoding: [0x0d,0xeb,0xb0,0x00]
+@ CHECK-NEXT: add.w   r0, sp, r0, ror #2      @ encoding: [0x0d,0xeb,0xb0,0x00]
+@ CHECK-NEXT: add.w   sp, sp, r1, lsl #15     @ encoding: [0x0d,0xeb,0xc1,0x3d]
+@ CHECK-NEXT: adds.w  r0, sp, r0, ror #2      @ encoding: [0x1d,0xeb,0xb0,0x00]
+@ CHECK-NEXT: adds.w  r0, sp, r0, ror #2      @ encoding: [0x1d,0xeb,0xb0,0x00]
+@ CHECK-NEXT: adds.w  sp, sp, r0, ror #31     @ encoding: [0x1d,0xeb,0xf0,0x7d]
+@ CHECK-NEXT: adds.w  sp, sp, r0, ror #31     @ encoding: [0x1d,0xeb,0xf0,0x7d]
+@ CHECK-NEXT: adds.w  sp, sp, r0, ror #31     @ encoding: [0x1d,0xeb,0xf0,0x7d]
 @------------------------------------------------------------------------------
 @ FIXME: ADR
 @------------------------------------------------------------------------------
 
         subw r11, pc, #3270
         adr.w r2, #3
         adr.w r11, #-826
         adr.w r1, #-0x0
@------------------------------------------------------------------------------
         subw r2, r3, #257
         sub r12, r6, #0x100
         subw r12, r6, #0x100
         subs r1, r2, #0x1f0
   sub r2, #1
         sub r0, r0, #32
         subs r2, r2, #56
         subs r2, #56
-
+        subw    r0, r0, #4095
+        subw    r0, #4095
+        sub    r0, r0, #4095
+        sub    r0, #4095
 @ CHECK: itet  eq                      @ encoding: [0x0a,0xbf]
 @ CHECK: subeq  r1, r2, #4              @ encoding: [0x11,0x1f]
 @ CHECK: subwne  r5, r3, #1023           @ encoding: [0xa3,0xf2,0xff,0x35]
 @ CHECK: subweq  r4, r5, #293            @ encoding: [0xa5,0xf2,0x25,0x14]
 @ CHECK: sub.w  r2, sp, #1024           @ encoding: [0xad,0xf5,0x80,0x62]
 @ CHECK: sub.w  r2, r8, #65280          @ encoding: [0xa8,0xf5,0x7f,0x42]
 @ CHECK: subw  r2, r3, #257            @ encoding: [0xa3,0xf2,0x01,0x12]
 @ CHECK: subw  r2, r3, #257            @ encoding: [0xa3,0xf2,0x01,0x12]
 @ CHECK: sub.w  r12, r6, #256           @ encoding: [0xa6,0xf5,0x80,0x7c]
 @ CHECK: subw  r12, r6, #256           @ encoding: [0xa6,0xf2,0x00,0x1c]
 @ CHECK: subs.w  r1, r2, #496            @ encoding: [0xb2,0xf5,0xf8,0x71]
 @ CHECK: sub.w  r2, r2, #1              @ encoding: [0xa2,0xf1,0x01,0x02]
 @ CHECK: sub.w  r0, r0, #32             @ encoding: [0xa0,0xf1,0x20,0x00]
 @ CHECK: subs  r2, #56                 @ encoding: [0x38,0x3a]
 @ CHECK: subs  r2, #56                 @ encoding: [0x38,0x3a]
-
-
+@ CHECK-NEXT: subw    r0, r0, #4095           @ encoding: [0xa0,0xf6,0xff,0x70]
+@ CHECK-NEXT: subw    r0, r0, #4095           @ encoding: [0xa0,0xf6,0xff,0x70]
+@ CHECK-NEXT: subw    r0, r0, #4095           @ encoding: [0xa0,0xf6,0xff,0x70]
+@ CHECK-NEXT: subw    r0, r0, #4095           @ encoding: [0xa0,0xf6,0xff,0x70]
+@------------------------------------------------------------------------------
+@ SUB (immediate, writting to SP)
+@------------------------------------------------------------------------------
+        sub.w sp, sp, #0x1fe0000 //T2
+        sub sp, sp, #0x1fe0000
+        sub.w sp, #0x1fe0000
+        sub sp, #0x1fe0000
+@ CHECK-NEXT: sub.w  sp, sp, #33423360       @ encoding: [0xad,0xf1,0xff,0x7d]
+@ CHECK-NEXT: sub.w  sp, sp, #33423360       @ encoding: [0xad,0xf1,0xff,0x7d]
+@ CHECK-NEXT: sub.w  sp, sp, #33423360       @ encoding: [0xad,0xf1,0xff,0x7d]
+@ CHECK-NEXT: sub.w  sp, sp, #33423360       @ encoding: [0xad,0xf1,0xff,0x7d]
+        subs.w sp, sp, #0x1fe0000 //T2
+        subs sp, sp, #0x1fe0000
+        subs.w sp, #0x1fe0000
+        subs sp, #0x1fe0000
+@ CHECK-NEXT: subs.w  sp, sp, #33423360       @ encoding: [0xbd,0xf1,0xff,0x7d]
+@ CHECK-NEXT: subs.w  sp, sp, #33423360       @ encoding: [0xbd,0xf1,0xff,0x7d]
+@ CHECK-NEXT: subs.w  sp, sp, #33423360       @ encoding: [0xbd,0xf1,0xff,0x7d]
+@ CHECK-NEXT: subs.w  sp, sp, #33423360       @ encoding: [0xbd,0xf1,0xff,0x7d]
+        subw sp, sp, #4095 //T3
+        sub sp, sp, #4095
+        subw sp, #4095
+        sub sp, #4095
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+@ CHECK-NEXT: subw    sp, sp, #4095           @ encoding: [0xad,0xf6,0xff,0x7d]
+         sub sp, #128 //T1
+@ CHECK-NEXT: sub     sp, #128                @ encoding: [0xa0,0xb0]
+         subs.w sp, #128 //T2
+         subs sp, #128 //T2
+@ CHECK-NEXT:  subs.w  sp, sp, #128            @ encoding: [0xbd,0xf1,0x80,0x0d]
+@ CHECK-NEXT:  subs.w  sp, sp, #128            @ encoding: [0xbd,0xf1,0x80,0x0d]
+        sub.w sp, #128 //T2
+@ CHECK-NEXT:  sub.w  sp, sp, #128            @ encoding: [0xad,0xf1,0x80,0x0d]
+        subw sp, #128 //T4
+@ CHECK-NEXT: subw    sp, sp, #128            @ encoding: [0xad,0xf2,0x80,0x0d]
 @------------------------------------------------------------------------------
 @ SUB (register)
 @------------------------------------------------------------------------------
         sub r4, r5, r6
         sub r4, r5, r6, lsl #5
         sub r4, r5, r6, lsr #5
         sub.w r4, r5, r6, lsr #5
         sub r4, r5, r6, asr #5

llvm/test/MC/ARM/invalid-addsub.s

-@ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o - 2>&1 | FileCheck %s
-
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
+@ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o /dev/null 2>&1 | FileCheck %s
 add sp, r5, #1
 addw sp, r7, #4
 add sp, r3, r2
 add sp, r3, r5, lsl #3
-
-
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
-@ CHECK: error: source register must be sp if destination is sp
 sub sp, r5, #1
 subw sp, r7, #4
 sub sp, r3, r2
 sub sp, r3, r5, lsl #3
+@CHECK: error: invalid instruction, any one of the following would fix this:
+@CHECK-NEXT: add sp, r5, #1
+@CHECK-NEXT: ^
+@CHECK-NEXT: note: invalid operand for instruction
+@CHECK-NEXT: add sp, r5, #1
+@CHECK-NEXT:             ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: add sp, r5, #1
+@CHECK-NEXT:             ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: add sp, r5, #1
+@CHECK-NEXT:     ^
+@CHECK-NEXT: note: operand must be a register sp
+@CHECK-NEXT: add sp, r5, #1
+@CHECK-NEXT:         ^
+@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
+@CHECK-NEXT: addw sp, r7, #4
+@CHECK-NEXT: ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: addw sp, r7, #4
+@CHECK-NEXT:      ^
+@CHECK-NEXT: note: operand must be a register sp
+@CHECK-NEXT: addw sp, r7, #4
+@CHECK-NEXT:          ^
+@CHECK-NEXT: error: source register must be sp if destination is sp
+@CHECK-NEXT: add sp, r3, r2
+@CHECK-NEXT:         ^
+@CHECK-NEXT: error: source register must be sp if destination is sp
+@CHECK-NEXT: add sp, r3, r5, lsl #3
+@CHECK-NEXT:         ^
+@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
+@CHECK-NEXT: sub sp, r5, #1
+@CHECK-NEXT: ^
+@CHECK-NEXT: note: invalid operand for instruction
+@CHECK-NEXT: sub sp, r5, #1
+@CHECK-NEXT:             ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: sub sp, r5, #1
+@CHECK-NEXT:             ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: sub sp, r5, #1
+@CHECK-NEXT:     ^
+@CHECK-NEXT: note: operand must be a register sp
+@CHECK-NEXT: sub sp, r5, #1
+@CHECK-NEXT:         ^
+@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
+@CHECK-NEXT: subw sp, r7, #4
+@CHECK-NEXT: ^
+@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
+@CHECK-NEXT: subw sp, r7, #4
+@CHECK-NEXT:      ^
+@CHECK-NEXT: note: operand must be a register sp
+@CHECK-NEXT: subw sp, r7, #4
+@CHECK-NEXT:          ^
+@CHECK-NEXT: error: source register must be sp if destination is sp
+@CHECK-NEXT: sub sp, r3, r2
+@CHECK-NEXT:         ^
+@CHECK-NEXT: error: source register must be sp if destination is sp
+@CHECK-NEXT: sub sp, r3, r5, lsl #3

llvm/test/MC/ARM/negative-immediates.s

# CHECK-DISABLED: SBC
   SUB r0, r1, #0xFFFFFF01
 # CHECK: add r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUB
 
 .thumb
 
   ADD r0, r1, #0xFFFFFF00
-# CHECK: subw r0, r1, #256
+# CHECK: sub.w r0, r1, #256
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ADD
   ADDS r0, r1, #0xFFFFFF00
 # CHECK: subs.w r0, r1, #256
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ADDS
   ADDS.W r0, r1, #0xFFFFFF00
 # CHECK: subs.w r0, r1, #256

 # CHECK: addw r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUBW
   SUB.W r0, r1, #0xFFFFFF01
 # CHECK: add.w r0, r1, #255
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUB.W
   SUB r0, r1, #0xFFFFFF00
-# CHECK: addw r0, r1, #256
+# CHECK: add.w r0, r1, #256
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUB
   SUBS r0, r1, #0xFFFFFF00
 # CHECK: adds.w r0, r1, #256
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUBS
   SUBS.W r0, r1, #0xFFFFFF00
 # CHECK: adds.w r0, r1, #256
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: SUBS.W
 
   ADD r0, r1, #-13
-# CHECK: subw r0, r1, #13
+# CHECK: sub.w r0, r1, #13
 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
 # CHECK-DISABLED: ADD

llvm/test/MC/ARM/register-token-source-loc.s

 // RUN: not llvm-mc -triple armv6m--none-eabi < %s 2>&1 | FileCheck %s
-
-// Some of these CHECK lines need to uses regexes to that the amount of
-// whitespace between the start of the line and the caret is significant.
-
   add sp, r0, #4
-// CHECK: error: invalid instruction, any one of the following would fix this:
-// CHECK: note: instruction requires: thumb2
-// CHECK: note: operand must be a register sp
-// CHECK-NEXT: {{^  add sp, r0, #4}}
-// CHECK-NEXT: {{^          \^}}
-// CHECK: note: too many operands for instruction
+// CHECK:     error: invalid instruction, any one of the following would fix this:
+// CHECK-NEXT:  add sp, r0, #4
+// CHECK-NEXT:  ^
+// CHECK-NEXT: note: operand must be a register sp
+// CHECK-NEXT:  add sp, r0, #4
+// CHECK-NEXT:          ^
+// CHECK-NEXT: note: too many operands for instruction
+// CHECK-NEXT:  add sp, r0, #4
+// CHECK-NEXT:              ^

llvm/test/MC/ARM/thumb-diagnostics.s

 
 
 @ Out of range immediate for ADD SP instructions
         add sp, #-1
         add sp, #3
         add sp, sp, #512
         add r2, sp, #1024
 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
-@ CHECK-ERRORS:         add sp, #-1
-@ CHECK-ERRORS:                 ^
+@ CHECK-ERRORS: add sp, #-1
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
+@ CHECK-ERRORS: add sp, #-1
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS: add sp, #-1
+@ CHECK-ERRORS:         ^
 @ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS: add sp, #-1
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
-@ CHECK-ERRORS:         add sp, #3
-@ CHECK-ERRORS:                 ^
+@ CHECK-ERRORS: add sp, #3
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
+@ CHECK-ERRORS: add sp, #3
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS: add sp, #3
+@ CHECK-ERRORS:         ^
 @ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS: add sp, #3
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
-@ CHECK-ERRORS:         add sp, sp, #512
-@ CHECK-ERRORS:                     ^
+@ CHECK-ERRORS: add sp, sp, #512
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
+@ CHECK-ERRORS: add sp, sp, #512
+@ CHECK-ERRORS:             ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS: add sp, sp, #512
+@ CHECK-ERRORS:             ^
 @ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS: add sp, sp, #512
+@ CHECK-ERRORS: ^
 @ CHECK-ERRORS: error: instruction requires: thumb2
-@ CHECK-ERRORS:         add r2, sp, #1024
-@ CHECK-ERRORS:         ^
-
+@ CHECK-ERRORS: add r2, sp, #1024
+@ CHECK-ERRORS: ^
         add r2, sp, ip
 @ CHECK-ERRORS: error: source register must be the same as destination
 @ CHECK-ERRORS:         add r2, sp, ip
 @ CHECK-ERRORS:                     ^
 
 
 @------------------------------------------------------------------------------
 @ B/Bcc - out of range immediates for Thumb1 branches

llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt

 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0xa5,0xf1,0x01,0x0d]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0xa7,0xf2,0x04,0x0d]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0xa3,0xeb,0x02,0x0d]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0xa3,0xeb,0xc5,0x0d]
+# CHECK-V7-NEXT: ^
+[0x0f,0xf2,0x00,0x4d]
+# CHECK-V7-NEXT: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x0f,0xf2,0x00,0x4d]
+# CHECK-V7-NEXT: ^

llvm/test/MC/Disassembler/ARM/thumb-tests.txt

-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
+# RUN: llvm-mc --disassemble --show-encoding %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
 
 # CHECK:  add r5, sp, #68
 0x11 0xad
 
 # CHECK:  adcs  r0, r0, #1
 0x50 0xf1 0x01 0x00
 
 # CHECK:  b #30

 0x0c 0xf3 0x10 0x00
 
 # CHECK:  strd  r0, r1, [r7, #64]
 0xc7 0xe9 0x10 0x01
 
 # CHECK:  sub sp, #60
 0x8f 0xb0
 
-# CHECK:  subw  r0, pc, #1
+# CHECK:  adr.w r0, #-1
 0xaf 0xf2 0x01 0x00
 
+# CHECK:  subw  r0, pc, #0
+0xaf 0xf2 0x00 0x00
+
 # CHECK:  subw  r0, sp, #835
 0xad 0xf2 0x43 0x30
 
 # CHECK:  uqadd16 r3, r4, r5
 0x94 0xfa 0x55 0xf3
 
 # CHECK:  usada8  r5, r4, r3, r2
 0x74 0xfb 0x03 0x25

 0x1f 0xc5
 
 # CHECK:  ldm r5, {r0, r1, r2, r3, r4, r5}
 0x3f 0xcd
 
 # CHECK:  ldm r5!, {r0, r1, r2, r3, r4}
 0x1f 0xcd
 
-# CHECK:  addw  r0, pc, #1050
+# CHECK:  adr.w r0, #1050
 0x0f 0xf2 0x1a 0x40
 
 # CHECK:  ldrd  r3, r8, [r11, #-60]
 0x5b 0xe9 0x0f 0x38
 
 # CHECK:  ldrex r8, [r2]
 0x52 0xe8 0x00 0x8f
 

 
 # CHECK:        ldrsb   r1, [r0, r0]
 0x01 0x56
 
 # CHECK:        ldrsh   r1, [r0, r0]
 0x01 0x5E
 
 # CHECK: and.w  r5, r1, r10, ror #7
 0x1 0xea 0xfa 0x95
 
 # CHECK: ldrsh  r6, [sp], #81
 0x3d 0xf9 0x51 0x6b
 
 # CHECK: usat16 r4, #10, r1
 0xa1 0xf3 0x0a 0x04
 
 # CHECK: smlad  r5, r12, r8, r11

llvm/test/MC/Disassembler/ARM/thumb2-v8.txt

 # CHECK: mrrc p15
 
 0x80 0xec 0x00 0x0e
 # CHECK: stc p14
 
 0x90 0xec 0x00 0x0e
 # CHECK: ldc p14
 
+[0x0f,0xf2,0x00,0x4d]
+# CHECK: adr.w   sp, #1024

llvm/test/MC/Disassembler/ARM/thumb2.txt

 0x13 0xeb 0xc1 0x77
 0x13 0xeb 0x56 0x60
 0x08 0xeb 0x31 0x34
 
 
 #------------------------------------------------------------------------------
 # ADR
 #------------------------------------------------------------------------------
-# CHECK: subw r11, pc, #3270
-# CHECK: subw r11, pc, #826
-# CHECK: subw r1, pc, #0
-
+# CHECK: adr.w r11, #-3270
+# CHECK-NEXT: adr.w r11, #-826
+# CHECK-NEXT: subw r1, pc, #0
+# CHECK-NEXT: adr.w   r0, #1024
 0xaf 0xf6 0xc6 0x4b
 0xaf 0xf2 0x3a 0x3b
 0xaf 0xf2 0x00 0x01
-
+0x0f,0xf2,0x00,0x40
 #------------------------------------------------------------------------------
 # AND (immediate)
 #------------------------------------------------------------------------------
 # CHECK: and r2, r5, #1044480
 # CHECK: ands r3, r12, #15
 # CHECK: and r1, r1, #255
 
 0x05 0xf4 0x7f 0x22

llvm/test/tools/llvm-mca/ARM/simple-cortex-m33.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv7 --mcpu=cortex-m33 -instruction-tables -o - %s | FileCheck %s
+
+sub sp, #4
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1     1.00                  U     sub sp, #4
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - M4Unit
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]
+# CHECK-NEXT: 1.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    Instructions:
+# CHECK-NEXT: 1.00   sub  sp, #4