[AArch64] Fix issues with large arrays on stack

[kiranchandramohan]

Summary

This patch fixes a few issues when large arrays are allocated on the stack. Currently, clang has inconsistent behaviour, for debug builds there is an assertion failure when the array size on stack is around 2GB but there is no assertion when the stack is around 8GB. For release builds there is no assertion, the compilation succeeds but generates incorrect code. The incorrect code generated is due to using int/unsigned int instead of their 64-bit counterparts. This patch,

1. Removes the assertion in frame legality check.
2. Converts int/unsigned int in some places to the 64-bit variants. This helps in generating correct code and removes the inconsistent behaviour.
3. Adds a test which runs without optimisations.

[fpetrogalli]

llvm/test/CodeGen/AArch64/large-stack.ll

2

Why can't you use the same prefix?

25

Do you need attribute #0 and #1?

[efriedma]

The general approach here seems fine, I guess. At least, we shouldn't crash or miscompile, and generating code to allocate the full requested stack is probably the easiest way to do that without worrying about weird edge cases. If we really cared about this, we might want to consider some heuristics to "split" the stack so spill slots and small variables are cheap to access, but I doubt that's actually important in practice.

Realistically, I can't imagine any good result from code allocating an 8GB array on the stack; no operating system is going to allocate enough stack to make this work, at least by default.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1394–1395

Indentation here needs to be fixed.

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

43

Is there a potential problem here as well?

llvm/test/CodeGen/AArch64/large-stack.ll

31

What sequence are we generating to adjust the stack pointer? For a large array that fits in 32 bits, I see a long sequence of "sub sp, sp, #4095, lsl #12"; are we doing the same thing here?

[kiranchandramohan]

Thanks @fpetrogalli, @eli.friedman for the review.

I have responded to the review comments. I have a few questions and will update with a new patch after your response to these questions.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1394–1395

Will fix, thanks.

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

43

I don't know whether i can answer that. Typically the ABI prohibits passing large objects by value. For e.g. the AArch64 ABI disallows passing composite types by value whose size is larger than 16bytes.
"If the argument type is a Composite Type that is larger than 16 bytes, then the argument is copied to memory allocated by the caller and the argument is replaced by a pointer to the copy."

If this refers to arguments only then probably it is not needed.

Do you feel there are cases which can cause this variable to have a high value which requires 64 bit?

llvm/test/CodeGen/AArch64/large-stack.ll

2

So that i can progressively construct the test. First check the spills, then the stack and the then accessing the value. Are you recommending combining them?

25

Maybe not. But these attributes are by default generated by clang and hence matches the IR that clang generates.

Also, the test will need updating since the attribute specified uses some attributes (no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf") which can change the assembly code generated.

What is the standard for these tests do you omit attributes?

31

Yes, we are doing the same thing here. That sequence is 128 long here.

[fpetrogalli]

llvm/test/CodeGen/AArch64/large-stack.ll

2

I can see value in having multiple prefixes when building the test. But multiple prefixes are designed to be used when executing multiple RUN lines on the same source. If you remove them the tests will be more clear.

If you need to highlight what you are checking, I'd rather add plain comments inline where the CHECKs are:

; Checking spill
; CHECK:                stp  x[[SPILL_REG1:[0-9]+]], x[[SPILL_REG2:[0-9]+]], [sp, #-[[SPILL_OFFSET1:[0-9]+]]]
; CHECK-NEXT:           str  x[[SPILL_REG3:[0-9]+]], [sp, #[[SPILL_OFFSET2:[0-9]+]]]
; Checking frame
; CHECK:                mov  x[[FRAME:[0-9]+]], sp
; Checking setstack count 128 bit
; CHECK:   sub  sp, sp, #[[STACK1:[0-9]+]], lsl #[[SHIFT:[0-9]+]]
; ...

25

If you need attributes, you should reduce them to the minimal set needed for the test. If no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" is all you need, remove the rest (and merge the two attributes in a single attribute). less is always better! :)

[efriedma]

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

43

I guess not in practice; functions can't have that many arguments.

[kiranchandramohan]

Addressed review comments by @fpetrogalli and @eli.friedman,

1. Fixed formatting in llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
2. Updated test to work with minimal attributes and removed prefixes for checks

[kiranchandramohan]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1394–1395

Done.

llvm/test/CodeGen/AArch64/large-stack.ll

25

Have now updated the test to have only the necessary attributes and also removed prefixes.

[kiranchandramohan]

Does this patch need additional reviews or changes?

[efriedma]

Please give reviewers at least a few days before you start pinging a patch. (I'll try to get to this today.)

[kiranchandramohan]

Apologies, will wait for the reviews.

[efriedma]

I'm a little concerned we've missed some conversion somewhere, but I don't have any good suggestion for that; we currently don't use integer conversion warnings in LLVM, and that would be a giant project to change.

There's some potential here that the arithmetic could overflow, even in 64 bits, but I'm not sure how we can handle that cleanly; I think it's okay to put off solving that issue.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

920

Indentation.

1037

This should also be uint64_t?

llvm/test/CodeGen/AArch64/large-stack.ll

29

Using FileCheck variables for values that will never change isn't helpful. For example, "lsl #[[SHIFT:[0-9]+]]" is actually always "lsl #12", because that's the only legal value.

Is there a reason some of these CHECKs aren't CHECK-NEXT?

[kiranchandramohan]

In general, I also worry that i might have missed some checks. I was hoping to get some pointers on how to run some tests so that we can minimise this. At the same time, I also feel that this change should not cause regressions.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1037

Initially missed out since this portion of the code seems to error out. But you are correct that it has to be int64_t to prevent overflows.

llvm/test/CodeGen/AArch64/large-stack.ll

29

I have removed the variables from here.

A few of these are CHECKS and not CHECK-NEXT.

1. Skips over some cfi attributes

; CHECK: sub x[[INDEX:[0-9]+]], x[[FRAME]], #8

2. Skips over some set up for calling the print function

; CHECK: bl printf

3. The CHECK-COUNTs did not seem to have a way of combining with NEXT.

; CHECK-COUNT-128: sub sp, sp, #[[STACK1:[0-9]+]], lsl #12
; CHECK-COUNT-128: add sp, sp, #[[STACK1]], lsl #12

Please let me know if this is not OK.

[efriedma]

LGTM

[kiranchandramohan]

Thanks @eli.friedman.
@fpetrogalli are you OK with the changes I made to your suggestions? Might need some handholding to land this patch.

[fpetrogalli]

In D70496#1770521, @kiranchandramohan wrote:

@fpetrogalli are you OK with the changes I made to your suggestions? Might need some handholding to land this patch.

I am happy, with a nit: I think that CHECK-COUNT-128 is ignored? Or is COUNT-128 a specific token for the CHECK prefix?

[fpetrogalli]

In D70496#1770739, @fpetrogalli wrote:

In D70496#1770521, @kiranchandramohan wrote:

@fpetrogalli are you OK with the changes I made to your suggestions? Might need some handholding to land this patch.

I am happy, with a nit: I think that CHECK-COUNT-128 is ignored? Or is COUNT-128 a specific token for the CHECK prefix?

Oh, I didn't know about this: https://llvm.org/docs/CommandGuide/FileCheck.html#the-check-count-directive

The patch LGTM. Thanks!

llvm/include/llvm/CodeGen/MachineFrameInfo.h

public:
   /// all of the fixed size frame objects.  This is only valid after
   /// Prolog/Epilog code insertion has finalized the stack frame layout.
   uint64_t getStackSize() const { return StackSize; }
 
   /// Set the size of the stack.
   void setStackSize(uint64_t Size) { StackSize = Size; }
 
   /// Estimate and return the size of the stack frame.
-  unsigned estimateStackSize(const MachineFunction &MF) const;
+  uint64_t estimateStackSize(const MachineFunction &MF) const;
 
   /// Return the correction for frame offsets.
   int getOffsetAdjustment() const { return OffsetAdjustment; }
 
   /// Set the correction for frame offsets.
   void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; }
 
   /// Return the alignment in bytes that this function must be aligned to,

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
 
   return *VRegs;
 }
 
 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
   if (FrameIndices.find(&AI) != FrameIndices.end())
     return FrameIndices[&AI];
 
-  unsigned ElementSize = DL->getTypeAllocSize(AI.getAllocatedType());
-  unsigned Size =
+  uint64_t ElementSize = DL->getTypeAllocSize(AI.getAllocatedType());
+  uint64_t Size =
       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
 
   // Always allocate at least one byte.
-  Size = std::max(Size, 1u);
+  Size = std::max<uint64_t>(Size, 1u);
 
   unsigned Alignment = AI.getAlignment();
   if (!Alignment)
     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
 
   int &FI = FrameIndices[&AI];
   FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
   return FI;

llvm/lib/CodeGen/MachineFrameInfo.cpp

BitVector MachineFrameInfo::getPristineRegs(const MachineFunction &MF) const {
   // Saved CSRs are not pristine.
   for (auto &I : getCalleeSavedInfo())
     for (MCSubRegIterator S(I.getReg(), TRI, true); S.isValid(); ++S)
       BV.reset(*S);
 
   return BV;
 }
 
-unsigned MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
+uint64_t MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   unsigned MaxAlign = getMaxAlignment();
-  int Offset = 0;
+  int64_t Offset = 0;
 
   // This code is very, very similar to PEI::calculateFrameObjectOffsets().
   // It really should be refactored to share code. Until then, changes
   // should keep in mind that there's tight coupling between the two.
 
   for (int i = getObjectIndexBegin(); i != 0; ++i) {
     // Only estimate stack size of default stack.
     if (getStackID(i) != TargetStackID::Default)
       continue;
-    int FixedOff = -getObjectOffset(i);
+    int64_t FixedOff = -getObjectOffset(i);
     if (FixedOff > Offset) Offset = FixedOff;
   }
   for (unsigned i = 0, e = getObjectIndexEnd(); i != e; ++i) {
     // Only estimate stack size of live objects on default stack.
     if (isDeadObjectIndex(i) || getStackID(i) != TargetStackID::Default)
       continue;
     Offset += getObjectSize(i);
     unsigned Align = getObjectAlignment(i);
else
     StackAlign = TFI->getTransientStackAlignment();
 
   // If the frame pointer is eliminated, all frame offsets will be relative to
   // SP not FP. Align to MaxAlign so this works.
   StackAlign = std::max(StackAlign, MaxAlign);
   unsigned AlignMask = StackAlign - 1;
   Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
 
-  return (unsigned)Offset;
+  return (uint64_t)Offset;
 }
 
 void MachineFrameInfo::computeMaxCallFrameSize(const MachineFunction &MF) {
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
   unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
   assert(FrameSetupOpcode != ~0u && FrameDestroyOpcode != ~0u &&
          "Can only compute MaxCallFrameSize if Setup/Destroy opcode are known");

llvm/lib/Target/AArch64/AArch64FrameLowering.h

public:
   bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
 
   int getFrameIndexReference(const MachineFunction &MF, int FI,
                              unsigned &FrameReg) const override;
   StackOffset resolveFrameIndexReference(const MachineFunction &MF, int FI,
                                          unsigned &FrameReg, bool PreferFP,
                                          bool ForSimm) const;
   StackOffset resolveFrameOffsetReference(const MachineFunction &MF,
-                                          int ObjectOffset, bool isFixed,
+                                          int64_t ObjectOffset, bool isFixed,
                                           bool isSVE, unsigned &FrameReg,
                                           bool PreferFP, bool ForSimm) const;
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
bool isSupportedStackID(TargetStackID::Value ID) const override {
     case TargetStackID::SVEVector:
     case TargetStackID::NoAlloc:
       return true;
     }
   }
 
 private:
   bool shouldCombineCSRLocalStackBump(MachineFunction &MF,
-                                      unsigned StackBumpBytes) const;
+                                      uint64_t StackBumpBytes) const;
 
   int64_t estimateSVEStackObjectOffsets(MachineFrameInfo &MF) const;
   int64_t assignSVEStackObjectOffsets(MachineFrameInfo &MF,
                                       int &MinCSFrameIndex,
                                       int &MaxCSFrameIndex) const;
 };
 
 } // End llvm namespace
 
 #endif

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

if (!EnableRedZone)
     return false;
   // Don't use the red zone if the function explicitly asks us not to.
   // This is typically used for kernel code.
   if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone))
     return false;
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
-  unsigned NumBytes = AFI->getLocalStackSize();
+  uint64_t NumBytes = AFI->getLocalStackSize();
 
   return !(MFI.hasCalls() || hasFP(MF) || NumBytes > 128 ||
            getSVEStackSize(MF));
 }
 
 /// hasFP - Return true if the specified function should have a dedicated frame
 /// pointer register.
 bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
bool AArch64FrameLowering::canUseAsPrologue(
   if (!RegInfo->needsStackRealignment(*MF))
     return true;
   // Otherwise, we can use any block as long as it has a scratch register
   // available.
   return findScratchNonCalleeSaveRegister(TmpMBB) != AArch64::NoRegister;
 }
 
 static bool windowsRequiresStackProbe(MachineFunction &MF,
-                                      unsigned StackSizeInBytes) {
+                                      uint64_t StackSizeInBytes) {
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   if (!Subtarget.isTargetWindows())
     return false;
   const Function &F = MF.getFunction();
   // TODO: When implementing stack protectors, take that into account
   // for the probe threshold.
   unsigned StackProbeSize = 4096;
   if (F.hasFnAttribute("stack-probe-size"))
     F.getFnAttribute("stack-probe-size")
         .getValueAsString()
         .getAsInteger(0, StackProbeSize);
   return (StackSizeInBytes >= StackProbeSize) &&
          !F.hasFnAttribute("no-stack-arg-probe");
 }
 
 bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(
-    MachineFunction &MF, unsigned StackBumpBytes) const {
+    MachineFunction &MF, uint64_t StackBumpBytes) const {
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
 
   if (MF.getFunction().hasOptSize())
     return false;
 
static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
   }
 
   return std::prev(MBB.erase(MBBI));
 }
 
 // Fixup callee-save register save/restore instructions to take into account
 // combined SP bump by adding the local stack size to the stack offsets.
 static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI,
-                                              unsigned LocalStackSize,
+                                              uint64_t LocalStackSize,
                                               bool NeedsWinCFI,
                                               bool *HasWinCFI) {
   if (AArch64InstrInfo::isSEHInstruction(MI))
     return;
 
   unsigned Opc = MI.getOpcode();
 
   // Ignore instructions that do not operate on SP, i.e. shadow call stack
void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   const StackOffset &SVEStackSize = getSVEStackSize(MF);
 
   // getStackSize() includes all the locals in its size calculation. We don't
   // include these locals when computing the stack size of a funclet, as they
   // are allocated in the parent's stack frame and accessed via the frame
   // pointer from the funclet.  We only save the callee saved registers in the
   // funclet, which are really the callee saved registers of the parent
   // function, including the funclet.
-  int NumBytes = IsFunclet ? (int)getWinEHFuncletFrameSize(MF)
-                           : (int)MFI.getStackSize();
+  int64_t NumBytes = IsFunclet ? getWinEHFuncletFrameSize(MF)
+                           : MFI.getStackSize();
   if (!AFI->hasStackFrame() && !windowsRequiresStackProbe(MF, NumBytes)) {
     assert(!HasFP && "unexpected function without stack frame but with FP");
     assert(!SVEStackSize &&
            "unexpected function without stack frame but with SVE objects");
     // All of the stack allocation is for locals.
     AFI->setLocalStackSize(NumBytes);
     if (!NumBytes)
       return;
if (F.hasPersonalityFn()) {
       }
     }
 
     return;
   }
 
   if (HasFP) {
     // Only set up FP if we actually need to.
-    int FPOffset = isTargetDarwin(MF) ? (AFI->getCalleeSavedStackSize() - 16) : 0;
+    int64_t FPOffset = isTargetDarwin(MF) ? (AFI->getCalleeSavedStackSize() - 16) : 0;
 
     if (CombineSPBump)
       FPOffset += AFI->getLocalStackSize();
 
     // Issue    sub fp, sp, FPOffset or
     //          mov fp,sp          when FPOffset is zero.
     // Note: All stores of callee-saved registers are marked as "FrameSetup".
     // This code marks the instruction(s) that set the FP also.
     emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP,
                     {FPOffset, MVT::i8}, TII, MachineInstr::FrameSetup, false,
                     NeedsWinCFI, &HasWinCFI);
   }
 
   if (windowsRequiresStackProbe(MF, NumBytes)) {
     uint32_t NumWords = NumBytes >> 4;
     if (NeedsWinCFI) {
       HasWinCFI = true;
       // alloc_l can hold at most 256MB, so assume that NumBytes doesn't
       // exceed this amount.  We need to move at most 2^24 - 1 into x15.
       // This is at most two instructions, MOVZ follwed by MOVK.
       // TODO: Fix to use multiple stack alloc unwind codes for stacks
       // exceeding 256MB in size.
       if (NumBytes >= (1 << 28))
if (MBB.end() != MBBI) {
     DL = MBBI->getDebugLoc();
     unsigned RetOpcode = MBBI->getOpcode();
     IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
                        RetOpcode == AArch64::TCRETURNri ||
                        RetOpcode == AArch64::TCRETURNriBTI;
     IsFunclet = isFuncletReturnInstr(*MBBI);
   }
 
-  int NumBytes = IsFunclet ? (int)getWinEHFuncletFrameSize(MF)
+  int64_t NumBytes = IsFunclet ? getWinEHFuncletFrameSize(MF)
                                : MFI.getStackSize();
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
   // Initial and residual are named for consistency with the prologue. Note that
void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
   if (!hasFP(MF)) {
     bool RedZone = canUseRedZone(MF);
     // If this was a redzone leaf function, we don't need to restore the
     // stack pointer (but we may need to pop stack args for fastcc).
     if (RedZone && AfterCSRPopSize == 0)
       return;
 
     bool NoCalleeSaveRestore = PrologueSaveSize == 0;
-    int StackRestoreBytes = RedZone ? 0 : NumBytes;
+    int64_t StackRestoreBytes = RedZone ? 0 : NumBytes;
     if (NoCalleeSaveRestore)
       StackRestoreBytes += AfterCSRPopSize;
 
     // If we were able to combine the local stack pop with the argument pop,
     // then we're done.
     bool Done = NoCalleeSaveRestore || AfterCSRPopSize == 0;
 
     // If we're done after this, make sure to help the load store optimizer.
return resolveFrameIndexReference(
       .getBytes();
 }
 
 int AArch64FrameLowering::getNonLocalFrameIndexReference(
   const MachineFunction &MF, int FI) const {
   return getSEHFrameIndexOffset(MF, FI);
 }
 
-static StackOffset getFPOffset(const MachineFunction &MF, int ObjectOffset) {
+static StackOffset getFPOffset(const MachineFunction &MF, int64_t ObjectOffset) {
   const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
   const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   bool IsWin64 =
       Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
   unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
   unsigned FPAdjust = isTargetDarwin(MF)
                         ? 16 : AFI->getCalleeSavedStackSize(MF.getFrameInfo());
   return {ObjectOffset + FixedObject + FPAdjust, MVT::i8};
 }
 
-static StackOffset getStackOffset(const MachineFunction &MF, int ObjectOffset) {
+static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset) {
   const auto &MFI = MF.getFrameInfo();
-  return {ObjectOffset + (int)MFI.getStackSize(), MVT::i8};
+  return {ObjectOffset + (int64_t)MFI.getStackSize(), MVT::i8};
 }
 
 int AArch64FrameLowering::getSEHFrameIndexOffset(const MachineFunction &MF,
                                                  int FI) const {
   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(
       MF.getSubtarget().getRegisterInfo());
   int ObjectOffset = MF.getFrameInfo().getObjectOffset(FI);
   return RegInfo->getLocalAddressRegister(MF) == AArch64::FP
              ? getFPOffset(MF, ObjectOffset).getBytes()
              : getStackOffset(MF, ObjectOffset).getBytes();
 }
 
 StackOffset AArch64FrameLowering::resolveFrameIndexReference(
     const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP,
     bool ForSimm) const {
   const auto &MFI = MF.getFrameInfo();
-  int ObjectOffset = MFI.getObjectOffset(FI);
+  int64_t ObjectOffset = MFI.getObjectOffset(FI);
   bool isFixed = MFI.isFixedObjectIndex(FI);
   bool isSVE = MFI.getStackID(FI) == TargetStackID::SVEVector;
   return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
                                      PreferFP, ForSimm);
 }
 
 StackOffset AArch64FrameLowering::resolveFrameOffsetReference(
-    const MachineFunction &MF, int ObjectOffset, bool isFixed, bool isSVE,
+    const MachineFunction &MF, int64_t ObjectOffset, bool isFixed, bool isSVE,
     unsigned &FrameReg, bool PreferFP, bool ForSimm) const {
   const auto &MFI = MF.getFrameInfo();
   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(
       MF.getSubtarget().getRegisterInfo());
   const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
   const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
 
-  int FPOffset = getFPOffset(MF, ObjectOffset).getBytes();
-  int Offset = getStackOffset(MF, ObjectOffset).getBytes();
+  int64_t FPOffset = getFPOffset(MF, ObjectOffset).getBytes();
+  int64_t Offset = getStackOffset(MF, ObjectOffset).getBytes();
   bool isCSR =
       !isFixed && ObjectOffset >= -((int)AFI->getCalleeSavedStackSize(MFI));
 
   const StackOffset &SVEStackSize = getSVEStackSize(MF);
 
   // Use frame pointer to reference fixed objects. Use it for locals if
   // there are VLAs or a dynamically realigned SP (and thus the SP isn't
   // reliable as a base). Make sure useFPForScavengingIndex() does the
for (unsigned Reg : SavedRegs.set_bits()) {
     else
       CSStackSize += RegSize;
   }
 
   // Save number of saved regs, so we can easily update CSStackSize later.
   unsigned NumSavedRegs = SavedRegs.count();
 
   // The frame record needs to be created by saving the appropriate registers
-  unsigned EstimatedStackSize = MFI.estimateStackSize(MF);
+  uint64_t EstimatedStackSize = MFI.estimateStackSize(MF);
   if (hasFP(MF) ||
       windowsRequiresStackProbe(MF, EstimatedStackSize + CSStackSize + 16)) {
     SavedRegs.set(AArch64::FP);
     SavedRegs.set(AArch64::LR);
   }
 
   LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nSaved CSRs:";
              for (unsigned Reg
if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
       RS->addScavengingFrameIndex(FI);
       LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
                         << " as the emergency spill slot.\n");
     }
   }
 
   // Adding the size of additional 64bit GPR saves.
   CSStackSize += 8 * (SavedRegs.count() - NumSavedRegs);
-  unsigned AlignedCSStackSize = alignTo(CSStackSize, 16);
+  uint64_t AlignedCSStackSize = alignTo(CSStackSize, 16);
   LLVM_DEBUG(dbgs() << "Estimated stack frame size: "
                << EstimatedStackSize + AlignedCSStackSize
                << " bytes.\n");
 
   assert((!MFI.isCalleeSavedInfoValid() ||
           AFI->getCalleeSavedStackSize() == AlignedCSStackSize) &&
          "Should not invalidate callee saved info");
 

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

static void emitFrameOffsetAdj(MachineBasicBlock &MBB,
   // register can be loaded with offset%8 and the add/sub can use an extending
   // instruction with LSL#3.
   // Currently the function handles any offsets but generates a poor sequence
   // of code.
   //  assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
 
   const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
   do {
-    unsigned ThisVal = std::min<unsigned>(Offset, MaxEncodableValue);
+    uint64_t ThisVal = std::min<uint64_t>(Offset, MaxEncodableValue);
     unsigned LocalShiftSize = 0;
     if (ThisVal > MaxEncoding) {
       ThisVal = ThisVal >> ShiftSize;
       LocalShiftSize = ShiftSize;
     }
     assert((ThisVal >> ShiftSize) <= MaxEncoding &&
            "Encoding cannot handle value that big");
     auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

class AArch64FunctionInfo final : public MachineFunctionInfo {
   /// is expected to restore the argument stack this should be a multiple of 16,
   /// all usable during a tail call.
   ///
   /// The alternative would forbid tail call optimisation in some cases: if we
   /// want to transfer control from a function with 8-bytes of stack-argument
   /// space to a function with 16-bytes then misalignment of this value would
   /// make a stack adjustment necessary, which could not be undone by the
   /// callee.
   unsigned BytesInStackArgArea = 0;
 
   /// The number of bytes to restore to deallocate space for incoming
   /// arguments. Canonically 0 in the C calling convention, but non-zero when
   /// callee is expected to pop the args.
   unsigned ArgumentStackToRestore = 0;
 
   /// HasStackFrame - True if this function has a stack frame. Set by
   /// determineCalleeSaves().
   bool HasStackFrame = false;
 
   /// Amount of stack frame size, not including callee-saved registers.
-  unsigned LocalStackSize = 0;
+  uint64_t LocalStackSize = 0;
 
   /// The start and end frame indices for the SVE callee saves.
   int MinSVECSFrameIndex = 0;
   int MaxSVECSFrameIndex = 0;
 
   /// Amount of stack frame size used for saving callee-saved registers.
   unsigned CalleeSavedStackSize = 0;
   unsigned SVECalleeSavedStackSize = 0;
bool hasCalleeSaveStackFreeSpace() const {
     return CalleeSaveStackHasFreeSpace;
   }
   void setCalleeSaveStackHasFreeSpace(bool s) {
     CalleeSaveStackHasFreeSpace = s;
   }
   bool isSplitCSR() const { return IsSplitCSR; }
   void setIsSplitCSR(bool s) { IsSplitCSR = s; }
 
-  void setLocalStackSize(unsigned Size) { LocalStackSize = Size; }
-  unsigned getLocalStackSize() const { return LocalStackSize; }
+  void setLocalStackSize(uint64_t Size) { LocalStackSize = Size; }
+  uint64_t getLocalStackSize() const { return LocalStackSize; }
 
   void setCalleeSavedStackSize(unsigned Size) {
     CalleeSavedStackSize = Size;
     HasCalleeSavedStackSize = true;
   }
 
   // When CalleeSavedStackSize has not been set (for example when
   // some MachineIR pass is run in isolation), then recalculate

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
 
   // The offset likely isn't legal; we want to allocate a virtual base register.
   return true;
 }
 
 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
                                              unsigned BaseReg,
                                              int64_t Offset) const {
-  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
   assert(MI && "Unable to get the legal offset for nil instruction.");
   StackOffset SaveOffset(Offset, MVT::i8);
   return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
 }
 
 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
 /// at the beginning of the basic block.
 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,

llvm/test/CodeGen/AArch64/large-stack.ll

+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+@.str = private unnamed_addr constant [11 x i8] c"val = %ld\0A\00", align 1
+
+; Function Attrs: noinline optnone
+define dso_local void @set_large(i64 %val) #0 {
+entry:
+  %val.addr = alloca i64, align 8
+  %large = alloca [268435456 x i64], align 8
+  %i = alloca i32, align 4
+  store i64 %val, i64* %val.addr, align 8
+  %0 = load i64, i64* %val.addr, align 8
+  %arrayidx = getelementptr inbounds [268435456 x i64], [268435456 x i64]* %large, i64 0, i64 %0
+  store i64 1, i64* %arrayidx, align 8
+  %1 = load i64, i64* %val.addr, align 8
+  %arrayidx1 = getelementptr inbounds [268435456 x i64], [268435456 x i64]* %large, i64 0, i64 %1
+  %2 = load i64, i64* %arrayidx1, align 8
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i64 %2)
+  ret void
+}
+
+declare dso_local i32 @printf(i8*, ...)
+
+attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" }
+
+; CHECK:                  stp x[[SPILL_REG1:[0-9]+]], x[[SPILL_REG2:[0-9]+]], [sp, #-[[SPILL_OFFSET1:[0-9]+]]]
+; CHECK-NEXT:             str x[[SPILL_REG3:[0-9]+]], [sp, #[[SPILL_OFFSET2:[0-9]+]]]
+; CHECK:                  mov x[[FRAME:[0-9]+]], sp
+; CHECK-COUNT-128:        sub sp, sp, #[[STACK1:[0-9]+]], lsl #[[SHIFT:[0-9]+]]
+; CHECK-NEXT:             sub sp, sp, #[[STACK2:[0-9]+]], lsl #[[SHIFT]]
+; CHECK-NEXT:             sub sp, sp, #[[STACK3:[0-9]+]]
+; CHECK:                  sub x[[INDEX:[0-9]+]], x[[FRAME]], #8
+; CHECK-NEXT:             str x0, [x[[INDEX]]]
+; CHECK-NEXT:             ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
+; CHECK-NEXT:             mov x[[VAL2:[0-9]+]], #8
+; CHECK-NEXT:             add x[[VAL3:[0-9]+]], sp, #8
+; CHECK-NEXT:             madd  x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]]
+; CHECK-NEXT:             mov x[[TMP1:[0-9]+]], #1
+; CHECK-NEXT:             str x[[TMP1]], [x[[VAL1]]]
+; CHECK-NEXT:             ldr x[[INDEX]], [x[[INDEX]]]
+; CHECK-NEXT:             mov x[[VAL4:[0-9]+]], #8
+; CHECK-NEXT:             madd  x[[INDEX]], x[[INDEX]], x[[VAL4]], x[[VAL3]]
+; CHECK-NEXT:             ldr x1, [x[[INDEX]]
+; CHECK:                  bl  printf
+; CHECK-COUNT-128:        add sp, sp, #[[STACK1]], lsl #[[SHIFT]]
+; CHECK-NEXT:             add sp, sp, #[[STACK2]], lsl #[[SHIFT]]
+; CHECK-NEXT:             add sp, sp, #[[STACK3]]
+; CHECK:                  ldr x[[SPILL_REG3]], [sp, #[[SPILL_OFFSET2]]]
+; CHECK-NEXT:             ldp x[[SPILL_REG1]], x[[SPILL_REG2]], [sp], #[[SPILL_OFFSET1]]