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[PowerPC] Relax the restrictions on loading doubles with SPE
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Authored by jhibbits on Oct 27 2019, 12:46 PM.

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nemanjai
hfinkel
joerg
stefanp
Group Reviewers
Restricted Project
Summary

The original commit forced all 64-bit values to be loaded from indexed
registers, regardless of how close they were located to a given base
register. This relaxes that, and permits some to be immediate-indexed
if they fit within a signed 255 (really 248, 8-byte aligned mask) byte
window. Patch by kthomsen.

Event Timeline

jhibbits created this revision.Oct 27 2019, 12:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 27 2019, 12:46 PM
jhibbits added a reviewer: Restricted Project.Dec 5 2019, 9:54 AM
emaste added a subscriber: emaste.Dec 5 2019, 9:55 AM
stefanp requested changes to this revision.Dec 5 2019, 7:16 PM
stefanp added a subscriber: stefanp.

Please add a test case for this.
Maybe an test were we have an SPE load of f64 with a 8 bit offset and one where the offset is larger or perhaps not aligned. Anyway, that's just a suggestion. You probably have a better idea of what you would like to test for this.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp
2281

This section of code looks to be loop invariant. I'm not sure if the intention was to use UT or not but if it is invariant you can pull it out of the loop. Basically, if isIntU8Immediate(N.getOperand(1), imm) && !(imm % EVXEncodingAlignment) is true then the function can only return false.

This revision now requires changes to proceed.Dec 5 2019, 7:16 PM

@kthomsen do you have any tests we can massage for this?

@jhibbits Sorry, I'm stucked in an important project and had no time, during the last 3 month, to do anything on the CLANG.