SPE follows soft-float ABI for doubles, including VAARG passing. For
soft-float, doubles are bitcast to i64, but for SPE they are not, so we
need to perform GPR alignment explicitly for SPE f64.
I think that for f64 on SPE the GprIndex you are computing it going to be ignored. (See my comment...)
Also, would it be possible to add a test case to go with it?
You are computing a new GprIndex above for MVT::f64 on SPE.
Oops, you're right, I need to update RegConstant as well.