[SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.

[foad]

Summary

This is used on AMDGPU for rounding from v3f64 (which is illegal) to
v3f32 (which is legal).

[craig.topper]

I think the code looks fine, but it doesn't look like some of the code is tested. And may not be testable?

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

4301

I'm not sure how this if could be true given that the opposite was checked in outer if. But since that was already like that when you got here this looks fine.

llvm/test/CodeGen/AMDGPU/fptrunc.ll

34

Is this hitting the unrolling path rather than any of the code that creates a wider node?

[foad]

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

4301

I hadn't noticed that. My guess is that the check for !N->isStrictFPOpcode() in the outer if was added along with the FIXME comment, so maybe it was supposed to be a temporary fix?

llvm/test/CodeGen/AMDGPU/fptrunc.ll

34

The test definitely fails without the fix above, but I haven't looked in detail at how it is handled.

[arsenm]

llvm/test/CodeGen/AMDGPU/fptrunc.ll

34

I would expect this to hit the unroll path. v3f64 isn't legal

[craig.topper]

LGTM

[foad]

llvm/test/CodeGen/AMDGPU/fptrunc.ll

34

If I'm reading the legalize-types debug output correctly it is being widened to v4 and then split to v2:

Legalizing node: t33: v3f32 = fp_round t30, TargetConstant:i64<0>
Analyzing result type: v3f32
Legal result type
Analyzing operand: t30: v3f64 = extract_subvector t37, Constant:i32<0>
Widen node operand 0: t33: v3f32 = fp_round t30, TargetConstant:i64<0>

Legalizing node: t49: v4f32 = fp_round t37, TargetConstant:i64<0>
Analyzing result type: v4f32
Legal result type
Analyzing operand: t37: v4f64 = bitcast t36
Split node operand: t49: v4f32 = fp_round t37, TargetConstant:i64<0>

Is that a problem? Is my patch still OK?

[craig.topper]

llvm/test/CodeGen/AMDGPU/fptrunc.ll

34

Ok so v4f32 result type is legal so it went up to v4f32 <- v4f64, but then v4f64 isn't legal so it split back down? I think that should be fine. But maybe @arsenm should confirm.

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::ANY_EXTEND:
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
     Res = WidenVecOp_EXTEND(N);
     break;
 
   case ISD::FP_EXTEND:
   case ISD::STRICT_FP_EXTEND:
+  case ISD::FP_ROUND:
+  case ISD::STRICT_FP_ROUND:
   case ISD::FP_TO_SINT:
   case ISD::STRICT_FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::STRICT_FP_TO_UINT:
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
   case ISD::TRUNCATE:
     Res = WidenVecOp_Convert(N);
SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
   unsigned Opcode = N->getOpcode();
 
   // See if a widened result type would be legal, if so widen the node.
   // FIXME: This isn't safe for StrictFP. Other optimization here is needed.
   EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
                                 InVT.getVectorNumElements());
   if (TLI.isTypeLegal(WideVT) && !N->isStrictFPOpcode()) {
     SDValue Res;
     if (N->isStrictFPOpcode()) {
-      Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other }, 
+      if (Opcode == ISD::STRICT_FP_ROUND)
+        Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
+                          { N->getOperand(0), InOp, N->getOperand(2) });
+      else
+        Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
                           { N->getOperand(0), InOp });
       // Legalize the chain result - switch anything that used the old chain to
       // use the new one.
       ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
-    } else
+    } else {
+      if (Opcode == ISD::FP_ROUND)
+        Res = DAG.getNode(Opcode, dl, WideVT, InOp, N->getOperand(1));
+      else
         Res = DAG.getNode(Opcode, dl, WideVT, InOp);
+    }
     return DAG.getNode(
         ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
         DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
   }
 
   EVT InEltVT = InVT.getVectorElementType();
 
   // Unroll the convert into some scalar code and create a nasty build vector.

llvm/test/CodeGen/AMDGPU/fptrunc.ll

 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x double> %in) {
   %result = fptrunc <2 x double> %in to <2 x float>
   store <2 x float> %result, <2 x float> addrspace(1)* %out
   ret void
 }
 
+; FUNC-LABEL: {{^}}fptrunc_v3f64_to_v3f32:
+; GCN: v_cvt_f32_f64_e32
+; GCN: v_cvt_f32_f64_e32
+; GCN: v_cvt_f32_f64_e32
+define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(<3 x float> addrspace(1)* %out, <3 x double> %in) {
+  %result = fptrunc <3 x double> %in to <3 x float>
+  store <3 x float> %result, <3 x float> addrspace(1)* %out
+  ret void
+}
+
 ; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 define amdgpu_kernel void @fptrunc_v4f64_to_v4f32(<4 x float> addrspace(1)* %out, <4 x double> %in) {
   %result = fptrunc <4 x double> %in to <4 x float>
   store <4 x float> %result, <4 x float> addrspace(1)* %out