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hliao (Michael Liao)
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Aug 7 2014, 12:01 PM (258 w, 3 d)

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Today

hliao added a comment to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..

when we insert that copy, if we still follow the current logic of phi-elim, that COPY is already inserted after its use (that CF_END).

Mon, Jul 22, 6:02 AM · Restricted Project

Fri, Jul 19

hliao added a comment to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..

It sounds to me that additional hook is a clear change. Or, we need to change the existing hook from const MachineInstr & to MachineInstr & to allow changing instruction. Any idea?

Fri, Jul 19, 11:56 AM · Restricted Project
hliao committed rGff9c9e644db9: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass (authored by hliao).
[AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass
Fri, Jul 19, 11:52 AM
hliao committed rL366602: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.
[AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass
Fri, Jul 19, 11:51 AM
hliao closed D64273: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.
Fri, Jul 19, 11:51 AM · Restricted Project

Thu, Jul 18

hliao added inline comments to D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..
Thu, Jul 18, 1:49 PM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

Please review https://reviews.llvm.org/D64946 following your suggestion.

Thu, Jul 18, 1:32 PM · Restricted Project
hliao created D64946: [AMDGPU] Fix trivial PHI into SI_END_CF..
Thu, Jul 18, 1:32 PM · Restricted Project
hliao committed rG17a8a9277c11: [LAA] Re-check bit-width of pointers after stripping. (authored by hliao).
[LAA] Re-check bit-width of pointers after stripping.
Thu, Jul 18, 10:33 AM
hliao committed rL366470: [LAA] Re-check bit-width of pointers after stripping..
[LAA] Re-check bit-width of pointers after stripping.
Thu, Jul 18, 10:32 AM
hliao closed D64928: [LAA] Re-check bit-width of pointers after stripping..
Thu, Jul 18, 10:32 AM · Restricted Project
hliao committed rG9ad917c2da72: Minor styling fix. NFC. (authored by hliao).
Minor styling fix. NFC.
Thu, Jul 18, 9:15 AM
hliao committed rL366456: Minor styling fix. NFC..
Minor styling fix. NFC.
Thu, Jul 18, 9:14 AM
hliao added a comment to D64928: [LAA] Re-check bit-width of pointers after stripping..

a similar case to https://reviews.llvm.org/D64768

Thu, Jul 18, 9:06 AM · Restricted Project
hliao created D64928: [LAA] Re-check bit-width of pointers after stripping..
Thu, Jul 18, 9:06 AM · Restricted Project

Wed, Jul 17

hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

No matter what, running UnreachableMachineBlockElim is not a fix for this.

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

any use before def is invalid MIR, right?

So the MIR is valid before phi elimination, and then becomes invalid after. Removing unreachable blocks earlier to avoid this happening is a workaround. It seems to me like we need to fix PHI elimination or avoid relying on the prolog instructions

my understanding is that MBB prologue instructions are designed NOT to take PHI as input. Like these pseudo instructions for structurized CFG, by design, they don't take any PHI as input. As an alternative approach (not workaround), we could ensure these instructions not taking PHI as input before PHIElim instead of teaching PHIElim to under them, more or less very target-specific stuff.

The verifier should probably check this. We definitely should not hack around this by deleting unreachable blocks that happens to run into this

Wed, Jul 17, 12:27 PM · Restricted Project

Tue, Jul 16

hliao committed rGccf22ef94c4a: Fix -Wreturn-type warning. NFC. (authored by hliao).
Fix -Wreturn-type warning. NFC.
Tue, Jul 16, 1:00 PM
hliao committed rL366251: Fix -Wreturn-type warning. NFC..
Fix -Wreturn-type warning. NFC.
Tue, Jul 16, 1:00 PM
hliao committed rGb3f967d41135: [AMDGPU] Add the adjusted FP as a livein register. (authored by hliao).
[AMDGPU] Add the adjusted FP as a livein register.
Tue, Jul 16, 9:00 AM
hliao committed rL366223: [AMDGPU] Add the adjusted FP as a livein register..
[AMDGPU] Add the adjusted FP as a livein register.
Tue, Jul 16, 8:59 AM
hliao closed D64145: [AMDGPU] Add the adjusted FP as a livein register..
Tue, Jul 16, 8:59 AM · Restricted Project
hliao added a comment to D64145: [AMDGPU] Add the adjusted FP as a livein register..

LGTM with nit

Tue, Jul 16, 8:58 AM · Restricted Project
hliao updated the diff for D64145: [AMDGPU] Add the adjusted FP as a livein register..

revise the test case

Tue, Jul 16, 6:50 AM · Restricted Project

Mon, Jul 15

hliao committed rG543ba4e9e0c4: [InstructionSimplify] Apply sext/trunc after pointer stripping (authored by hliao).
[InstructionSimplify] Apply sext/trunc after pointer stripping
Mon, Jul 15, 6:04 PM
hliao committed rL366162: [InstructionSimplify] Apply sext/trunc after pointer stripping.
[InstructionSimplify] Apply sext/trunc after pointer stripping
Mon, Jul 15, 6:03 PM
hliao closed D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.
Mon, Jul 15, 6:03 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

LGTM, one request and a proposal to fix it slightly differently.

This is fine with me. Though, I'm unsure if this should not live in the stripAndAccumulateConstantOffsets method.

The problem is that we have two bit-widths now, pointer before and after. Since we have to express offset in one of them, we have a choice.
I think we already guarantee that the offset is representable in the initial bit-width so that was what I choose. Question is, do we want
to change it to be in the resulting bit-width or not. Either way, we should add a comment to the stripAndAccumulateConstantOffsets method
explaining the situation.

As I mentioned, without this fix, there are crashes when compiling similar patterns. The issue is that LHS gets the original bit-width as the offset is 0 and RHS gets the one after stripping. Later, as the stripped pointers point the same object, instsimplify will create compare of the offset, that triggers the crash. We have to ensure offset after stripping has the same bit-width.

I understand. That is what I tried to describe above. My question was: Should stripAndAccumulateConstantOffsets return the offset wrt. the bit-width of the input pointer or output pointer? I can see arguments for both. If you think this way is better you can go ahead and commit. If you think the other way around is better, we should move the conversion into stripAndAccumulateConstantOffsets. I personally tend towards the latter.

Either way, we have to add a comment to the stripAndAccumulateConstantOffsets method explaining the choice!

Mon, Jul 15, 6:02 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

This is fine with me. Though, I'm unsure if this should not live in the stripAndAccumulateConstantOffsets method.

The problem is that we have two bit-widths now, pointer before and after. Since we have to express offset in one of them, we have a choice.
I think we already guarantee that the offset is representable in the initial bit-width so that was what I choose. Question is, do we want
to change it to be in the resulting bit-width or not. Either way, we should add a comment to the stripAndAccumulateConstantOffsets method
explaining the situation.

Mon, Jul 15, 3:16 PM · Restricted Project
hliao added a comment to D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.

this fixes crashes found on targets where addrspacecast is used.

Mon, Jul 15, 1:48 PM · Restricted Project
hliao created D64768: [InstructionSimplify] Apply sext/trunc after pointer stripping.
Mon, Jul 15, 1:48 PM · Restricted Project

Sat, Jul 13

hliao committed rG124cae7d3fc5: Remove extra ';' to silent compiler warning. (authored by hliao).
Remove extra ';' to silent compiler warning.
Sat, Jul 13, 12:53 PM
hliao committed rL366010: Remove extra ';' to silent compiler warning..
Remove extra ';' to silent compiler warning.
Sat, Jul 13, 12:49 PM

Thu, Jul 11

hliao committed rG16d3c1ac03d3: [AMDGPU] Skip calculating callee saved registers for entry function. (authored by hliao).
[AMDGPU] Skip calculating callee saved registers for entry function.
Thu, Jul 11, 4:54 PM
hliao committed rL365846: [AMDGPU] Skip calculating callee saved registers for entry function..
[AMDGPU] Skip calculating callee saved registers for entry function.
Thu, Jul 11, 4:53 PM
hliao closed D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Thu, Jul 11, 4:53 PM · Restricted Project
hliao added a comment to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..

What is this supposed to solve?

Thu, Jul 11, 2:26 PM · Restricted Project
hliao updated the diff for D64596: [AMDGPU] Skip calculating callee saved registers for entry function..

skip determining callee saved scalar register as well.

Thu, Jul 11, 2:22 PM · Restricted Project
hliao added inline comments to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Thu, Jul 11, 2:17 PM · Restricted Project
hliao added inline comments to D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Thu, Jul 11, 2:16 PM · Restricted Project
hliao created D64596: [AMDGPU] Skip calculating callee saved registers for entry function..
Thu, Jul 11, 2:10 PM · Restricted Project
hliao added a comment to D64557: Add llvm.loop.licm.disable metadata.

please update the doc on transformation metadata

Thu, Jul 11, 5:58 AM · Restricted Project

Wed, Jul 10

hliao accepted D64478: AMDGPU: Serialize mode from MachineFunctionInfo.

LGTM

Wed, Jul 10, 7:35 AM

Tue, Jul 9

hliao committed rG9cf71d10f826: [unittest] Add the missing bogus machine register info initialization. (authored by hliao).
[unittest] Add the missing bogus machine register info initialization.
Tue, Jul 9, 11:24 AM
hliao committed rL365529: [unittest] Add the missing bogus machine register info initialization..
[unittest] Add the missing bogus machine register info initialization.
Tue, Jul 9, 11:22 AM
hliao committed rG329c03204069: [unittest] Add bogus register info. (authored by hliao).
[unittest] Add bogus register info.
Tue, Jul 9, 10:20 AM
hliao committed rL365516: [unittest] Add bogus register info..
[unittest] Add bogus register info.
Tue, Jul 9, 10:18 AM
hliao closed D64421: [unittest] Add bogus register info..
Tue, Jul 9, 10:18 AM · Restricted Project
hliao added a comment to D64421: [unittest] Add bogus register info..

LGTM, although these should probably be the default implementations anyway

Tue, Jul 9, 10:18 AM · Restricted Project
hliao updated the summary of D64421: [unittest] Add bogus register info..
Tue, Jul 9, 9:03 AM · Restricted Project
hliao created D64421: [unittest] Add bogus register info..
Tue, Jul 9, 8:20 AM · Restricted Project

Mon, Jul 8

hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

any use before def is invalid MIR, right?

So the MIR is valid before phi elimination, and then becomes invalid after. Removing unreachable blocks earlier to avoid this happening is a workaround. It seems to me like we need to fix PHI elimination or avoid relying on the prolog instructions

Mon, Jul 8, 11:53 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

cf.end and related MBB prologue instructions should not take PHIs as input. Before LCSSA is turned on, we won't have that IR. After LCSSA, the only possible PHI input is the one from non-latch loop single exit. That PHI is unnecessary and should be removed early to assure that the later passes could relies on the fact they cf.end and etc. won't take PHI as input.

Mon, Jul 8, 11:20 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

the misplacement of def/use is not the fault of SILowerControlFlow but PHIEliminate. However, even PHIEliminate should not be blamed as cf.end is part of MBB prologue. cf.end should not take any input from PHI.

In O2 compilation, there won't be such issue as, in optimized RA, livevariable is used to eliminate PHI better. LiveVariables depends on unreachable-mbb-elimin, which remove the PHI to cf.end.

This isn't a property the pass should rely on. SILowerControlFlow should defend against unexpected iteration order and unreachable blocks

Mon, Jul 8, 11:11 AM · Restricted Project
hliao updated the diff for D64353: [AMDGPU] Run '' after isel to simplify PHIs..

revise test case

Mon, Jul 8, 11:11 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I think you should probably fix SILowerControlFlow

Mon, Jul 8, 11:05 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I'm still confused. When I try your testcase, I see an earlier iterator crash in SILowerControlFlow

Mon, Jul 8, 10:11 AM · Restricted Project
hliao added inline comments to D64353: [AMDGPU] Run '' after isel to simplify PHIs..
Mon, Jul 8, 9:58 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I don't follow how eliminating unreachable blocks fixes this.

In general expecting code placement with the block "prolog" instructions isn't reliable. I had fixed this in rL357634, except it was reverted

Mon, Jul 8, 9:56 AM · Restricted Project
hliao added a comment to D64353: [AMDGPU] Run '' after isel to simplify PHIs..

I don't follow how eliminating unreachable blocks fixes this.

In general expecting code placement with the block "prolog" instructions isn't reliable. I had fixed this in rL357634, except it was reverted

Mon, Jul 8, 9:56 AM · Restricted Project
hliao updated the diff for D64353: [AMDGPU] Run '' after isel to simplify PHIs..

revise commit message.

Mon, Jul 8, 9:50 AM · Restricted Project
hliao created D64353: [AMDGPU] Run '' after isel to simplify PHIs..
Mon, Jul 8, 9:44 AM · Restricted Project

Sat, Jul 6

hliao updated the diff for D64273: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.

revise the test function name

Sat, Jul 6, 4:24 AM · Restricted Project

Fri, Jul 5

hliao committed rG88b0d20edf67: Revert "[FileCheck] Simplify numeric variable interface" (authored by hliao).
Revert "[FileCheck] Simplify numeric variable interface"
Fri, Jul 5, 3:28 PM
hliao added a reverting change for rG096600a4b073: [FileCheck] Simplify numeric variable interface: rG88b0d20edf67: Revert "[FileCheck] Simplify numeric variable interface".
Fri, Jul 5, 3:27 PM
hliao committed rL365251: Revert "[FileCheck] Simplify numeric variable interface".
Revert "[FileCheck] Simplify numeric variable interface"
Fri, Jul 5, 3:23 PM
hliao created D64273: [AMDGPU] Add test case on crashing of `si-lower-sgpr-spills` pass.
Fri, Jul 5, 3:08 PM · Restricted Project
hliao committed rG8d6ea2d48c87: [CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used. (authored by hliao).
[CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used.
Fri, Jul 5, 1:26 PM
hliao committed rL365240: [CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used..
[CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used.
Fri, Jul 5, 1:26 PM
hliao closed D64261: [CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used..
Fri, Jul 5, 1:25 PM · Restricted Project
hliao created D64261: [CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used..
Fri, Jul 5, 12:21 PM · Restricted Project

Thu, Jul 4

hliao added a comment to D64144: [AMDGPU] Update NumUserSGPRs and NumSystemSGPRs in MIR parsing..

Test? I’m also note sure we get much value by tracking these here. I don’t think they are accurate for shaders

Thu, Jul 4, 11:30 AM · Restricted Project
hliao committed rG7a9ad430fec9: [AMDGPU] Correct the setting of `FlatScratchInit`. (authored by hliao).
[AMDGPU] Correct the setting of `FlatScratchInit`.
Thu, Jul 4, 6:31 AM
hliao committed rL365137: [AMDGPU] Correct the setting of `FlatScratchInit`..
[AMDGPU] Correct the setting of `FlatScratchInit`.
Thu, Jul 4, 6:29 AM
hliao closed D64143: [AMDGPU] Correct the setting of `FlatScratchInit`..
Thu, Jul 4, 6:29 AM · Restricted Project

Wed, Jul 3

hliao created D64145: [AMDGPU] Add the adjusted FP as a livein register..
Wed, Jul 3, 10:27 AM · Restricted Project
hliao added inline comments to D64143: [AMDGPU] Correct the setting of `FlatScratchInit`..
Wed, Jul 3, 10:24 AM · Restricted Project
hliao created D64144: [AMDGPU] Update NumUserSGPRs and NumSystemSGPRs in MIR parsing..
Wed, Jul 3, 10:24 AM · Restricted Project
hliao added a comment to D64143: [AMDGPU] Correct the setting of `FlatScratchInit`..

FlatScratchInit is set by checking whether there are any stack objects in the early stage of codegen. As we could load MIR in any stage, even after RA, it may set that flag incorrectly by counting spilling stack slot.

Wed, Jul 3, 10:24 AM · Restricted Project
hliao added a comment to D64144: [AMDGPU] Update NumUserSGPRs and NumSystemSGPRs in MIR parsing..

NumUserSGPRs and NumSystemSGPRs need updating during the parsing argument info.

Wed, Jul 3, 10:24 AM · Restricted Project
hliao created D64143: [AMDGPU] Correct the setting of `FlatScratchInit`..
Wed, Jul 3, 10:19 AM · Restricted Project

Tue, Jul 2

hliao committed rG80177ca5a9b0: [AMDGPU] Enable serializing of argument info. (authored by hliao).
[AMDGPU] Enable serializing of argument info.
Tue, Jul 2, 7:02 PM
hliao committed rL364995: [AMDGPU] Enable serializing of argument info..
[AMDGPU] Enable serializing of argument info.
Tue, Jul 2, 7:02 PM
hliao closed D64096: [AMDGPU] Enable serializing of argument info..
Tue, Jul 2, 7:01 PM · Restricted Project
hliao updated the diff for D64096: [AMDGPU] Enable serializing of argument info..

minor style fixing

Tue, Jul 2, 6:52 PM · Restricted Project
hliao updated the diff for D64096: [AMDGPU] Enable serializing of argument info..

patch is enhanced to remove 'isReg'

Tue, Jul 2, 6:40 PM · Restricted Project
hliao added inline comments to D64096: [AMDGPU] Enable serializing of argument info..
Tue, Jul 2, 1:50 PM · Restricted Project
hliao added inline comments to D64096: [AMDGPU] Enable serializing of argument info..
Tue, Jul 2, 1:13 PM · Restricted Project
hliao created D64096: [AMDGPU] Enable serializing of argument info..
Tue, Jul 2, 1:12 PM · Restricted Project

Thu, Jun 27

hliao committed rGc5486b23bc72: Correct the file path. NFC. (authored by hliao).
Correct the file path. NFC.
Thu, Jun 27, 12:07 PM
hliao committed rL364577: Correct the file path. NFC..
Correct the file path. NFC.
Thu, Jun 27, 12:06 PM
hliao committed rGa166b903d0ee: Fix lld build on Windows with MSVC due to C2461 (authored by hliao).
Fix lld build on Windows with MSVC due to C2461
Thu, Jun 27, 10:20 AM
hliao committed rL364567: Fix lld build on Windows with MSVC due to C2461.
Fix lld build on Windows with MSVC due to C2461
Thu, Jun 27, 10:19 AM

Wed, Jun 26

hliao committed rG68ea5fee21b7: Fix build in shared lib mode. (authored by hliao).
Fix build in shared lib mode.
Wed, Jun 26, 8:48 AM
hliao committed rL364440: Fix build in shared lib mode..
Fix build in shared lib mode.
Wed, Jun 26, 8:47 AM
hliao committed rG5c94dd76d779: Make CodeGen depend on ASTMatchers (authored by hliao).
Make CodeGen depend on ASTMatchers
Wed, Jun 26, 7:15 AM
hliao committed rL364428: Make CodeGen depend on ASTMatchers.
Make CodeGen depend on ASTMatchers
Wed, Jun 26, 7:14 AM

Tue, Jun 25

hliao committed rL364318: [AMDGPU] Null checking on TS to avoid crashing in clang tests..
[AMDGPU] Null checking on TS to avoid crashing in clang tests.
Tue, Jun 25, 7:11 AM
hliao committed rGf0a665afca70: [AMDGPU] Null checking on TS to avoid crashing in clang tests. (authored by hliao).
[AMDGPU] Null checking on TS to avoid crashing in clang tests.
Tue, Jun 25, 7:08 AM

Jun 18 2019

hliao committed rG4f7f70e26245: Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas (authored by hliao).
Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas
Jun 18 2019, 2:40 PM
hliao committed rL363743: Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas.
Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas
Jun 18 2019, 2:40 PM