Add support for intrinsic llvm.ppc.eieio

[anil9]

Summary

Add support for the intrinsic llvm.ppc.eieio to emit the instruction eieio.

[lei]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2287

This used to be under PowerPC Instructions used for assembler/disassembler only. Is this no longer true? You seem to have moved this into PPC32 Store Instructions section. What does this intrinsic do?

We generally don't move unrelated code around. Maybe keep this where it was and add your new def under PowerPC Assembler Instruction Aliases?

[anil9]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2287

We are exposing it as an intrinsic, so I think it is not just for assembler/disassembler only so should not be in the previous place anymore.

It is a form of barrier that acts on only load and stores related to data not instructions.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2284

Please set the has side effect bit to make it clear.

[anil9]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2284

The purpose of this patch is to expose this instruction using a built in function. You are correct that using the hasSideEffects bit will make it clear, but I checked that there are a lot of synchronization instructions without the hasSideEffects bit set, I think all of them should be handled together in a separate patch.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2286

I think this indenting is a bit off -- align the second line starting from the double quote under the 3 in the top line.

[anil9]

Addressed review comment. [NFC]

[nemanjai]

The code looks fine to me, but where is the test case?

[anil9]

Added test case.

[nemanjai]

LGTM.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<0>]>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
+  // eieio instruction
+  def int_ppc_eieio : Intrinsic<[],[],[]>;
 
   // Intrinsics used to generate ctr-based loops. These should only be
   // generated by the PowerPC backend!
   // The branch intrinsic is marked as NoDuplicate because loop rotation will
   // attempt to duplicate it forming loops where a block reachable from one
   // instance of it can contain another.
   def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>;
   def int_ppc_is_decremented_ctr_nonzero :

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 let isCodeGenOnly = 1 in {
   def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
                            "msync", IIC_LdStSync, []> {
     let L = 0;
   }
 }
 
+// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
+def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
+                                 "eieio", IIC_LdStLoad, []>;
+
 def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_eieio),  (EnforceIEIO)>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Arithmetic Instructions.
 //
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
                      "addi $rD, $rA, $imm", IIC_IntSimple,
def STSWI : XForm_base_r3xo_memOp<31, 725, (outs),
                                   "stswi $RT, $A, $B", IIC_LdStLoad, []>;
 
 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
                          "isync", IIC_SprISYNC, []>;
 
 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
                     "icbi $src", IIC_LdStICBI, []>;
 
-// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
-def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
-                           "eieio", IIC_LdStLoad, []>;
-
 def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
                          "wait $L", IIC_LdStLoad, []>;
 
 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
                          "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
 
 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
             "mtsr $SR, $RS", IIC_SprMTSR>;

llvm/test/CodeGen/PowerPC/eieio.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @eieio_test() {
+; CHECK-LABEL: @eieio_test
+; CHECK: eieio
+; CHECK-NEXT: blr
+
+entry:
+  tail call void @llvm.ppc.eieio()
+  ret void
+}
+
+declare void @llvm.ppc.eieio()