[ARM] Allocatable Global Register Variables for ARM

[anwel]

Summary

This patch combines two earlier patches aiming at providing the same support (https://reviews.llvm.org/D56003 for clang, https://reviews.llvm.org/D56005 for LLVM). It enables reservation of allocatable registers via command line options, which in turn allows them to be used as global named register variables. They will then not be used by the register allocator nor spilled to the stack.

More information is available in the original RFC: http://lists.llvm.org/pipermail/llvm-dev/2018-December/128706.html

Changes from the previous patches include:

• adding a constraint to specify -ffixed-rN if rN is used as named register variable.
• upgrading the frame-pointer warning to an error and throwing an error in LLVM, as well as clang.*

Additionally this patch now only supports r6-r11. r4 and r5 are excluded from this patch as r4 is used as hard-coded scratch register in various parts of the ARM backend. r4 also appears to be used as an input register for a Windows asm routine (__chkstk). Similarly, the ABI of the segmented stack prologue for Android and Linux seems to use r4 and r5 as input registers. A separate patch could follow to add the support for r4 and/or r5, such that the whole range of allocatable registers (r4-r11) is available.

As before it should be noted that this also changes the behaviour of the old -ffixed-r9 option. This option will now prevent the register from being spilled to the stack.

*This was originally a warning, but we don't seem to have the necessary information to determine frame-pointer usage in the given context. Any insight here would be welcome.

[SjoerdMeijer]

Bit of a drive-by comment, but I can't say I am big fan of all the string matching on the register names. Not sure if this is a fair comment, because I haven't looked closely at it yet, but could we use more the ARM::R[0-9] values more? Perhaps that's difficult from the Clang parts?

clang/lib/Basic/Targets/ARM.cpp

902

I was pointed at something similar myself recently, but if I am not mistaken then I think this is a use-after-free:

"+reserve-" + RegName.str()

this will allocate a temp std::string that SearchFeature points to, which then gets released, and SearchFeature is still pointing at it.

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll

16

nit: +m -> + m

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll

14

same nit

llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll

4

As all these tests (this file and the ones above) are the same, the "equivalent C source code" is the same, perhaps move all these cases into 1 file.

14

same nit here

[chill]

TBH, I quite dislike the creeping abuse of SubtargetFeatures as code generation options.

cf. Target.td:1477

//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//

IMHO, since reserved registes are per-function, this strongly suggests implementation as function attribute(s), rather than subtarget features (also for the pre-existing r9).
It also opens the path towards possible future __attribute__.

clang/include/clang/Basic/TargetInfo.h

944

Parameter name can be omitted if unused; that would remove a potential warning.

clang/lib/Basic/Targets/ARM.cpp

884

Perhaps you can use here RegName == "r6" or string switch ?

890

HasSizeMismatch is not set along all possible paths.

895

s/enable/reserve/ ?

899

Likewise ?

901–902

These variables can be const.

903–907

This explicit loop can be written like:

return llvm::any_of(getTargetOpts().Features(),
                   [&](auto &P) { return P == SearchFeature; });

llvm/lib/Target/ARM/ARMSubtarget.h

236

The usual designation for these registers is "GPR". Suggestion either ReservedGPRegisters or just ReservedRegisters,
here and elsewhere.

[chill]

clang/lib/Basic/Targets/ARM.cpp

902

Any temporaries would be destructed at the end of the full expression. By that time, the SearchString would be constructed and stand on its own.

[SjoerdMeijer]

clang/lib/Basic/Targets/ARM.cpp

902

Ah yes, true. This is a std::string, not stringref as in my case.

[carwil]

IMHO, since reserved registes are per-function, this strongly suggests implementation as function attribute(s), rather than subtarget features (also for the pre-existing r9).

What do you mean reserved registers are per-function? That sounds like you're describing local register variables, which I don't believe Clang has any support for (and there aren't a great deal of use-cases for anyway).
We're specifically talking about global usage here.

[anwel]

Applied some minor changes suggested in the comments, including renaming the array of reserved registers.

[chill]

In D68862#1708079, @carwil wrote:

IMHO, since reserved registes are per-function, this strongly suggests implementation as function attribute(s), rather than subtarget features (also for the pre-existing r9).

What do you mean reserved registers are per-function? That sounds like you're describing local register variables, which I don't believe Clang has any support for (and there aren't a great deal of use-cases for anyway).
We're specifically talking about global usage here.

I mean that the set is dynamically computed and depends on the specific function: cf. https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp#L184
as opposed to, say, depend only on target/subtarget/abi.

[carwil]

In D68862#1708132, @chill wrote:

In D68862#1708079, @carwil wrote:

IMHO, since reserved registes are per-function, this strongly suggests implementation as function attribute(s), rather than subtarget features (also for the pre-existing r9).

What do you mean reserved registers are per-function? That sounds like you're describing local register variables, which I don't believe Clang has any support for (and there aren't a great deal of use-cases for anyway).
We're specifically talking about global usage here.

I mean that the set is dynamically computed and depends on the specific function: cf. https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp#L184
as opposed to, say, depend only on target/subtarget/abi.

Ah, I see. That's a fair comment. AArch64 also achieves it's -reserve-xN options via subtarget features (despite function context), I think that's where the inspiration/suggestion for doing it this way in the ARM backend came from.

[anwel]

Rebase and make some variables const

clang/lib/Basic/Targets/ARM.cpp

903–907

I see your point, but using a for loop seems to better match the style of the code.

llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll

4

I see your point, but I'd still prefer to leave them as they are because in my opinion having the test cases separated into individual files it's much easier to grasp what they are doing.

[carwil]

Just want to double check with @efriedma, before we except this. I believe this patch now catches all the points you made on https://reviews.llvm.org/D56005. Anything we've missed?

[anwel]

Rebase on current llvm-project master

[anwel]

Change clang's error message when trying to use the target's frame pointer as GRV to sound more like an error then a warning.

[carwil]

I think there's been plenty of time for comments here. LGTM.

[efriedma]

Approval is not ever a time-based process; someone appropriate actually has to do the work of reviewing the patch. If a patch doesn't get reviewed, you "ping" it a couple times, to note that you're waiting for a review. If it still isn't reviewed at that point, and you're not sure what to do, send an email to cfe-dev.

In this case, it was on me to review; I apologize for not looking at this earlier.

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

438

I'm a little concerned about this... what happens if r6 is reserved, and the code uses a construct which LLVM implements using a base pointer? For example:

void f(void a(char*, char*), int n) {
  char r[n];
  char r2[16] __attribute((aligned(16)));
  a(r, r2);
}

(There are potentially other ways to implement this construct. But I'm pretty sure using a base pointer is the only method which is currently implemented.)

[carwil]

Hi @efriedma, thanks your comments. You're right, that was hasty of me. Apologies for that, it won't happen again.

RE: R6
Case in point: you're right. We're definitely not handling this correctly. I'll revert the patch, or ask @anwel too. Once we have a fix, we'll raise another review.

[carwil]

Reverted.

clang/docs/ClangCommandLineReference.rst

 Wavefront size 64 is used if enabled and wavefront size 32 if disabled (AMDGPU only)
 
 .. option:: -mxnack, -mno-xnack
 
 Enable XNACK (AMDGPU only)
 
 ARM
 ---
+
+.. option:: -ffixed-r6
+
+Reserve the r6 register (ARM only)
+
+.. option:: -ffixed-r7
+
+Reserve the r7 register (ARM only)
+
+.. option:: -ffixed-r8
+
+Reserve the r8 register (ARM only)
+
 .. option:: -ffixed-r9
 
 Reserve the r9 register (ARM only)
 
+.. option:: -ffixed-r10
+
+Reserve the r10 register (ARM only)
+
+.. option:: -ffixed-r11
+
+Reserve the r11 register (ARM only)
+
 .. option:: -mexecute-only, -mno-execute-only, -mpure-code
 
 Disallow generation of data access to code sections (ARM only)
 
 .. option:: -mno-movt
 
 Disallow use of movt/movw pairs (ARM only)
 

clang/include/clang/Basic/DiagnosticDriverKinds.td

 def warn_drv_msp430_hwmult_mismatch : Warning<"the given MCU supports %0 "
   "hardware multiply, but -mhwmult is set to %1.">,
    InGroup<InvalidCommandLineArgument>;
 def warn_drv_msp430_hwmult_no_device : Warning<"no MCU device specified, but "
   "'-mhwmult' is set to 'auto', assuming no hardware multiply. Use -mmcu to "
   "specify a MSP430 device, or -mhwmult to set hardware multiply type "
   "explicitly.">, InGroup<InvalidCommandLineArgument>;
 
+// Frame pointer reservation.
+def err_reserved_frame_pointer : Error<
+  "'%0' has been specified but '%1' may still be used as a frame pointer">;
+
 def warn_drv_libstdcxx_not_found : Warning<
   "include path for libstdc++ headers not found; pass '-stdlib=libc++' on the "
   "command line to use the libc++ standard library instead">,
   InGroup<DiagGroup<"stdlibcxx-not-found">>;
 
 def err_drv_cannot_mix_options : Error<"cannot specify '%1' along with '%0'">;
 }

clang/include/clang/Basic/DiagnosticGroups.td

 def NoDeref : DiagGroup<"noderef">;
 
 // A group for cross translation unit static analysis related warnings.
 def CrossTU : DiagGroup<"ctu">;
 
 def CTADMaybeUnsupported : DiagGroup<"ctad-maybe-unsupported">;
 
 def FortifySource : DiagGroup<"fortify-source">;
+
+// Register reservation.
+def FixedRegs : DiagGroup<"fixed-registers">;

clang/include/clang/Basic/DiagnosticSemaKinds.td

def err_asm_tying_incompatible_types : Error<
     "unsupported inline asm: input with type "
     "%diff{$ matching output with type $|}0,1">;
   def err_asm_unexpected_constraint_alternatives : Error<
     "asm constraint has an unexpected number of alternatives: %0 vs %1">;
   def err_asm_incomplete_type : Error<"asm operand has incomplete type %0">;
   def err_asm_unknown_register_name : Error<"unknown register name '%0' in asm">;
   def err_asm_invalid_global_var_reg : Error<"register '%0' unsuitable for "
     "global register variables on this target">;
+  def err_asm_missing_fixed_reg_opt : Error<"-ffixed-%0 is required for "
+    "global named register variable declaration">;
   def err_asm_register_size_mismatch : Error<"size of register '%0' does not "
     "match variable size">;
   def err_asm_bad_register_type : Error<"bad type for named register variable">;
   def err_asm_invalid_input_size : Error<
     "invalid input size for constraint '%0'">;
   def err_asm_invalid_output_size : Error<
     "invalid output size for constraint '%0'">;
   def err_invalid_asm_cast_lvalue : Error<

clang/include/clang/Basic/TargetInfo.h

public:
   /// variable size passed in RegSize.
   virtual bool validateGlobalRegisterVariable(StringRef RegName,
                                               unsigned RegSize,
                                               bool &HasSizeMismatch) const {
     HasSizeMismatch = false;
     return true;
   }
 
+  /// Check if the register is reserved globally
+  ///
+  /// This function returns true if the register passed in RegName is reserved
+  /// using the corresponding -ffixed-RegName option.
+  virtual bool isRegisterReservedGlobally(StringRef) const { return true; }
+
   // validateOutputConstraint, validateInputConstraint - Checks that
   // a constraint is valid and provides information about it.
   // FIXME: These should return a real error instead of just true/false.
   bool validateOutputConstraint(ConstraintInfo &Info) const;
   bool validateInputConstraint(MutableArrayRef<ConstraintInfo> OutputConstraints,
                                ConstraintInfo &info) const;
 
   virtual bool validateOutputSize(StringRef /*Constraint*/,

clang/include/clang/Driver/Options.td

 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;
 def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Disallow generation of deprecated IT blocks for ARMv8. It is on by default for ARMv8 Thumb mode.">;
 def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Allow generation of deprecated IT blocks for ARMv8. It is off by default for ARMv8 Thumb mode">;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
-def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
-  HelpText<"Reserve the r9 register (ARM only)">;
+foreach i = {6-11} in
+  def ffixed_r#i : Flag<["-"], "ffixed-r"#i>, Group<m_arm_Features_Group>,
+    HelpText<"Reserve the r"#i#" register (ARM only)">;
 def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of movt/movw pairs (ARM only)">;
 def mcrc : Flag<["-"], "mcrc">, Group<m_Group>,
   HelpText<"Allow use of CRC instructions (ARM/Mips only)">;
 def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of CRC instructions (ARM only)">;
 def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_Group>,
   HelpText<"Disallow converting instructions with negative immediates to their negation or inversion.">;

clang/lib/Basic/Targets/ARM.h

public:
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   bool isCLZForZeroUndef() const override;
   BuiltinVaListKind getBuiltinVaListKind() const override;
 
   ArrayRef<const char *> getGCCRegNames() const override;
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
+  bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
+                                      bool &HasSizeMismatch) const override;
+  bool isRegisterReservedGlobally(StringRef RegName) const override;
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
   std::string convertConstraint(const char *&Constraint) const override;
   bool
   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
                              std::string &SuggestedModifier) const override;
   const char *getClobbers() const override;
 

clang/lib/Basic/Targets/ARM.cpp

const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
     // The S, D and Q registers overlap, but aren't really aliases; we
     // don't want to substitute one of these for a different-sized one.
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool ARMTargetInfo::validateGlobalRegisterVariable(
+    StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {
+  bool isValid = llvm::StringSwitch<bool>(RegName)
+                     .Case("r6", true)
+                     .Case("r7", true)
+                     .Case("r8", true)
+                     .Case("r9", true)
+                     .Case("r10", true)
+                     .Case("r11", true)
+                     .Case("sp", true)
+                     .Default(false);
+  HasSizeMismatch = false;
+  return isValid;
+}
+
+bool ARMTargetInfo::isRegisterReservedGlobally(StringRef RegName) const {
+  // The "sp" register does not have a -ffixed-sp option,
+  // so reserve it unconditionally.
+  if (RegName.equals("sp"))
+    return true;
+
+  // reserve rN (N:6-11) registers only if the corresponding
+  // +reserve-rN feature is found
+  const std::vector<std::string> &Features = getTargetOpts().Features;
+  const std::string SearchFeature = "+reserve-" + RegName.str();
+  for (const std::string &Feature : Features) {
+    if (Feature.compare(SearchFeature) == 0)
+      return true;
+  }
+  return false;
+}
+
 bool ARMTargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   switch (*Name) {
   default:
     break;
   case 'l': // r0-r7 if thumb, r0-r15 if ARM
     Info.setAllowsRegister();
     return true;

clang/lib/Driver/ToolChains/Arch/ARM.cpp

if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
         Features.push_back("+strict-align");
     } else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
       if (VersionNum < 7)
         Features.push_back("+strict-align");
     } else
       Features.push_back("+strict-align");
   }
 
-  // llvm does not support reserving registers in general. There is support
-  // for reserving r9 on ARM though (defined as a platform-specific register
-  // in ARM EABI).
-  if (Args.hasArg(options::OPT_ffixed_r9))
-    Features.push_back("+reserve-r9");
+  // Do not allow r9 reservation with -frwpi.
+  if (Args.hasArg(options::OPT_ffixed_r9) && Args.hasArg(options::OPT_frwpi)) {
+    Arg *A = Args.getLastArg(options::OPT_ffixed_r9);
+    Arg *B = Args.getLastArg(options::OPT_frwpi);
+    D.Diag(diag::err_opt_not_valid_with_opt)
+        << A->getAsString(Args) << B->getAsString(Args);
+  }
+
+  // The compiler can still use a FP in certain circumstances,
+  // even when frame pointer elimination is enabled. Thus we should
+  // not allow to reserve a target's FP register.
+  const llvm::opt::OptSpecifier RestrictFPOpt =
+      (Triple.isOSDarwin() || (!Triple.isOSWindows() && Triple.isThumb()))
+          ? options::OPT_ffixed_r7
+          : options::OPT_ffixed_r11;
+  if (Args.hasArg(RestrictFPOpt)) {
+    const std::string OptStr =
+        Args.getLastArg(RestrictFPOpt)->getAsString(Args);
+    const unsigned int SubStrIndex = strlen("ffixed-r");
+    D.Diag(diag::err_reserved_frame_pointer)
+        << OptStr << OptStr.substr(SubStrIndex);
+  }
+
+// Reservation of general purpose registers.
+#define HANDLE_FFIXED_R(n) \
+  if (Args.hasArg(options::OPT_ffixed_r##n)) \
+    Features.push_back("+reserve-r" #n)
+  HANDLE_FFIXED_R(6);
+  HANDLE_FFIXED_R(7);
+  HANDLE_FFIXED_R(8);
+  HANDLE_FFIXED_R(9);
+  HANDLE_FFIXED_R(10);
+  HANDLE_FFIXED_R(11);
 
   // The kext linker doesn't know how to deal with movw/movt.
   if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
     Features.push_back("+no-movt");
 
   if (Args.hasArg(options::OPT_mno_neg_immediates))
     Features.push_back("+no-neg-immediates");
 }

clang/lib/Sema/SemaDecl.cpp

if (S->getFnParent() != nullptr) {
         if (!TI.isValidGCCRegisterName(Label))
           Diag(E->getExprLoc(), diag::err_asm_unknown_register_name) << Label;
         else if (!TI.validateGlobalRegisterVariable(Label,
                                                     Context.getTypeSize(R),
                                                     HasSizeMismatch))
           Diag(E->getExprLoc(), diag::err_asm_invalid_global_var_reg) << Label;
         else if (HasSizeMismatch)
           Diag(E->getExprLoc(), diag::err_asm_register_size_mismatch) << Label;
+        else if (!TI.isRegisterReservedGlobally(Label))
+          Diag(E->getExprLoc(), diag::err_asm_missing_fixed_reg_opt) << Label;
       }
 
       if (!R->isIntegralType(Context) && !R->isPointerType()) {
         Diag(D.getBeginLoc(), diag::err_asm_bad_register_type);
         NewVD->setInvalidDecl(true);
       }
     }
 

clang/test/Driver/arm-reserved-reg-options.c

+// ## FP ARM + Thumb
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R11 %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -mthumb -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -mthumb -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// ## FP Darwin (R7)
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R7 %s
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// ## FP Windows (R11)
+// RUN: %clang -target armv7-windows -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-ERROR-R11 %s
+// RUN: %clang -target armv7-windows -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-ERROR %s
+
+// ## FRWPI (R9)
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-CONFLICT %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s
+
+// CHECK-ERROR-R11: error: '-ffixed-r11' has been specified but 'r11' may still be used as a frame pointer
+// CHECK-ERROR-R7: error: '-ffixed-r7' has been specified but 'r7' may still be used as a frame pointer
+// CHECK-NO-ERROR-NOT: may still be used as a frame pointer
+
+// CHECK-RESERVED-FRWPI-CONFLICT: option '-ffixed-r9' cannot be specified with '-frwpi'
+// CHECK-RESERVED-FRWPI-VALID-NOT: option '-ffixed-r9' cannot be specified with '-frwpi'

clang/test/Sema/arm-global-regs.c

+// RUN: %clang_cc1 -ffreestanding -fsyntax-only -target-feature +reserve-r9  -verify -triple arm-arm-none-eabi %s
+
+// Check a small subset of valid and invalid global register variable declarations.
+// Also check that for global register variables without -ffixed-reg options it throws an error.
+
+register unsigned arm_r3 __asm("r3"); //expected-error {{register 'r3' unsuitable for global register variables on this target}}
+
+register unsigned arm_r12 __asm("r12"); //expected-error {{register 'r12' unsuitable for global register variables on this target}}
+
+register unsigned arm_r5 __asm("r5"); //expected-error {{register 'r5' unsuitable for global register variables on this target}}
+
+register unsigned arm_r9 __asm("r9");
+
+register unsigned arm_r6 __asm("r6"); //expected-error {{-ffixed-r6 is required for global named register variable declaration}}
+
+register unsigned arm_r7 __asm("r7"); //expected-error {{-ffixed-r7 is required for global named register variable declaration}}
+
+register unsigned *parm_r7 __asm("r7"); //expected-error {{-ffixed-r7 is required for global named register variable declaration}}
+
+register unsigned arm_sp __asm("sp");

llvm/lib/Target/ARM/ARM.td

def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
                                              "Generate calls via indirect call "
                                              "instructions">;
 
 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
                                              "GenExecuteOnly", "true",
                                              "Enable the generation of "
                                              "execute only code.">;
 
-def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
-                                             "Reserve R9, making it unavailable"
-                                             " as GPR">;
+foreach i = {6-11} in
+    def FeatureReserveR#i : SubtargetFeature<"reserve-r"#i,
+                                             "ReservedGPRegisters["#i#"]", "true",
+                                             "Reserve R"#i#", making it "
+                                             "unavailable as a GPR">;
 
 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
                                              "Don't use movt/movw pairs for "
                                              "32-bit imms">;
 
 def FeatureNoNegativeImmediates
                           : SubtargetFeature<"no-neg-immediates",
                                              "NegativeImmediates", "false",

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

if (const Module *SourceModule = MMI->getModule()) {
       }
     }
   }
 
   // We currently do not support using R9 as the TLS pointer.
   if (STI.isRWPI())
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsSB);
-  else if (STI.isR9Reserved())
+  else if (STI.isGPRegisterReserved(9))
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9Reserved);
   else
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsGPR);
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, ARM::SP);
   markSuperRegs(Reserved, ARM::PC);
   markSuperRegs(Reserved, ARM::FPSCR);
   markSuperRegs(Reserved, ARM::APSR_NZCV);
   if (TFI->hasFP(MF) || STI.isTargetDarwin())
     markSuperRegs(Reserved, getFramePointerReg(STI));
   if (hasBasePointer(MF))
     markSuperRegs(Reserved, BasePtr);
-  // Some targets reserve R9.
-  if (STI.isR9Reserved())
-    markSuperRegs(Reserved, ARM::R9);
+  for (size_t R = 0; R < ARM::GPRRegClass.getNumRegs(); ++R) {
+    if (STI.isGPRegisterReserved(R)) {
+      markSuperRegs(Reserved, ARM::R0 + R);
+    }
+  }
   // Reserve D16-D31 if the subtarget doesn't support them.
   if (!STI.hasD32()) {
     static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
     for (unsigned R = 0; R < 16; ++R)
       markSuperRegs(Reserved, ARM::D16 + R);
   }
   const TargetRegisterClass &RC = ARM::GPRPairRegClass;
   for (unsigned Reg : RC)
case ARM::tGPRRegClassID: {
     // ScheduleDAGRRList.
     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
                  ? TFI->hasFP(MF) : true;
     return 5 - HasFP;
   }
   case ARM::GPRRegClassID: {
     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
                  ? TFI->hasFP(MF) : true;
-    return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
+    return 10 - HasFP - STI.getNumGPRegistersReserved();
   }
   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
   case ARM::DPRRegClassID:
     return 32 - 10;
   }
 }
 
 // Get the other register in a GPRPair.
if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
     }
   }
 }
 
 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   const ARMFrameLowering *TFI = getFrameLowering(MF);
+  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
+
+  // Disable base pointer R6 if -ffixed-r6 is used.
+  if (STI.isGPRegisterReserved(BasePtr - ARM::R0))
+    return false;
 
   // If we have stack realignment and VLAs, we have no pointer to use to
   // access the stack. If we have stack realignment, and a large call frame,
   // we have no place to allocate the emergency spill slot.
   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
     return true;
 
   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))
     return true;
   return false;
 }
 
 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   const MachineRegisterInfo *MRI = &MF.getRegInfo();
   const ARMFrameLowering *TFI = getFrameLowering(MF);
+  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
   // We can't realign the stack if:
   // 1. Dynamic stack realignment is explicitly disabled,
   // 2. There are VLAs in the function and the base pointer is disabled.
   if (!TargetRegisterInfo::canRealignStack(MF))
     return false;
   // Stack realignment requires a frame pointer.  If we already started
   // register allocation with frame pointer elimination, it is too late now.
   if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
     return false;
+  // Disable base pointer R6 if -ffixed-r6 is used.
+  if (STI.isGPRegisterReserved(BasePtr - ARM::R0))
+    return false;
   // We may also need a base pointer if there are dynamic allocas or stack
   // pointer adjustments around calls.
   if (TFI->hasReservedCallFrame(MF))
     return true;
   // A base pointer is required and allowed.  Check that it isn't too late to
   // reserve it.
   return MRI->canReserveReg(BasePtr);
 }

llvm/lib/Target/ARM/ARMFrameLowering.cpp

void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
   if (RegInfo->hasBasePointer(MF))
     SavedRegs.set(RegInfo->getBaseRegister());
 
   // Don't spill FP if the frame can be eliminated. This is determined
   // by scanning the callee-save registers to see if any is modified.
   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
+    if (STI.isRWPI() && Reg == ARM::R9) {
+      // Paranoid check for use of R9 with RWPI. Clobbering R9 with -frwpi will
+      // emit warnings about undefined behaviour but maybe theres's a valid use
+      // case so on that basis allow it to be pushed/popped in the
+      // prologue/epilogue.
+    } else if (Reg > ARM::R0 && ARM::GPRRegClass.contains(Reg) &&
+               STI.isGPRegisterReserved(Reg - ARM::R0)) {
+      LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << " has been reserved and"
+                        << " should not be allocatable"
+                        << " or spillable.\n");
+      SavedRegs.reset(Reg);
+      continue;
+    }
     bool Spilled = false;
     if (SavedRegs.test(Reg)) {
       Spilled = true;
       CanEliminateFrame = false;
     }
 
     if (!ARM::GPRRegClass.contains(Reg)) {
       if (Spilled) {
if (AFI->isThumb1OnlyFunction()) {
       // r4-r6 can be used in the prologue if they are pushed by the first push
       // instruction.
       for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
         if (SavedRegs.test(Reg)) {
           --RegDeficit;
           LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
                             << " is saved low register, RegDeficit = "
                             << RegDeficit << "\n");
-        } else {
+        } else if (!STI.isGPRegisterReserved(Reg - ARM::R0)) {
           AvailableRegs.push_back(Reg);
           LLVM_DEBUG(
               dbgs()
               << printReg(Reg, TRI)
               << " is non-saved low register, adding to AvailableRegs\n");
         }
       }
 
       // r7 can be used if it is not being used as the frame pointer.
       if (!HasFP) {
         if (SavedRegs.test(ARM::R7)) {
           --RegDeficit;
           LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
                             << RegDeficit << "\n");
-        } else {
+        } else if (!STI.isGPRegisterReserved(7)) {
           AvailableRegs.push_back(ARM::R7);
           LLVM_DEBUG(
               dbgs()
               << "%r7 is non-saved low register, adding to AvailableRegs\n");
         }
       }
 
       // Each of r8-r11 needs to be copied to a low register, then pushed.

llvm/lib/Target/ARM/ARMISelLowering.cpp

SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
   return FrameAddr;
 }
 
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
                                               const MachineFunction &MF) const {
   Register Reg = StringSwitch<unsigned>(RegName)
-                       .Case("sp", ARM::SP)
-                       .Default(0);
-  if (Reg)
+                     .Case("r6", ARM::R6)
+                     .Case("r7", ARM::R7)
+                     .Case("r8", ARM::R8)
+                     .Case("r9", ARM::R9)
+                     .Case("r10", ARM::R10)
+                     .Case("r11", ARM::R11)
+                     .Default(ARM::NoRegister);
+  if (Reg != ARM::NoRegister)
     return Reg;
   report_fatal_error(Twine("Invalid register name \""
                               + StringRef(RegName)  + "\"."));
 }
 
 // Result is 64 bit value so split into two 32 bit values and return as a
 // pair of values.
 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,

llvm/lib/Target/ARM/ARMSubtarget.h

protected:
   bool UseAA = false;
 
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
   /// NoARM - True if subtarget does not support ARM mode execution.
   bool NoARM = false;
 
-  /// ReserveR9 - True if R9 is not available as a general purpose register.
-  bool ReserveR9 = false;
+  // ReservedGPRegisters[i] - R#i is not available as a general purpose register
+  BitVector ReservedGPRegisters;
 
   /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
   /// 32-bit imms (including global addresses).
   bool NoMovt = false;
 
   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
   /// must be able to synthesize call stubs for interworking between ARM and
   /// Thumb.
public:
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
   bool isThumb2() const { return InThumbMode && HasThumb2; }
   bool hasThumb2() const { return HasThumb2; }
   bool isMClass() const { return ARMProcClass == MClass; }
   bool isRClass() const { return ARMProcClass == RClass; }
   bool isAClass() const { return ARMProcClass == AClass; }
   bool isReadTPHard() const { return ReadTPHard; }
 
-  bool isR9Reserved() const {
-    return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
+  bool isGPRegisterReserved(size_t i) const { return ReservedGPRegisters[i]; }
+  unsigned getNumGPRegistersReserved() const {
+    return ReservedGPRegisters.count();
   }
 
   bool useR7AsFramePointer() const {
     return isTargetDarwin() || (!isTargetWindows() && isThumb());
   }
 
   /// Returns true if the frame setup is split into two separate pushes (first
   /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent

llvm/lib/Target/ARM/ARMSubtarget.cpp

ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
   return new ARMFrameLowering(STI);
 }
 
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle,
                            bool MinSize)
     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
-      CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
-      TargetTriple(TT), Options(TM.Options), TM(TM),
+      ReservedGPRegisters(ARM::GPRRegClass.getNumRegs()), CPUString(CPU),
+      OptMinSize(MinSize), IsLittle(IsLittle), TargetTriple(TT),
+      Options(TM.Options), TM(TM),
       FrameLowering(initializeFrameLowering(CPU, FS)),
       // At this point initializeSubtargetDependencies has been called so
       // we can query directly.
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   }
 
   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
   const FeatureBitset &Bits = getFeatureBits();
   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
       (Options.UnsafeFPMath || isTargetDarwin()))
     UseNEONForSinglePrecisionFP = true;
 
-  if (isRWPI())
-    ReserveR9 = true;
+  if (isRWPI() || (isTargetMachO() && !HasV6Ops))
+    ReservedGPRegisters.set(9);
+
+  // Throw an error when trying to reserve a target's FP register. It may
+  // be used by the compiler even when frame pointer elimination is enabled.
+  // FIXME: Throw this error if -frame-pointer=none is not set; otherwise
+  //        only emit a warning.
+  const int restFP = (useR7AsFramePointer()) ? 7 : 11;
+  if (isGPRegisterReserved(restFP))
+    report_fatal_error(
+        "Register r" + std::to_string(restFP) +
+        " has been specified but is used as a frame pointer on this target.");
 
   // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
   if (MVEVectorCostFactor == 0)
     MVEVectorCostFactor = 2;
 
   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
   switch (ARMProcFamily) {
   case Others:

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

const FeatureBitset InlineFeatureWhitelist = {
       ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
       ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
       ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
       ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
       ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
       ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
       ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
       ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
-      ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
+      ARM::FeatureExecuteOnly, ARM::FeatureReserveR6, ARM::FeatureReserveR7,
+      ARM::FeatureReserveR8, ARM::FeatureReserveR9, ARM::FeatureReserveR10,
+      ARM::FeatureReserveR11, ARM::FeatureNoMovt,
       ARM::FeatureNoNegativeImmediates
   };
 
   const ARMSubtarget *getST() const { return ST; }
   const ARMTargetLowering *getTLI() const { return TLI; }
 
 public:
   explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)

llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll

+; Using VLAs(Variable Length Arrays) in a function will use R6 to keep track
+; of the stack frame, and also spill/restore R6 to the stack.
+; This tests that using -ffixed-r6 (-mattr=+reserve-r6) will stop R6
+; being used and also stop it being spilled/restored to the stack.
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi  | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-R6
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi -mattr=+reserve-r6  | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-NO-R6
+
+define void @f() #0 {
+entry:
+  %i = alloca i32, align 4
+  store i32 0, i32* %i, align 4
+
+  %saved_stack = alloca i8*, align 4
+  %0 = call i8* @llvm.stacksave()
+  store i8* %0, i8** %saved_stack, align 4
+
+  %__vla_expr0 = alloca i32, align 4
+  %1 = load i32, i32* %i, align 4
+  %vla = alloca double, i32 %1, align 8
+  store i32 %1, i32* %__vla_expr0, align 4
+
+  %2 = load i8*, i8** %saved_stack, align 4
+  call void @llvm.stackrestore(i8* %2)
+
+  ret void
+}
+
+declare i8* @llvm.stacksave() #1
+declare void @llvm.stackrestore(i8* %ptr) #1
+
+attributes #0 = { noinline nounwind "stackrealign" }
+attributes #1 = { nounwind }
+
+; CHECK-STATIC: push {r4,
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: lr}
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: pop {r4,
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: pc}
+

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll

+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; register unsigned r6 asm("r6");
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     r6 = 10;
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+declare void @llvm.write_register.i32(metadata, i32) nounwind
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+; CHECK: {{.*}}mov{{.*}}r6,{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  call void @llvm.write_register.i32(metadata !0, i32 10)
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+  ret void
+}
+
+!llvm.named.register.r6 = !{!0}
+!0 = !{!"r6"}
+

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll

+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r6,{{.*}}}
+}
+

llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll

+; RUN: llc < %s -mtriple=arm-linux-gnueabi  -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK: push {{{.*}}r4, r5{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK: {{.*}}r5{{.*}}
+
+; CHECK: pop {{{.*}}r4, r5{{.*}}}
+  ret void
+}
+

llvm/test/CodeGen/Thumb/callee_save_reserved.ll

+; RUN: llc < %s -mtriple=thumbv6m-none-eabi -verify-machineinstrs -frame-pointer=none -mattr=+reserve-r6,+reserve-r8 \
+; RUN:     -asm-verbose=false | FileCheck --check-prefix=CHECK-INVALID %s
+
+; Reserved low registers should not be used to correct reg deficit.
+define <4 x i32> @four_high_four_return_reserved() {
+entry:
+  ; CHECK-INVALID-NOT: r{{6|8}}
+  tail call void asm sideeffect "", "~{r8},~{r9}"()
+  %vecinit = insertelement <4 x i32> undef, i32 1, i32 0
+  %vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
+  %vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
+  %vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
+  ret <4 x i32> %vecinit13
+}
+

llvm/test/Feature/reserve_global_reg.ll

+; RUN: not llc < %s -mtriple=thumbv7-apple-darwin -mattr=+reserve-r7 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP7 %s
+; RUN: not llc < %s -mtriple=armv7-windows-msvc -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11 %s
+; RUN: not llc < %s -mtriple=thumbv7-windows -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11-2 %s
+
+; int test(int a, int b, int c) {
+;   return a + b + c;
+; }
+
+; Function Attrs: noinline nounwind optnone
+define hidden i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  %2 = load i32, i32* %c.addr, align 4
+  %add1 = add nsw i32 %add, %2
+  ret i32 %add1
+}
+
+; CHECK-RESERVE-FP7: Register r7 has been specified but is used as a frame pointer on this target.
+; CHECK-RESERVE-FP11: Register r11 has been specified but is used as a frame pointer on this target.
+; CHECK-RESERVE-FP11-2: Register r11 has been specified but is used as a frame pointer on this target.
+