[X86] add mayRaiseFPException flag and FPCW registers for X87 instructions

[LiuChen3]

Summary

This patch adds flag "mayRaiseFPException" , FPCW and FPSW for X87 instructions which could raise
float exception.

[RKSimon]

Test cases?

llvm/lib/Target/X86/X86InstrFPStack.td

703

Why did you change this? FFREE/FFREEP leave FPSW in an undefined state

[LiuChen3]

llvm/lib/Target/X86/X86InstrFPStack.td

703

Thanks for your review. I have added 'let Defs = [FPSW]' in class FPI.

[LiuChen3]

Add testcase to verify if x87 instructions use/def fpcw and fpcw registers.

[LiuChen3]

The Diff 226855 has some problems. This one adds testcase to verify if x87 instructions use/def fpcw and fpcw registers.

[LiuChen3]

I am sorry I updated two wrong versions. The Diff 226862 is right version.

[craig.topper]

llvm/lib/Target/X86/X86InstrFPStack.td

706

FNINIT also defs FPCW as far as I can tell. It reinitializes the entire X87 FPU.

714

I don't think this instruction updates FPSW it appears to be a mistake in the Intel SDM, but since we never generate it it probably doesn't matter.

[craig.topper]

commandeering so I can fix the FNINIT issue. And put FPCW/FPSW in consistent order in the Uses/Defs so we don't end up with two different Implicit defs lists in X86GenInstrInfo.inc

[craig.topper]

Fix FNINIT Defs. Put FPSW/FPCW in consistent order when both are used or defed.

[craig.topper]

LGTM

[thakis]

This broke CodeGen/ms-inline-asm.c' everywhere. Can you please revert?

[thakis]

Reverted in a5bf48b84c38a180cf64ef90a46988adea2de78e

[LiuChen3]

This patch fix the broken test: CodeGen/ms-inline-asm.c.

[craig.topper]

LGTM

[RKSimon]

@LiuChen3 @craig.topper This has broken EXPENSIVE_CHECKS builds, please can you take a look? http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-ubuntu/builds/184/

llvm/lib/Target/X86/X86InstrFPStack.td

 let mayLoad = 1 in
 def _FI16m  : FPI<0xDE, fp, (outs), (ins i16mem:$src),
                   !strconcat("fi", asmstring, "{s}\t$src")>;
 let mayLoad = 1 in
 def _FI32m  : FPI<0xDA, fp, (outs), (ins i32mem:$src),
                   !strconcat("fi", asmstring, "{l}\t$src")>;
 }
 
-let Defs = [FPSW], Uses = [FPCW] in {
+let Uses = [FPCW], mayRaiseFPException = 1 in {
 // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
 // resources.
 let hasNoSchedulingInfo = 1 in {
 defm ADD : FPBinary_rr<fadd>;
 defm SUB : FPBinary_rr<fsub>;
 defm MUL : FPBinary_rr<fmul>;
 defm DIV : FPBinary_rr<fdiv>;
 }
 
 // Sets the scheduling resources for the actual NAME#_F<size>m defintions.
 let SchedRW = [WriteFAddLd] in {
 defm ADD : FPBinary<fadd, MRM0m, "add">;
 defm SUB : FPBinary<fsub, MRM4m, "sub">;
 defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>;
 }
 
 let SchedRW = [WriteFMulLd] in {
 defm MUL : FPBinary<fmul, MRM1m, "mul">;
 }
 
 let SchedRW = [WriteFDivLd] in {
 defm DIV : FPBinary<fdiv, MRM6m, "div">;
 defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
 }
-} // Defs = [FPSW]
+} // Uses = [FPCW], mayRaiseFPException = 1
 
 class FPST0rInst<Format fp, string asm>
   : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
 class FPrST0Inst<Format fp, string asm>
   : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;
 class FPrST0PInst<Format fp, string asm>
   : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>;
 
 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
 // of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,
 // we have to put some 'r's in and take them out of weird places.
-let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in {
 def ADD_FST0r   : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
 def ADD_FrST0   : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
 def ADD_FPrST0  : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
 def SUBR_FST0r  : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;
 def SUB_FrST0   : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;
 def SUB_FPrST0  : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;
 def SUB_FST0r   : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
 def SUBR_FrST0  : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
 } // SchedRW
-let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in {
 def COM_FST0r   : FPST0rInst <MRM2r, "fcom\t$op">;
 def COMP_FST0r  : FPST0rInst <MRM3r, "fcomp\t$op">;
 } // SchedRW
-let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in {
 def MUL_FST0r   : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;
 def MUL_FrST0   : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;
 def MUL_FPrST0  : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;
 } // SchedRW
-let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in {
 def DIVR_FST0r  : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;
 def DIV_FrST0   : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;
 def DIV_FPrST0  : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
 def DIV_FST0r   : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">;
 def DIVR_FrST0  : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">;
 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">;
 } // SchedRW
 
 // Unary operations.
 multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> {
 def _Fp32  : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
                  [(set RFP32:$dst, (OpNode RFP32:$src))]>;
 def _Fp64  : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
                  [(set RFP64:$dst, (OpNode RFP64:$src))]>;
 def _Fp80  : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
                  [(set RFP80:$dst, (OpNode RFP80:$src))]>;
 def _F     : FPI<0xD9, fp, (outs), (ins), asmstring>;
 }
 
-let Defs = [FPSW], Uses = [FPCW] in {
-
 let SchedRW = [WriteFSign] in {
 defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
 defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
 }
 
+let Uses = [FPCW], mayRaiseFPException = 1 in {
 let SchedRW = [WriteFSqrt80] in
 defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
 
 let SchedRW = [WriteFCom] in {
 let hasSideEffects = 0 in {
 def TST_Fp32  : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
 def TST_Fp64  : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
 def TST_Fp80  : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
 } // hasSideEffects
 
 def TST_F  : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
 } // SchedRW
-} // Defs = [FPSW]
+} // Uses = [FPCW], mayRaiseFPException = 1
 
 // Versions of FP instructions that take a single memory operand.  Added for the
 //   disassembler; remove as they are included with patterns elsewhere.
-let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in {
+let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1 in {
 def FCOM32m  : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
 
 def FCOM64m  : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
 
 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
 
 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
 } // SchedRW
 
 let SchedRW = [WriteMicrocoded] in {
+let Defs = [FPSW, FPCW] in {
 def FLDENVm  : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
-def FSTENVm  : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
-
 def FRSTORm  : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
+}
+
+let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW] in {
+def FSTENVm  : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
 def FSAVEm   : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;
+}
+
+let Uses = [FPSW] in
 def FNSTSWm  : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
 
 def FBLDm    : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
+let Uses = [FPCW] ,mayRaiseFPException = 1 in
 def FBSTPm   : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
 } // SchedRW
 
 // Floating point cmovs.
 class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
   FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
 class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
   FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
def _Fp64  : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
                                         cc, EFLAGS))]>;
   def _Fp80  : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
                      CondMovFP,
                      [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
                                         cc, EFLAGS))]>,
                                         Requires<[HasCMov]>;
 }
 
-let Defs = [FPSW] in {
 let SchedRW = [WriteFCMOV] in {
 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
 defm CMOVB  : FPCMov<X86_COND_B>;
 defm CMOVBE : FPCMov<X86_COND_BE>;
 defm CMOVE  : FPCMov<X86_COND_E>;
 defm CMOVP  : FPCMov<X86_COND_P>;
 defm CMOVNB : FPCMov<X86_COND_AE>;
 defm CMOVNBE: FPCMov<X86_COND_A>;
def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),
                   "fcmovnbe\t{$op, %st|st, $op}">;
 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
                   "fcmovne\t{$op, %st|st, $op}">;
 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
                   "fcmovnu\t{$op, %st|st, $op}">;
 } // Predicates = [HasCMov]
 } // SchedRW
 
+let mayRaiseFPException = 1 in {
 // Floating point loads & stores.
 let SchedRW = [WriteLoad], Uses = [FPCW] in {
 let canFoldAsLoad = 1 in {
 def LD_Fp32m   : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
                   [(set RFP32:$dst, (loadf32 addr:$src))]>;
 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
                   [(set RFP64:$dst, (loadf64 addr:$src))]>;
 def LD_Fp80m   : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (loadf80 addr:$src))]>;
 } // canFoldAsLoad
 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
                   [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
+let mayRaiseFPException = 0 in {
 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
                   [(set RFP32:$dst, (X86fild16 addr:$src))]>;
 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
                   [(set RFP32:$dst, (X86fild32 addr:$src))]>;
 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
                   [(set RFP32:$dst, (X86fild64 addr:$src))]>;
 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
                   [(set RFP64:$dst, (X86fild16 addr:$src))]>;
 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
                   [(set RFP64:$dst, (X86fild32 addr:$src))]>;
 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
                   [(set RFP64:$dst, (X86fild64 addr:$src))]>;
 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (X86fild16 addr:$src))]>;
 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (X86fild32 addr:$src))]>;
 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
                   [(set RFP80:$dst, (X86fild64 addr:$src))]>;
+} // mayRaiseFPException = 0
 } // SchedRW
 
 let SchedRW = [WriteStore], Uses = [FPCW] in {
 def ST_Fp32m   : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
                   [(store RFP32:$src, addr:$op)]>;
 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
                   [(truncstoref32 RFP64:$src, addr:$op)]>;
 def ST_Fp64m   : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,

 def IST_Fp64m80  : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
 } // mayStore
 } // SchedRW, Uses = [FPCW]
 
 let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {
 def LD_F32m   : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
 def LD_F64m   : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
 def LD_F80m   : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
+let mayRaiseFPException = 0 in {
 def ILD_F16m  : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
 def ILD_F32m  : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
 def ILD_F64m  : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
 }
+}
 let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
 def ST_F32m   : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
 def ST_F64m   : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
 def ST_FP32m  : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
 def ST_FP64m  : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
 def ST_FP80m  : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
 def IST_F16m  : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
 def IST_F32m  : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;

 }
 
 let SchedRW = [WriteFLD0], Uses = [FPCW] in
 def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
 
 let SchedRW = [WriteFLD1], Uses = [FPCW] in
 def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
 
-let SchedRW = [WriteFLDC], Uses = [FPCW] in {
+let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW] in {
 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
 } // SchedRW
 
 // Floating point compares.
 let SchedRW = [WriteFCom], Uses = [FPCW] in {
 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
                         [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
                         [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>;
 def UCOM_Fpr80 : FpI_  <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
                         [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
 } // SchedRW
-} // Defs = [FPSW]
+} // mayRaiseFPException = 1
 
-let SchedRW = [WriteFCom] in {
+let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
 // CC = ST(0) cmp ST(i)
-let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
+let Defs = [EFLAGS, FPCW], Uses = [FPCW] in {
 def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
                   [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
                   Requires<[FPStackf32, HasCMov]>;
 def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
                   [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>,
                   Requires<[FPStackf64, HasCMov]>;
 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
                   [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>,
                   Requires<[HasCMov]>;
 }
 
-let Defs = [FPSW], Uses = [ST0, FPCW] in {
+let Uses = [ST0, FPCW] in {
 def UCOM_Fr    : FPI<0xDD, MRM4r,    // FPSW = cmp ST(0) with ST(i)
                     (outs), (ins RSTi:$reg), "fucom\t$reg">;
 def UCOM_FPr   : FPI<0xDD, MRM5r,    // FPSW = cmp ST(0) with ST(i), pop
                     (outs), (ins RSTi:$reg), "fucomp\t$reg">;
 def UCOM_FPPr  : FPI<0xDA, MRM_E9,       // cmp ST(0) with ST(1), pop, pop
                     (outs), (ins), "fucompp">;
 }
 
 let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {
 def UCOM_FIr   : FPI<0xDB, MRM5r,     // CC = cmp ST(0) with ST(i)
                     (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">;
 def UCOM_FIPr  : FPI<0xDF, MRM5r,     // CC = cmp ST(0) with ST(i), pop
                     (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">;
 
 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg),
                   "fcomi\t{$reg, %st|st, $reg}">;
 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),
                    "fcompi\t{$reg, %st|st, $reg}">;
 }
 } // SchedRW
 
 // Floating point flag ops.
 let SchedRW = [WriteALU] in {
-let Defs = [AX], Uses = [FPSW] in
+let Defs = [AX, FPSW], Uses = [FPSW] in
 def FNSTSW16r : I<0xDF, MRM_E0,                  // AX = fp flags
                   (outs), (ins), "fnstsw\t{%ax|ax}",
                   [(set AX, (X86fp_stsw FPSW))]>;
 let Defs = [FPSW], Uses = [FPCW] in
 def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
                   (outs), (ins i16mem:$dst), "fnstcw\t$dst",
                   [(X86fp_cwd_get16 addr:$dst)]>;
 } // SchedRW
 let Defs = [FPSW,FPCW], mayLoad = 1 in
 def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
                   (outs), (ins i16mem:$dst), "fldcw\t$dst", []>,
                 Sched<[WriteLoad]>;
 
 // FPU control instructions
 let SchedRW = [WriteMicrocoded] in {
-let Defs = [FPSW] in {
-def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
 
+let Defs = [FPSW, FPCW] in
+def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
 // Clear exceptions
+let Defs = [FPSW] in
 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
-} // Defs = [FPSW]
 } // SchedRW
 
 // Operand-less floating-point instructions for the disassembler.
+let Defs = [FPSW] in
 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;
 
 let SchedRW = [WriteMicrocoded] in {
 let Defs = [FPSW] in {
 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>;
+def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
+def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
+let Uses = [FPCW], mayRaiseFPException = 1 in {
 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
 def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;
 def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;
 def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;
 def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;
 def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;
-def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
-def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
 def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;
 def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;
 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;
 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
+} // Uses = [FPCW], mayRaiseFPException = 1
 } // Defs = [FPSW]
 
+let Uses = [FPSW, FPCW] in {
 def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
              "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,
              Requires<[HasFXSR]>;
 def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
                "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,
                TB, Requires<[HasFXSR, In64BitMode]>;
+} // Uses = [FPSW, FPCW]
+
+let Defs = [FPSW, FPCW] in {
 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),
               "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,
               TB, Requires<[HasFXSR]>;
 def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),
                 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,
                 TB, Requires<[HasFXSR, In64BitMode]>;
+} // Defs = [FPSW, FPCW]
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
 // Required for RET of f32 / f64 / f80 values.
 def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>;

llvm/lib/Target/X86/X86InstrFormats.td

class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
   : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
   let Pattern = pattern;
   let CodeSize = 3;
 }
 
 // FPStack Instruction Templates:
 // FPI - Floating Point Instruction template.
 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
-  : I<o, F, outs, ins, asm, []> {}
+  : I<o, F, outs, ins, asm, []> {
+  let Defs = [FPSW];
+}
 
 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
   : PseudoI<outs, ins, pattern> {
   let FPForm = fp;
+  let Defs = [FPSW];
 }
 
 // Templates for instructions that use a 16- or 32-bit segmented address as
 //  their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
 //
 //   Iseg16 - 16-bit segment selector, 16-bit offset
 //   Iseg32 - 16-bit segment selector, 32-bit offset
 

llvm/test/CodeGen/X86/x87-reg-usage.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=x86-64 -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the x87 fpcw and fpcw regs
+
+--- |
+  declare float @llvm.sqrt.f32(float)
+
+  define void @f1(float* %a, float* %b) {
+    %1 = load float, float* %a, align 4
+    %2 = load float, float* %b, align 4
+    %sub = fsub float %1, %2
+    store float %sub, float* %a, align 4
+    ret void
+  }
+
+  define void @f2(double* %a, double* %b) {
+    %1 = load double, double* %a, align 8
+    %2 = load double, double* %b, align 8
+    %add = fadd double %1, %2
+    store double %add, double* %a, align 8
+    ret void
+  }
+
+  define void @f3(x86_fp80* %a, x86_fp80* %b) {
+    %1 = load x86_fp80, x86_fp80* %a, align 16
+    %2 = load x86_fp80, x86_fp80* %b, align 16
+    %mul = fmul x86_fp80 %1, %2
+    store x86_fp80 %mul, x86_fp80* %a, align 16
+    ret void
+  }
+
+  define void @f4(float* %a, float* %b) {
+    %1 = load float, float* %a, align 4
+    %2 = load float, float* %b, align 4
+    %div = fdiv float %1, %2
+    store float %div, float* %a, align 4
+    ret void
+  }
+
+  define void @f5(float* %val, double* %ret) {
+    %1 = load float, float* %val, align 4
+    %res = fpext float %1 to double
+    store double %res, double* %ret, align 8
+    ret void
+  }
+
+  define void @f6(double* %val, float* %ret) {
+    %1 = load double, double* %val, align 8
+    %res = fptrunc double %1 to float
+    store float %res, float* %ret, align 4
+    ret void
+  }
+
+  define void @f7(float* %a) {
+    %1 = load float, float* %a, align 4
+    %res = call float @llvm.sqrt.f32(float %1)
+    store float %res, float* %a, align 4
+    ret void
+  }
+
+
+
+...
+---
+name:            f1
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f1
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    ; CHECK: renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
+    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
+    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    RET 0
+
+...
+---
+name:            f2
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f2
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
+    ; CHECK: renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
+    ; CHECK: ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)
+    renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)
+    ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)
+    RET 0
+
+...
+---
+name:            f3
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f3
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
+    ; CHECK: renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
+    ; CHECK: renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
+    ; CHECK: ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)
+    renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)
+    renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
+    ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)
+    RET 0
+
+...
+---
+name:            f4
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f4
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    ; CHECK: renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
+    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)
+    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    RET 0
+
+...
+---
+name:            f5
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f5
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
+    ; CHECK: ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)
+    ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)
+    RET 0
+
+...
+---
+name:            f6
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+  - { reg: '$rsi' }
+frameInfo:
+  maxAlignment:    4
+stack:
+  - { id: 0, size: 4, alignment: 4 }
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi, $rsi
+
+    ; CHECK-LABEL: name: f6
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK: renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
+    ; CHECK: ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
+    ; CHECK: renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
+    ; CHECK: ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)
+    ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)
+    renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)
+    ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)
+    RET 0
+
+...
+---
+name:            f7
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $rdi
+
+    ; CHECK-LABEL: name: f7
+    ; CHECK: liveins: $rdi
+    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    ; CHECK: renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
+    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    ; CHECK: RET 0
+    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)
+    renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
+    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)
+    RET 0
+
+...