[Mips][llvm-exegesis] Add a Mips target

[mstojanovic]

Summary

The target does just enough to be able to run llvm-exegesis in latency mode for at least some opcodes.

[courbet]

Thanks for the contribution. I only have cosmetic comments.

unittests/tools/llvm-exegesis/Mips/TargetTest.cpp

28

You don't need these. I guess this is a copy-paste from the X86 tests: these are remains from a time when we were not in namespace llvm. (Fixed in rL374143).

57

ditto: remove llvm::

58

Don't you want to test the actual instruction ?

[atanasyan]

tools/llvm-exegesis/lib/Assembler.cpp

233–234

clang-format this line. it's too long.

[mstojanovic]

Removed obsolete llvm:: and includes, ran clang-format. Added direct testing of the instruction.

[atanasyan]

LGTM
Do you have commit access?

[mstojanovic]

Thank you for the reviews. I don't have commit access. @petarj usually commits the patches.

lib/Target/Mips/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
 tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
 tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM MipsGenExegesis.inc -gen-exegesis)
 
 add_public_tablegen_target(MipsCommonTableGen)
 
 add_llvm_target(MipsCodeGen
   Mips16FrameLowering.cpp
   Mips16HardFloat.cpp
   Mips16HardFloatInfo.cpp
   Mips16InstrInfo.cpp

lib/Target/Mips/Mips.td

 }
 
 def Mips : Target {
   let InstructionSet = MipsInstrInfo;
   let AssemblyParsers = [MipsAsmParser];
   let AssemblyParserVariants = [MipsAsmParserVariant];
   let AllowRegisterRenaming = 1;
 }
+
+//===----------------------------------------------------------------------===//
+// Pfm Counters
+//===----------------------------------------------------------------------===//
+
+include "MipsPfmCounters.td"

lib/Target/Mips/MipsPfmCounters.td

+//===-- MipsPfmCounters.td - Mips Hardware Counters --------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This describes the available hardware counters for Mips.
+//
+//===----------------------------------------------------------------------===//
+
+def CpuCyclesPfmCounter : PfmCounter<"CYCLES">;
+
+def DefaultPfmCounters : ProcPfmCounters {
+  let CycleCounter = CpuCyclesPfmCounter;
+}
+def : PfmCountersDefaultBinding<DefaultPfmCounters>;

tools/llvm-exegesis/lib/Assembler.cpp

void assembleToStream(const ExegesisTarget &ET,
   TargetPassConfig *TPC = TM->createPassConfig(PM);
   PM.add(TPC);
   PM.add(MMIWP.release());
   TPC->printAndVerify("MachineFunctionGenerator::assemble");
   // Add target-specific passes.
   ET.addTargetSpecificPasses(PM);
   TPC->printAndVerify("After ExegesisTarget::addTargetSpecificPasses");
   // Adding the following passes:
+  // - postrapseudos: expands pseudo return instructions used on some targets.
   // - machineverifier: checks that the MachineFunction is well formed.
   // - prologepilog: saves and restore callee saved registers.
-  for (const char *PassName : {"machineverifier", "prologepilog"})
+  for (const char *PassName :
+       {"postrapseudos", "machineverifier", "prologepilog"})
     if (addPass(PM, PassName, *TPC))
       report_fatal_error("Unable to add a mandatory pass");
   TPC->setInitialized();
 
   // AsmPrinter is responsible for generating the assembly into AsmBuffer.
   if (TM->addAsmPrinter(PM, AsmStream, nullptr, TargetMachine::CGFT_ObjectFile,
                         MCContext))
     report_fatal_error("Cannot add AsmPrinter passes");

tools/llvm-exegesis/lib/CMakeLists.txt

 set(TARGETS_TO_APPEND "")
 
 if (LLVM_TARGETS_TO_BUILD MATCHES "X86")
   add_subdirectory(X86)
   set(TARGETS_TO_APPEND "${TARGETS_TO_APPEND} X86")
 endif()
 if (LLVM_TARGETS_TO_BUILD MATCHES "AArch64")
   add_subdirectory(AArch64)
   set(TARGETS_TO_APPEND "${TARGETS_TO_APPEND} AArch64")
 endif()
 if (LLVM_TARGETS_TO_BUILD MATCHES "PowerPC")
   add_subdirectory(PowerPC)
   set(TARGETS_TO_APPEND "${TARGETS_TO_APPEND} PowerPC")
 endif()
+if (LLVM_TARGETS_TO_BUILD MATCHES "Mips")
+  add_subdirectory(Mips)
+  set(TARGETS_TO_APPEND "${TARGETS_TO_APPEND} Mips")
+endif()
 
 set(LLVM_EXEGESIS_TARGETS "${LLVM_EXEGESIS_TARGETS} ${TARGETS_TO_APPEND}" PARENT_SCOPE)
 
 add_library(LLVMExegesis
   STATIC
   Analysis.cpp
   Assembler.cpp
   BenchmarkResult.cpp

tools/llvm-exegesis/lib/Mips/CMakeLists.txt

+include_directories(
+  ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips
+  ${LLVM_BINARY_DIR}/lib/Target/Mips
+  )
+
+add_library(LLVMExegesisMips
+  STATIC
+  Target.cpp
+  )
+
+llvm_update_compile_flags(LLVMExegesisMips)
+llvm_map_components_to_libnames(libs
+  Mips
+  Exegesis
+  )
+
+target_link_libraries(LLVMExegesisMips ${libs})
+set_target_properties(LLVMExegesisMips PROPERTIES FOLDER "Libraries")

tools/llvm-exegesis/lib/Mips/LLVMBuild.txt

+;===- ./tools/llvm-exegesis/lib/Mips/LLVMBuild.txt -------------*- Conf -*--===;
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = ExegesisMips
+parent = Libraries
+required_libraries = Mips

tools/llvm-exegesis/lib/Mips/Target.cpp

+//===-- Target.cpp ----------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#include "../Target.h"
+#include "../Latency.h"
+#include "Mips.h"
+#include "MipsRegisterInfo.h"
+
+namespace llvm {
+namespace exegesis {
+
+#include "MipsGenExegesis.inc"
+
+namespace {
+class ExegesisMipsTarget : public ExegesisTarget {
+public:
+  ExegesisMipsTarget() : ExegesisTarget(MipsCpuPfmCounters) {}
+
+private:
+  std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+                               const APInt &Value) const override;
+  bool matchesArch(Triple::ArchType Arch) const override {
+    return Arch == Triple::mips || Arch == Triple::mipsel ||
+           Arch == Triple::mips64 || Arch == Triple::mips64el;
+  }
+};
+} // end anonymous namespace
+
+// Generates instruction to load an immediate value into a register.
+static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+                            const APInt &Value) {
+  if (Value.getActiveBits() > 16)
+    llvm_unreachable("Not implemented for Values wider than 16 bits");
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the Register");
+  return MCInstBuilder(Mips::ORi)
+      .addReg(Reg)
+      .addReg(Mips::ZERO)
+      .addImm(Value.getZExtValue());
+}
+
+std::vector<MCInst> ExegesisMipsTarget::setRegTo(const MCSubtargetInfo &STI,
+                                                 unsigned Reg,
+                                                 const APInt &Value) const {
+  if (Mips::GPR32RegClass.contains(Reg))
+    return {loadImmediate(Reg, 32, Value)};
+  if (Mips::GPR64RegClass.contains(Reg))
+    return {loadImmediate(Reg, 64, Value)};
+  errs() << "setRegTo is not implemented, results will be unreliable\n";
+  return {};
+}
+
+static ExegesisTarget *getTheExegesisMipsTarget() {
+  static ExegesisMipsTarget Target;
+  return &Target;
+}
+
+void InitializeMipsExegesisTarget() {
+  ExegesisTarget::registerTarget(getTheExegesisMipsTarget());
+}
+
+} // namespace exegesis
+} // namespace llvm

unittests/tools/llvm-exegesis/CMakeLists.txt

if(LLVM_TARGETS_TO_BUILD MATCHES "ARM")
   add_subdirectory(ARM)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "AArch64")
   add_subdirectory(AArch64)
 endif()
 if(LLVM_TARGETS_TO_BUILD MATCHES "PowerPC")
   add_subdirectory(PowerPC)
 endif()
+if(LLVM_TARGETS_TO_BUILD MATCHES "Mips")
+  add_subdirectory(Mips)
+endif()

unittests/tools/llvm-exegesis/Mips/CMakeLists.txt

+include_directories(
+  ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips
+  ${LLVM_BINARY_DIR}/lib/Target/Mips
+  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
+  )
+
+set(LLVM_LINK_COMPONENTS
+  MC
+  MCParser
+  Object
+  Support
+  Symbolize
+  Mips
+  )
+
+add_llvm_unittest(LLVMExegesisMipsTests
+  TargetTest.cpp
+  )
+target_link_libraries(LLVMExegesisMipsTests PRIVATE
+  LLVMExegesis
+  LLVMExegesisMips)

unittests/tools/llvm-exegesis/Mips/TargetTest.cpp

+//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Target.h"
+
+#include <cassert>
+#include <memory>
+
+#include "MCTargetDesc/MipsMCTargetDesc.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+
+namespace llvm {
+namespace exegesis {
+
+void InitializeMipsExegesisTarget();
+
+namespace {
+
+using testing::AllOf;
+using testing::ElementsAre;
+using testing::Eq;
+using testing::Matcher;
+using testing::Property;
+
+Matcher<MCOperand> IsImm(int64_t Value) {
+  return AllOf(Property(&MCOperand::isImm, Eq(true)),
+               Property(&MCOperand::getImm, Eq(Value)));
+}
+
+Matcher<MCOperand> IsReg(unsigned Reg) {
+  return AllOf(Property(&MCOperand::isReg, Eq(true)),
+               Property(&MCOperand::getReg, Eq(Reg)));
+}
+
+Matcher<MCInst> OpcodeIs(unsigned Opcode) {
+  return Property(&MCInst::getOpcode, Eq(Opcode));
+}
+
+Matcher<MCInst> IsLoadLowImm(int64_t Reg, int64_t Value) {
+  return AllOf(OpcodeIs(Mips::ORi),
+               ElementsAre(IsReg(Reg), IsReg(Mips::ZERO), IsImm(Value)));
+}
+
+constexpr const char kTriple[] = "mips-unknown-linux";
+
+class MipsTargetTest : public ::testing::Test {
+protected:
+  MipsTargetTest() : State(kTriple, "mips32", "") {}
+
+  static void SetUpTestCase() {
+    LLVMInitializeMipsTargetInfo();
+    LLVMInitializeMipsTarget();
+    LLVMInitializeMipsTargetMC();
+    InitializeMipsExegesisTarget();
+  }
+
+  std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
+    return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
+                                              Value);
+  }
+
+  LLVMState State;
+};
+
+TEST_F(MipsTargetTest, SetRegToConstant) {
+  const uint16_t Value = 0xFFFFU;
+  const unsigned Reg = Mips::T0;
+  EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
+              ElementsAre(IsLoadLowImm(Reg, Value)));
+}
+
+TEST_F(MipsTargetTest, DefaultPfmCounters) {
+  const std::string Expected = "CYCLES";
+  EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
+            Expected);
+  EXPECT_EQ(
+      State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
+      Expected);
+}
+
+} // namespace
+} // namespace exegesis
+} // namespace llvm