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[PowerPC] Handle f16 as a storage type only
Needs ReviewPublic

Authored by nemanjai on Sep 30 2019, 12:15 PM.

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hfinkel
jsji
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Restricted Project
Summary

The PPC back end currently crashes (fails to select) with f16 input. This patch expands it on subtargets prior to ISA 3.0 (Power9) and uses the HW conversions on Power9.

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rL LLVM

Event Timeline

nemanjai created this revision.Sep 30 2019, 12:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 30 2019, 12:15 PM
shchenz added inline comments.Oct 10 2019, 7:44 PM
lib/Target/PowerPC/PPCISelLowering.cpp
184

Do we need to handle ppcf128 also?

lib/Target/PowerPC/PPCInstrVSX.td
114

Guard under IsISA3_0?

3263

Guard under IsISA3_0?

test/CodeGen/PowerPC/handle-f16-storage-type.ll
8

#0 , seems all the function attributes are not defined?

nemanjai marked 4 inline comments as done.Oct 11 2019, 5:28 AM
nemanjai added inline comments.
lib/Target/PowerPC/PPCISelLowering.cpp
184

Not really. That type is really just a pair of doubles and there is no register that can contain it, so it will always be broken up into a pair of doubles by the legalizer.

lib/Target/PowerPC/PPCInstrVSX.td
114

Why? This is just a def of a pattern fragment. It is only defined here because it is missing in the target independent td file.

3263

The instructions used are defined in a Power9Vector guard and so are these patterns. I realize this is hard to track down from the patch - this file is in desperate need of refactoring :(

test/CodeGen/PowerPC/handle-f16-storage-type.ll
8

Sure, I can get rid of these (actually, I'll just define #0 as nounwind and use it for all the functions so we don't get the CFI nodes).

lei added a subscriber: lei.Tue, Nov 12, 7:40 AM
lei added inline comments.
lib/Target/PowerPC/PPCInstrVSX.td
3272

Should we clear the side effect bit for these? let hasSideEffects = 0