[ARM][AArch64][DebugInfo] Improve call site instruction interpretation

[NikolaPrica]

Summary

Extend describeLoadedValue with support for target specific ARM and AArch64 instruction interpretation. Some of the instructions can operate with global string addresses or constant pool indexes but such cases are omitted since we currently lack flexible support for processing such operands at dwarf generating backed.

[dstenb]

In general, is it really safe to describe loaded values at the call sites?

For example, consider the following program:

caller.c:

#include <stdint.h>

extern int callee(uint64_t);
extern void escape(uint64_t *);

uint64_t value = 0x1234;

int main() {
  uint64_t local = value;
  escape(&local);
  callee(local);
  return 0;
}

callee.c:

#include <stdint.h>

extern void clobber(void);

static uint64_t *ptr;

void escape(uint64_t *p) {
  ptr = p;
}

int callee(uint64_t p) {
  *ptr = 0xdead;
  clobber();
  // Print parameter here.
  return 0;
}

compiled using -O3 -g -Xclang -femit-debug-entry-values --target=aarch64 results in the following call site entry for callee's parameter:

0x000000cf:       DW_TAG_GNU_call_site_parameter
                    DW_AT_location	(DW_OP_reg0 W0)
                    DW_AT_GNU_call_site_value	(DW_OP_breg31 WSP+1, DW_OP_deref)

In this case it seems that the parameter would be printed incorrectly due to deref'ing local, which has been modified after the call to callee began? I unfortunately don't have any ARM machine/qemu up and running, so I can't verify this.

(A side-comment, but shouldn't the offset be 8 here? The value corresponds to a ldr x0, [sp, #8].)

I think that the same concern holds about the MI.hasOneMemOperand() part of TargetInstrInfo's implementation of describeLoadedValue().

The DWARF standard (Sec. 3.4.2) states that call site values should be omitted if they may be clobbered by the call:

If it is not possible to avoid registers or memory locations that might be clobbered by the call in the expression, then the DW_AT_call_value attribute should not be provided. The reason for the restriction is that the value of the parameter may be needed in the midst of the callee, where the call clobbered registers or memory might be already clobbered, and if the consumer is not assured by the producer it can safely use those values, the consumer can not safely use the values at all.

Or am I overlooking something here?

include/llvm/CodeGen/TargetInstrInfo.h

891 ↗

(On Diff #220110)

spelling: Immediate

lib/Target/ARM/ARMBaseInstrInfo.cpp

5327 ↗

(On Diff #220110)

nit: describe

5348 ↗

(On Diff #220110)

nit: also

[NikolaPrica]

-Address spelling issues.
-Dispatch memory loading instruction descriptions.

[NikolaPrica]

@dstenb you are right! I've tried this example and it is as you expected. We should avoid dereferencing memory locations. I will address those issues in separate patch.

[NikolaPrica]

-Remove unnecessary MIR test elements.

[NikolaPrica]

-Remove redundant comment.

[vsk]

In D67556#1672428, @NikolaPrica wrote:

@dstenb you are right! I've tried this example and it is as you expected. We should avoid dereferencing memory locations. I will address those issues in separate patch.

@dstenb @NikolaPrica, thanks for sharing, that's a great example. I've filed llvm.org/PR43343 so we can track the issue and discuss solutions.

[dstenb]

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

682–684 ↗

(On Diff #220487)

Any sense of what it would take to add support for such entry values? Would it be enough to store the expression alongside the new register in the work list, and then concatenate the two expressions when finding an instruction that describes the new register? Or must we consider how the expressions look in some way?

[NikolaPrica]

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

682–684 ↗

(On Diff #220487)

I believe that such pair of register and expression would be enough for generating new entry value. For now, there are simple cases such as DW_OP_plus/minus over the parameter forwarding registers. This new restriction came from instructions such as "$w0 = nsw ADDWri $w0, 2, 0".

[dstenb]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

I wonder if the hook should allow the source and destination to be different, as we then for example could describe cases like this:

$reg0 = add $frame-ptr, -13

If so, would it then make sense to move the LEA part of X86's describeLoadedValue() hook into this hook instead?

[dstenb]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

If so, should we perhaps also consider generalizing the hook so that it has a Destination out-parameter, e.g. same as isCopyInstr()? That could probably be helpful if we make the describeLoadedValue() hook aware of which register it should describe, as we discussed in D67225.

[NikolaPrica]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

I wonder if the hook should allow the source and destination to be different

In fact we should only relay on situations were source and destination operands are different. Such restriction should be used at general part of describeLoadedValue(). There is no use of describing situatios like

$reg0 = add $reg0, 4

This case would require recursive description of $reg0. Describing such instruction is a different story.

If so, would it then make sense to move the LEA part of X86's describeLoadedValue() hook into this hook instead?

The LEA instruction is more complex than add immidiate instruction. It could be observed as add immidiate for one case but it could also have addition of multiple source registers with some multiplication operations. IMHO it would be better to keep this API function clean in sense of recognizing only clear add immidiate instruction for purpose of further usage.

If so, should we perhaps also consider generalizing the hook so that it has a Destination out-parameter, e.g. same as isCopyInstr()? That could probably be helpful if we make the describeLoadedValue() hook aware of which register it should describe, as we discussed in D67225.

In the first version of this function I've added a destination operand but I've removed it since there was no current use of it. But for further flexibilty I will add it.

[dstenb]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

In fact we should only relay on situations were source and destination operands are different. Such restriction should be used at general part of describeLoadedValue(). There is no use of describing situatios like

$reg0 = add $reg0, 4

In previous revisions of the downstream target we develop for we had to resort to:

$reg0 = mov $frame-ptr
$reg0 = add $reg0, $offset

instead of loading the frame pointer with an offset in one instruction. Perhaps there is some upstream target that requires the same?

This case would require recursive description of $reg0. Describing such instruction is a different story.

Is that due to the issue with expressions in collectCallSiteParameters() which we discussed earlier in this patch?

The LEA instruction is more complex than add immidiate instruction. It could be observed as add immidiate for one case but it could also have addition of multiple source registers with some multiplication operations. IMHO it would be better to keep this API function clean in sense of recognizing only clear add immidiate instruction for purpose of further usage.

Okay, that sounds fair. Moving some parts to the LEA implementation to this hook, and keeping the rest in describeLoadedValue() would probably not be ideal.

In the first version of this function I've added a destination operand but I've removed it since there was no current use of it. But for further flexibilty I will add it.

Okay, thanks!

[NikolaPrica]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

Is that due to the issue with expressions in collectCallSiteParameters() which we discussed earlier in this patch?

Yes. You are right. Such cases should be handled the way we discussed there. But until such support is provided such instructions ($reg0 = add $reg0, 4) should be omitted. I will emphasize that as TODO comment.

[NikolaPrica]

-Include Destination operand in isAddImmediate()
-Exclude description of add immediate instructions where source and destination registers are the same.

[dstenb]

include/llvm/CodeGen/TargetInstrInfo.h

888 ↗

(On Diff #220487)

[...] adds an immediate value to its first operand and stores it in the first, [...]

This part of the comment needs to be updated to reflect that the destination and source can be any operands.

lib/Target/ARM/ARMBaseInstrInfo.cpp

5335 ↗

(On Diff #223848)

nit: theirs -> their

test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir

2 ↗

(On Diff #223848)

I'm sorry for such a late comment about this, but if you still have the C reproducers readily available I think it would be helpful to add them to the tests (assuming that the IR or MIR haven't been substantially modified).

[NikolaPrica]

-Update addImmediate() commet.
-Add source code producer for test case.

[NikolaPrica]

Any additional comments?

[dstenb]

Thanks for adding the source-level reproducers!

LGTM except for the some minor inline comments. I think it would be good to let the others have their say about this also.

lib/CodeGen/TargetInstrInfo.cpp

1137–1140 ↗

(On Diff #224077)

Would it be safe to return such values without this check due to the getNumElements() == 0 check in collectCallSiteParameters()? If so, perhaps we should just consider this a limitation in collectCallSiteParameters(), and let the hook describe the values even though they currently can't be used by the caller.

lib/Target/AArch64/AArch64InstrInfo.cpp

5698–5700 ↗

(On Diff #224077)

nit: Indentation. There are some minor indentation things inside the switch case also (e.g. space before parenthesis in assert ().

lib/Target/ARM/ARMBaseInstrInfo.cpp

5335 ↗

(On Diff #223848)

That typo is still here.

[NikolaPrica]

-AArch64InstrInfo::addImmediate() indentation

Thanks for useful comments @dstenb!

[NikolaPrica]

lib/CodeGen/TargetInstrInfo.cpp

1137–1140 ↗

(On Diff #224077)

It would be safe. getNumElements() == 0 would cover this case. But I wanted to explicitly document such behaviour in form of code block and TODO. Although in describeLoadedValue () we choose what we describe it may be better to move such verification to collectCallSiteParameters ()?

[dstenb]

lib/CodeGen/TargetInstrInfo.cpp

1137–1140 ↗

(On Diff #224077)

Sorry for the delay!

Moving the verification to collectCallSiteParameters() sounds good to me.

[NikolaPrica]

-Rebase
-Move register identity transformation check to DwarfDebug::collectCallSiteParameters()

[aprantl]

include/llvm/CodeGen/TargetInstrInfo.h

947 ↗

(On Diff #225430)

nit: \c Source

[NikolaPrica]

include/llvm/CodeGen/TargetInstrInfo.h

947 ↗

(On Diff #225430)

Sorry, I'm not sure what are you aiming at. Do you think I should replace the order of Source and Destination?

[dstenb]

include/llvm/CodeGen/TargetInstrInfo.h

947 ↗

(On Diff #225430)

Looking at the Doxygen documentation, it appears that @ is an alias for \, i.e. a command prefix, so I think this says that Source and Destination are Doxygen commands. \c Source would print the variable with the typewriter font, which I guess was the intention here?

[aprantl]

include/llvm/CodeGen/TargetInstrInfo.h

947 ↗

(On Diff #225430)

Correct. We generally prefer the \ version over @ in LLVM.

[NikolaPrica]

@ -> \c

[aprantl]

lib/Target/ARM/ARMBaseInstrInfo.cpp

5355 ↗

(On Diff #226415)

Sorry for being late in the game. I find it weird for a function called is to have inout parameters. What about doing something along the lines of:

struct DestSourcePair {const MachineOperand *Destination, *Source;};
Optional<DestSource> isAddImmediate(MI);

[NikolaPrica]

lib/Target/ARM/ARMBaseInstrInfo.cpp

5355 ↗

(On Diff #226415)

That sound better. But since isCopyInstr and isCopyInstrImpl have similar signature maybe I should post such change as a separate NFC patch?

[aprantl]

lib/Target/ARM/ARMBaseInstrInfo.cpp

5355 ↗

(On Diff #226415)

Sure. Either way works.

[NikolaPrica]

Is this good to go now?

[vsk]

Thanks, lgtm. This seems to be in great shape.

[dstenb]

Yes, thanks!

llvm/include/llvm/CodeGen/TargetInstrInfo.h

bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
     if (MI.isCopy()) {
       Destination = &MI.getOperand(0);
       Source = &MI.getOperand(1);
       return true;
     }
     return isCopyInstrImpl(MI, Source, Destination);
   }
 
+  /// If the specific machine instruction is an instruction that adds an
+  /// immediate value to its \c Source operand and stores it in \c Destination,
+  /// return true along with \c Destination and \c Source machine operand to
+  /// which \c Offset has been added.
+  virtual bool isAddImmediate(const MachineInstr &MI,
+                              const MachineOperand *&Destination,
+                              const MachineOperand *&Source,
+                              int64_t &Offset) const {
+    return false;
+  }
+
   /// Store the specified register of the given register class to the specified
   /// stack frame index. The store instruction is to be added to the given
   /// machine basic block before the specified machine instruction. If isKill
   /// is true, the register operand is the last use and must be marked kill.
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned SrcReg, bool isKill, int FrameIndex,
                                    const TargetRegisterClass *RC,

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

for (auto Reg : concat<unsigned>(ExplicitFwdRegDefs, ImplicitFwdRegDefs))
       ForwardedRegWorklist.erase(Reg);
 
     // The describeLoadedValue() hook currently does not have any information
     // about which register it should describe in case of multiple defines, so
     // for now we only handle instructions where a forwarded register is (at
     // least partially) defined by the instruction's single explicit define.
     if (I->getNumExplicitDefs() != 1 || ExplicitFwdRegDefs.empty())
       continue;
-    unsigned Reg = ExplicitFwdRegDefs[0];
+    unsigned ParamFwdReg = ExplicitFwdRegDefs[0];
 
     if (auto ParamValue = TII->describeLoadedValue(*I)) {
       if (ParamValue->first.isImm()) {
         int64_t Val = ParamValue->first.getImm();
         DbgValueLoc DbgLocVal(ParamValue->second, Val);
-        finishCallSiteParam(DbgLocVal, Reg);
+        finishCallSiteParam(DbgLocVal, ParamFwdReg);
       } else if (ParamValue->first.isReg()) {
         Register RegLoc = ParamValue->first.getReg();
+       // TODO: For now, there is no use of describing the value loaded into the
+       //       register that is also the source registers (e.g. $r0 = add $r0, x).
+       if (ParamFwdReg == RegLoc)
+         continue;
+
         unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
         Register FP = TRI->getFrameRegister(*MF);
         bool IsSPorFP = (RegLoc == SP) || (RegLoc == FP);
         if (TRI->isCalleeSavedPhysReg(RegLoc, *MF) || IsSPorFP) {
           DbgValueLoc DbgLocVal(ParamValue->second,
                                 MachineLocation(RegLoc,
                                                 /*IsIndirect=*/IsSPorFP));
-          finishCallSiteParam(DbgLocVal, Reg);
-        } else if (ShouldTryEmitEntryVals) {
+          finishCallSiteParam(DbgLocVal, ParamFwdReg);
+        // TODO: Add support for entry value plus an expression.
+        } else if (ShouldTryEmitEntryVals &&
+                   ParamValue->second->getNumElements() == 0) {
           ForwardedRegWorklist.insert(RegLoc);
-          RegsForEntryValues[RegLoc] = Reg;
+          RegsForEntryValues[RegLoc] = ParamFwdReg;
         }
       }
     }
   }
 
   // Emit the call site parameter's value as an entry value.
   if (ShouldTryEmitEntryVals) {
     // Create an expression where the register's entry value is used.

llvm/lib/CodeGen/TargetInstrInfo.cpp

bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
   unsigned DefClass = DefMI.getDesc().getSchedClass();
   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
   return (DefCycle != -1 && DefCycle <= 1);
 }
 
 Optional<ParamLoadedValue>
 TargetInstrInfo::describeLoadedValue(const MachineInstr &MI) const {
   const MachineFunction *MF = MI.getMF();
-  const MachineOperand *Op = nullptr;
-  DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});;
+  DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
   const MachineOperand *SrcRegOp, *DestRegOp;
+  int64_t Offset;
 
   if (isCopyInstr(MI, SrcRegOp, DestRegOp)) {
-    Op = SrcRegOp;
-    return ParamLoadedValue(*Op, Expr);
+    return ParamLoadedValue(*SrcRegOp, Expr);
+  } else if (isAddImmediate(MI, DestRegOp, SrcRegOp, Offset)) {
+    Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
+    return ParamLoadedValue(*SrcRegOp, Expr);
   }
 
   return None;
 }
 
 /// Both DefMI and UseMI must be valid.  By default, call directly to the
 /// itinerary. This may be overriden by the target.
 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
   /// Returns true if the instruction has a shift by immediate that can be
   /// executed in one cycle less.
   static bool isFalkorShiftExtFast(const MachineInstr &MI);
   /// Return true if the instructions is a SEH instruciton used for unwinding
   /// on Windows.
   static bool isSEHInstruction(const MachineInstr &MI);
 
+  bool isAddImmediate(const MachineInstr &MI,
+                      const MachineOperand *&Destination,
+                      const MachineOperand *&Source,
+                      int64_t &Offset) const override;
+
+  Optional<ParamLoadedValue>
+  describeLoadedValue(const MachineInstr &MI) const override;
+
 #define GET_INSTRINFO_HELPER_DECLS
 #include "AArch64GenInstrInfo.inc"
 
 protected:
   /// If the specific machine instruction is a instruction that moves/copies
   /// value from one register to another register return true along with
   /// @Source machine operand and @Destination machine operand.
   bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (MI.getOpcode() == AArch64::ORRXrs &&
     Destination = &MI.getOperand(0);
     Source = &MI.getOperand(2);
     return true;
   }
 
   return false;
 }
 
+bool AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
+                                      const MachineOperand *&Destination,
+                                      const MachineOperand *&Source,
+                                      int64_t &Offset) const {
+  int Sign = 1;
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case AArch64::SUBWri:
+  case AArch64::SUBXri:
+  case AArch64::SUBSWri:
+  case AArch64::SUBSXri:
+    Sign *= -1;
+    LLVM_FALLTHROUGH;
+  case AArch64::ADDSWri:
+  case AArch64::ADDSXri:
+  case AArch64::ADDWri:
+  case AArch64::ADDXri: {
+    // TODO: Third operand can be global address (usually some string).
+    if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
+        !MI.getOperand(2).isImm())
+      return false;
+    Source = &MI.getOperand(1);
+    Offset = MI.getOperand(2).getImm() * Sign;
+    int Shift = MI.getOperand(3).getImm();
+    assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
+    Offset = Offset << Shift;
+  }
+  }
+  Destination = &MI.getOperand(0);
+  return true;
+}
+
+Optional<ParamLoadedValue>
+AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case AArch64::MOVZWi:
+  case AArch64::MOVZXi:
+    if (!MI.getOperand(1).isImm())
+      return None;
+    int Immediate = MI.getOperand(1).getImm();
+    int Shift = MI.getOperand(2).getImm();
+    return ParamLoadedValue(MachineOperand::CreateImm(Immediate << Shift),
+                            nullptr);
+  }
+  return TargetInstrInfo::describeLoadedValue(MI);
+}
+
 #define GET_INSTRINFO_HELPERS
 #include "AArch64GenInstrInfo.inc"

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

unsigned getFramePred(const MachineInstr &MI) const {
     // - argument declared in the pattern:
     // 0 - frame size
     // 1 - arg of CALLSEQ_START/CALLSEQ_END
     // 2 - predicate code (like ARMCC::AL)
     // - added by predOps:
     // 3 - predicate reg
     return MI.getOperand(3).getReg();
   }
+
+  bool isAddImmediate(const MachineInstr &MI,
+                      const MachineOperand *&Destination,
+                      const MachineOperand *&Source,
+                      int64_t &Offset) const override;
 };
 
 /// Get the operands corresponding to the given \p Pred value. By default, the
 /// predicate register is assumed to be 0 (no register), but you can pass in a
 /// \p PredReg if that is not the case.
 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
                                                     unsigned PredReg = 0) {
   return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_GOT, "arm-got"},
       {MO_SBREL, "arm-sbrel"},
       {MO_DLLIMPORT, "arm-dllimport"},
       {MO_SECREL, "arm-secrel"},
       {MO_NONLAZY, "arm-nonlazy"}};
   return makeArrayRef(TargetFlags);
 }
 
+bool ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
+                                      const MachineOperand *&Destination,
+                                      const MachineOperand *&Source,
+                                      int64_t &Offset) const {
+  int Sign = 1;
+  unsigned Opcode = MI.getOpcode();
+
+  // We describe SUBri or ADDri instructions.
+  if (Opcode == ARM::SUBri)
+    Sign = -1;
+  else if (Opcode != ARM::ADDri)
+    return false;
+
+  // TODO: Third operand can be global address (usually some string). Since
+  //       strings can be relocated we cannot calculate their offsets for
+  //       now.
+  if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
+      !MI.getOperand(2).isImm())
+    return false;
+
+  Destination = &MI.getOperand(0);
+  Source = &MI.getOperand(1);
+  Offset = MI.getOperand(2).getImm() * Sign;
+  return true;
+}
+
 bool llvm::registerDefinedBetween(unsigned Reg,
                                   MachineBasicBlock::iterator From,
                                   MachineBasicBlock::iterator To,
                                   const TargetRegisterInfo *TRI) {
   for (auto I = From; I != To; ++I)
     if (I->modifiesRegister(Reg, TRI))
       return true;
   return false;

llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir

+# RUN: llc -mtriple aarch64-linux-gnu -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s
+# Following code is used for producing this test case. Note that
+# some of argument loading instruction are modified in order to
+# cover certain cases.
+#
+# extern int func2(int,int,int*);
+# int func1(int arg1, int arg2, int arg3) {
+#   int a = func2(arg1 + 2, arg2 - 4, &arg3);
+#   a += func2(arg3 - 16, arg1 + 8, &a);
+#   return a++;
+# }
+#
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "func2"
+# CHECK: DW_TAG_GNU_call_site_parameter
+# CHECK-NOT:   DW_AT_location      (DW_OP_reg2 W0)
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg2 W2)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_fbreg +28)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg1 W1)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg19 W19-4)
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "func2")
+# CHECK-NEXT: DW_AT_low_pc
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg0 W0)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_lit13)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# W2 loads memory location. We can't rely that memory location won't be changed.
+# CHECK-NOT:   DW_AT_location      (DW_OP_reg2 W2)
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg1 W1)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_constu 0xc0)
+--- |
+  ; ModuleID = 'describe-call-pram-load-instruction.c'
+  source_filename = "describe-call-pram-load-instruction.c"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-linux-gnu"
+  
+  ; Function Attrs: nounwind
+  define dso_local i32 @func1(i32 %arg1, i32 %arg2, i32 %arg3) local_unnamed_addr #0 !dbg !13 {
+  entry:
+    %arg3.addr = alloca i32, align 4
+    %a = alloca i32, align 4
+    call void @llvm.dbg.value(metadata i32 %arg1, metadata !17, metadata !DIExpression()), !dbg !21
+    call void @llvm.dbg.value(metadata i32 %arg2, metadata !18, metadata !DIExpression()), !dbg !21
+    call void @llvm.dbg.value(metadata i32 %arg3, metadata !19, metadata !DIExpression()), !dbg !21
+    store i32 %arg3, i32* %arg3.addr, align 4
+    %0 = bitcast i32* %a to i8*, !dbg !21
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !21
+    %add = add nsw i32 %arg1, 2, !dbg !21
+    %sub = add nsw i32 %arg2, -4, !dbg !21
+    call void @llvm.dbg.value(metadata i32* %arg3.addr, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21
+    %call = call i32 @func2(i32 %add, i32 %sub, i32* nonnull %arg3.addr), !dbg !21
+    call void @llvm.dbg.value(metadata i32 %call, metadata !20, metadata !DIExpression()), !dbg !21
+    store i32 %call, i32* %a, align 4, !dbg !21
+    %1 = load i32, i32* %arg3.addr, align 4, !dbg !21
+    call void @llvm.dbg.value(metadata i32 %1, metadata !19, metadata !DIExpression()), !dbg !21
+    %sub1 = add nsw i32 %1, -16, !dbg !21
+    %add2 = add nsw i32 %arg1, 8, !dbg !21
+    call void @llvm.dbg.value(metadata i32* %a, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !21
+    %call3 = call i32 @func2(i32 %sub1, i32 %add2, i32* nonnull %a), !dbg !21
+    %2 = load i32, i32* %a, align 4, !dbg !21
+    call void @llvm.dbg.value(metadata i32 %2, metadata !20, metadata !DIExpression()), !dbg !21
+    %add4 = add nsw i32 %2, %call3, !dbg !21
+    call void @llvm.dbg.value(metadata i32 %add4, metadata !20, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !21
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0), !dbg !21
+    ret i32 %add4, !dbg !21
+  }
+  
+  ; Function Attrs: argmemonly nounwind willreturn
+  declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+  
+  declare !dbg !4 dso_local i32 @func2(i32, i32, i32*) local_unnamed_addr
+  
+  ; Function Attrs: argmemonly nounwind willreturn
+  declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+  
+  ; Function Attrs: nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**)
+  
+  attributes #0 = { "frame-pointer"="all" }
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!9, !10, !11}
+  !llvm.ident = !{!12}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None)
+  !1 = !DIFile(filename: "describe-call-pram-load-instruction.c", directory: "/")
+  !2 = !{}
+  !3 = !{!4}
+  !4 = !DISubprogram(name: "func2", scope: !1, file: !1, line: 8, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+  !5 = !DISubroutineType(types: !6)
+  !6 = !{!7, !7, !7, !8}
+  !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64)
+  !9 = !{i32 2, !"Dwarf Version", i32 4}
+  !10 = !{i32 2, !"Debug Info Version", i32 3}
+  !11 = !{i32 1, !"wchar_size", i32 4}
+  !12 = !{!"clang version 10.0.0 "}
+  !13 = distinct !DISubprogram(name: "func1", scope: !1, file: !1, line: 9, type: !14, scopeLine: 9, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
+  !14 = !DISubroutineType(types: !15)
+  !15 = !{!7, !7, !7, !7}
+  !16 = !{!17, !18, !19, !20}
+  !17 = !DILocalVariable(name: "arg1", arg: 1, scope: !13, file: !1, line: 9, type: !7, flags: DIFlagArgumentNotModified)
+  !18 = !DILocalVariable(name: "arg2", arg: 2, scope: !13, file: !1, line: 9, type: !7, flags: DIFlagArgumentNotModified)
+  !19 = !DILocalVariable(name: "arg3", arg: 3, scope: !13, file: !1, line: 9, type: !7)
+  !20 = !DILocalVariable(name: "a", scope: !13, file: !1, line: 10, type: !7)
+  !21 = !DILocation(line: 0, scope: !13)
+
+...
+---
+name:            func1
+frameInfo:
+  adjustsStack:    true
+  hasCalls:        true
+stack:
+  - { id: 0, name: arg3.addr, offset: -4, size: 4, alignment: 4, local-offset: -4 }
+  - { id: 1, name: a, offset: -8, size: 4, alignment: 4, local-offset: -8 }
+  - { id: 2, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x19' }
+  - { id: 3, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$lr' }
+  - { id: 4, type: spill-slot, offset: -32, size: 8, alignment: 8, callee-saved-register: '$fp' }
+callSites:
+  - { bb: 0, offset: 20, fwdArgRegs: 
+      - { arg: 0, reg: '$w0' }
+      - { arg: 1, reg: '$w1' }
+      - { arg: 2, reg: '$x2' } }
+  - { bb: 0, offset: 29, fwdArgRegs: 
+      - { arg: 0, reg: '$w0' }
+      - { arg: 1, reg: '$w1' }
+      - { arg: 2, reg: '$x2' } }
+body:             |
+  bb.0.entry:
+    liveins: $w0, $w1, $w2, $lr, $x19
+  
+    DBG_VALUE $w0, $noreg, !17, !DIExpression(), debug-location !21
+    DBG_VALUE $w1, $noreg, !18, !DIExpression(), debug-location !21
+    DBG_VALUE $w1, $noreg, !18, !DIExpression(), debug-location !21
+    DBG_VALUE $w2, $noreg, !19, !DIExpression(), debug-location !21
+    DBG_VALUE $w2, $noreg, !19, !DIExpression(), debug-location !21
+    early-clobber $sp = frame-setup STPXpre $fp, killed $lr, $sp, -4 :: (store 8 into %stack.4), (store 8 into %stack.3)
+    frame-setup STRXui killed $x19, $sp, 2 :: (store 8 into %stack.2)
+    $fp = frame-setup ADDXri $sp, 0, 0
+    frame-setup CFI_INSTRUCTION def_cfa $w29, 32
+    frame-setup CFI_INSTRUCTION offset $w19, -16
+    frame-setup CFI_INSTRUCTION offset $w30, -24
+    frame-setup CFI_INSTRUCTION offset $w29, -32
+    $w19 = ORRWrs $wzr, $w0, 0
+    DBG_VALUE $w19, $noreg, !17, !DIExpression(), debug-location !21
+    STRWui killed renamable $w2, $fp, 7 :: (store 4 into %ir.arg3.addr)
+    renamable $w0 = nsw ADDWri $w0, 2, 0, debug-location !21
+    renamable $w1 = nsw SUBWri renamable $w19, 4, 0, debug-location !21
+    DBG_VALUE $w1, $noreg, !18, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
+    DBG_VALUE $fp, $noreg, !19, !DIExpression(DW_OP_plus_uconst, 28, DW_OP_deref), debug-location !21
+    $x2 = ADDXri $fp, 28, 0, debug-location !21
+    BL @func2, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $x2, implicit-def $sp, implicit-def $w0, debug-location !21
+    DBG_VALUE $w0, $noreg, !20, !DIExpression(), debug-location !21
+    renamable $w8 = LDRWui $fp, 7, debug-location !21 :: (dereferenceable load 4 from %ir.arg3.addr)
+    DBG_VALUE $w8, $noreg, !19, !DIExpression(), debug-location !21
+    STRWui killed renamable $w0, $fp, 6, debug-location !21 :: (store 4 into %ir.a)
+    renamable $w1 = nsw MOVZWi 12, 4
+    DBG_VALUE $fp, $noreg, !20, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref), debug-location !21
+    $x2 = LDRXui $fp, 24, debug-location !21
+    renamable $w0 = nsw MOVZWi 13, 0
+    BL @func2, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $x2, implicit-def $sp, implicit-def $w0, debug-location !21
+    renamable $w8 = LDRWui $fp, 6, debug-location !21 :: (dereferenceable load 4 from %ir.a)
+    DBG_VALUE $w8, $noreg, !20, !DIExpression(), debug-location !21
+    $x19 = frame-destroy LDRXui $sp, 2, debug-location !21 :: (load 8 from %stack.2)
+    DBG_VALUE $w0, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
+    $w0 = ADDWrs killed renamable $w8, killed renamable $w0, 0, debug-location !21
+    DBG_VALUE $w0, $noreg, !20, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !21
+    early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 4, debug-location !21 :: (load 8 from %stack.4), (load 8 from %stack.3)
+    RET undef $lr, implicit killed $w0, debug-location !21
+
+...