This adds the patterns required to transform xor P0, -1 to a VPNOT. The instruction operands have to change a little for this, adding an in and an out VCCR reg and using a custom DecodeMVEVPNOT for the decode.
Details
Details
Diff Detail
Diff Detail
- Repository
- rL LLVM
Event Timeline
llvm/lib/Target/ARM/ARMInstrMVE.td | ||
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4604 ↗ | (On Diff #211254) | I like the fact that, unlike almost any other instruction that modifies a register in place, you don't need a constraint here tying together the input and output register numbers :-) |