Page MenuHomePhabricator

[ARM] MVE VPNOT
ClosedPublic

Authored by dmgreen on Jul 23 2019, 12:41 AM.

Details

Summary

This adds the patterns required to transform xor P0, -1 to a VPNOT. The instruction operands have to change a little for this, adding an in and an out VCCR reg and using a custom DecodeMVEVPNOT for the decode.

Diff Detail

Repository
rL LLVM

Event Timeline

dmgreen created this revision.Jul 23 2019, 12:41 AM
simon_tatham accepted this revision.Jul 23 2019, 1:15 AM
simon_tatham added inline comments.
llvm/lib/Target/ARM/ARMInstrMVE.td
4604 ↗(On Diff #211254)

I like the fact that, unlike almost any other instruction that modifies a register in place, you don't need a constraint here tying together the input and output register numbers :-)

This revision is now accepted and ready to land.Jul 23 2019, 1:15 AM
Closed by commit rL367192: [ARM] MVE VPNOT (authored by dmgreen, committed by ). · Explain WhyJul 28 2019, 7:49 AM
This revision was automatically updated to reflect the committed changes.