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[ARM] MVE integer compares and selects
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Authored by dmgreen on Jul 21 2019, 6:46 AM.

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Summary

This adds the very basics for MVE vector predication, adding integer VCMP and VSEL instruction support. This is done through predicate registers (MVT::v16i1, MVT::v8i1, MVT::v4i1), but otherwise using same mechanics as NEON to custom lower setcc's through ARMISD::VCXX nodes (VCEQ, VCGT, VCEQZ, etc). An extra VCNE was added, as this can be handled sensibly by MVE's expanded number of VCMP condition codes. (There are also VCLE and VCLT which are added later). VPSEL is also added here, simply selecting on the vselect.

Original code by David Sherwood.

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Repository
rL LLVM

Event Timeline

dmgreen created this revision.Jul 21 2019, 6:46 AM
SjoerdMeijer accepted this revision.Jul 23 2019, 2:22 PM

Looks reasonable to me.

This revision is now accepted and ready to land.Jul 23 2019, 2:22 PM
This revision was automatically updated to reflect the committed changes.