[RISCV] Specify registers used for exception handling

[edward-jones]

Summary

Implements the handling of __builtin_eh_return_regno()

[edward-jones]

Added tests

[asb]

Could you please add a riscv64 RUN line too, for completeness? Other archs seem to call the equivalent test file builtins-archname.c rather than builtin-archname.c, so I'd adjust the naming to match.

Then this looks good to me. Thanks!

[edward-jones]

Add riscv64 target run line, renamed test file to builtins-riscv.c, and rebased.

[asb]

Thanks, looks good to me!

[asb]

test/CodeGen/builtins-riscv.c

4 ↗

(On Diff #207736)

Nit: having { on this line would be more consistent with usual LLVM style

[asb]

Ed, if you haven't already could you request commit access so you can commit these approved patches yourself? See https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access for details.

lib/Basic/Targets/RISCV.h

public:
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::VoidPtrBuiltinVaList;
   }
 
   const char *getClobbers() const override { return ""; }
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
+  int getEHDataRegisterNumber(unsigned RegNo) const override {
+    if (RegNo == 0)
+      return 10;
+    else if (RegNo == 1)
+      return 11;
+    else
+      return -1;
+  }
+
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,