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[RISCV] Specify registers used for exception handling
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Authored by edward-jones on Jun 17 2019, 4:52 AM.

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edward-jones created this revision.Jun 17 2019, 4:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 17 2019, 4:52 AM
edward-jones retitled this revision from [WIP][RISCV] Specify registers used for exception handling to [RISCV] Specify registers used for exception handling.
edward-jones edited the summary of this revision. (Show Details)

Added tests

asb requested changes to this revision.Jul 2 2019, 3:09 AM

Could you please add a riscv64 RUN line too, for completeness? Other archs seem to call the equivalent test file builtins-archname.c rather than builtin-archname.c, so I'd adjust the naming to match.

Then this looks good to me. Thanks!

This revision now requires changes to proceed.Jul 2 2019, 3:09 AM

Add riscv64 target run line, renamed test file to builtins-riscv.c, and rebased.

asb accepted this revision.Jul 3 2019, 5:09 AM

Thanks, looks good to me!

This revision is now accepted and ready to land.Jul 3 2019, 5:10 AM
asb added inline comments.Jul 3 2019, 5:11 AM
test/CodeGen/builtins-riscv.c
4 ↗(On Diff #207736)

Nit: having { on this line would be more consistent with usual LLVM style

asb added a comment.Jul 3 2019, 6:12 AM

Ed, if you haven't already could you request commit access so you can commit these approved patches yourself? See https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access for details.

This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 8 2019, 2:38 AM