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[RISCV] Specify registers used in DWARF exception handling
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Authored by edward-jones on Jun 17 2019, 4:41 AM.

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Summary

Defines RISCV registers for getExceptionPointerRegister() and getExceptionSelectorRegister()

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rL LLVM

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edward-jones created this revision.Jun 17 2019, 4:41 AM
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edward-jones retitled this revision from [WIP][RISCV] Specify registers used in DWARF exception handling to [RISCV] Specify registers used in DWARF exception handling.
edward-jones edited the summary of this revision. (Show Details)

Rebased against master

asb added a comment.Jun 20 2019, 4:57 AM

Thanks for the patch! Do you have a reference for these being the appropriate values?

In D63411#1551719, @asb wrote:

Thanks for the patch! Do you have a reference for these being the appropriate values?

I based these values on what the GCC tool chain appears to do, but now after searching around I can't find any documentation saying what the correct values should be. I had assumed that this would be written in the ABI documentation (https://github.com/riscv/riscv-elf-psabi-doc (?)) but I can't see any mention there.

In D63411#1551719, @asb wrote:

Thanks for the patch! Do you have a reference for these being the appropriate values?

I had an old patch that also implemented this and the registers match this patch. It's been over an year so I'm no longer sure where I dug up the information (maybe binutils), but the fact that it matches is good evidence that this is correct, although it would be nice leaving a source here in the review for future reference.

asb requested changes to this revision.EditedJul 1 2019, 7:20 AM

It looks like docs/ExceptionHandling.rst documents that for most targets, the registers are the same as the calling convention GPRs.

Ed, can you please update with a test? You should be able to copy test/Transforms/CallSiteSplitting/lpad.ll to something like test/CodeGen/RISCV/exception-pointer-register.ll then add riscv32 and riscv64 RUN lines and a comment that this test asserted prior to getExceptionPointerRegister and getExceptionSelectorRegister being implemented.

This revision now requires changes to proceed.Jul 1 2019, 7:20 AM

Added test, rebased.

asb accepted this revision.Jul 3 2019, 6:16 AM

I think you might as well add RV32 and RV64 CHECK prefixes and put the test through update_llc_test_checks.py to ensure the generated code is sane, but with that change this is good to land. Thanks!

This revision is now accepted and ready to land.Jul 3 2019, 6:16 AM
This revision was automatically updated to reflect the committed changes.