[globalisel][legalizer] Combine G_TRUNC+G_MERGE_VALUES in artifact combiner

[dsanders]

Summary

This has a fairly good chance of killing off significant amounts of dead
code when narrowScalar() is used to legalize certain instructions since
it removes vestigial uses of the upper component of a G_MERGE_VALUES that
may not contribute to the final value. For example, a sequence of s128
operations narrowScalar'd to s64 that ends in a truncation to s64 can
discard all the operations for the upper s64. As they are no longer
kept alive by the use of the lower s64.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

430

No else after return

431

Aren't these both required to be scalars anyway? If a vector is involved you have to use G_CONCAT_VECTOR or G_BUILD_VECTOR

[dsanders]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

431

Good point. I'd forgotten we had split vectors out

[dsanders]

G_MERGE_VALUES always has scalars
Fixed a else after return

[arsenm]

LGTM with nit

llvm/unittests/CodeGen/GlobalISel/LegalizerArtifactCombinerTest.cpp

88

EXPECT_EQ(0, .size())

127

EXPECT_EQ(0, .size())

[Petar.Avramovic]

Patch alone looks good.
I'm just coming from D61787, hopefully it shouldn't be to complicated to make them both work together.
Also targets does not have to define any legalization rules for this combine to work which is great.

In D61787 I mentioned that it might be easier for artifact combiner if this was handled with adding narrow scalar rule for G_TRUNC(G_UNMERGE+COPY) and allowing combiner to finish with combining G_UNMERGE/G_MERGE.
What do you think is better in the sense that we also want to allow legalization of chained artifacts?

Now we have G_SEXT/G_TRUNC combine and G_TRUNC/G_UNMERGE_VALUES, which one should happen first in a sequence like this?

%2:_(s128) = G_MERGE_VALUES %0:_(s64), %1:_(s64) 
%3:_(s64) = G_TRUNC %2(s128)
%4:_(s128) = G_SEXT %3:_(s64)
  . . .   = G_UNMERGE_VALUES %4:_(s128)

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

321–325

Uncombined G_UNMERGE/G_MERGE pair.

[dsanders]

Rebased to master

[dsanders]

Rebase
Note: The addition of s128 G_LOAD/G_STORE to AArch64's made test_inserts_[123] from test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir unusable so they are only tested in LegalizerArtifactCombinerTest.cpp now

[arsenm]

This looks like it's done already on master?

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

bool tryCombineExtract(MachineInstr &MI,
     Builder.buildExtract(
       MI.getOperand(0).getReg(),
       MergeI->getOperand(MergeSrcIdx + 1).getReg(),
       Offset - MergeSrcIdx * MergeSrcSize);
     markInstAndDefDead(MI, *MergeI, DeadInsts);
     return true;
   }
 
+  bool tryCombineTrunc(MachineInstr &MI,
+                       SmallVectorImpl<MachineInstr *> &DeadInsts,
+                       GISelChangeObserver &Observer) {
+    if (MI.getOpcode() != TargetOpcode::G_TRUNC)
+      return false;
+
+    // Attempt to combine:
+    //   %2 = G_MERGE_VALUES %0, %1
+    //   %3 = G_TRUNC %2
+    //   ... = ... %3
+    // to this when %0 and %3 are the same type:
+    //   ... = ... %0
+    // or to this when %0 and %3 are scalars and %3 is smaller:
+    //   %3 = G_TRUNC %0
+    //   ... = ... %3
+    // There are other possibilities but this should cover the common ones.
+    unsigned DstReg = MI.getOperand(0).getReg();
+    LLT DstTy = MRI.getType(DstReg);
+    unsigned DefReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
+    MachineInstr *DefMI = MRI.getVRegDef(DefReg);
+    if (!DefMI)
+      return false;
+    if (DefMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) {
+      Register OriginReg = DefMI->getOperand(1).getReg();
+      LLT OriginTy = MRI.getType(OriginReg);
+      Builder.setInstr(MI);
+      if (DstTy == OriginTy) {
+        if (MRI.constrainRegAttrs(DstReg, OriginReg))
+          MRI.replaceRegWith(OriginReg, DstReg);
+        else {
+          Builder.buildCopy(DstReg, OriginReg);
+        }
+        markInstAndDefDead(MI, *DefMI, DeadInsts);
+        return true;
+      }
+      if (DstTy.getSizeInBits() < OriginTy.getSizeInBits()) {
+        assert(DstTy.isScalar() && OriginTy.isScalar() &&
+               "G_MERGE_VALUES with non-scalar?");
+        Builder.buildTrunc(DstReg, OriginReg);
+        markInstAndDefDead(MI, *DefMI, DeadInsts);
+        return true;
+      }
+    }
+    return false;
+  }
+
   /// Try to combine away MI.
   /// Returns true if it combined away the MI.
   /// Adds instructions that are dead as a result of the combine
   /// into DeadInsts, which can include MI.
   bool tryCombineInstruction(MachineInstr &MI,
                              SmallVectorImpl<MachineInstr *> &DeadInsts,
                              GISelObserverWrapper &WrapperObserver) {
     // This might be a recursive call, and we might have DeadInsts already
case TargetOpcode::G_ZEXT:
       return tryCombineZExt(MI, DeadInsts);
     case TargetOpcode::G_SEXT:
       return tryCombineSExt(MI, DeadInsts);
     case TargetOpcode::G_UNMERGE_VALUES:
       return tryCombineMerges(MI, DeadInsts);
     case TargetOpcode::G_EXTRACT:
       return tryCombineExtract(MI, DeadInsts);
     case TargetOpcode::G_TRUNC: {
-      bool Changed = false;
+      bool Changed = tryCombineTrunc(MI, DeadInsts, WrapperObserver);
       for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
         Changed |= tryCombineInstruction(Use, DeadInsts, WrapperObserver);
       return Changed;
     }
     }
   }
 
 private:

llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test_inserts_nonpow2() { ret void }
+  define void @test_inserts_4() { ret void }
+  define void @test_inserts_5() { ret void }
+  define void @test_inserts_6() { ret void }
 ...
 
 ---
 name:            test_inserts_nonpow2
 body: |
   bb.0:
     liveins: $x0, $x1, $x2
 
 
     ; CHECK-LABEL: name: test_inserts_nonpow2
     ; CHECK: [[C:%[0-9]+]]:_(s64) = COPY $x3
     ; CHECK: $x0 = COPY [[C]]
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s64) = COPY $x3
     %4:_(s192) = G_MERGE_VALUES %0, %1, %2
     %5:_(s192) = G_INSERT %4, %3, 0
     %6:_(s64), %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %5
     $x0 = COPY %6
     RET_ReallyLR
 ...
+
+---
+name:            test_inserts_4
+body: |
+  bb.0:
+    liveins: $w0
+
+      ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair.
+    ; CHECK-LABEL: name: test_inserts_4
+    ; CHECK: [[VALEXT:%[0-9]+]]:_(s32) = COPY %2(s32)
+    ; CHECK: [[VAL:%[0-9]+]]:_(s32) = G_INSERT [[VALEXT]], %1(s1), 0
+    ; CHECK: %5:_(s8) = G_TRUNC [[VAL]](s32)
+    %4:_(s32) = COPY $w0
+    %0:_(s1) = G_TRUNC %4
+    %5:_(s32) = COPY $w1
+    %1:_(s8) = G_TRUNC %5
+    %2:_(p0) = COPY $x2
+    %3:_(s8) = G_INSERT %1(s8), %0(s1), 0
+    G_STORE %3(s8), %2(p0) :: (store 1)
+    RET_ReallyLR
+...
+
+---
+name:            test_inserts_5
+body: |
+  bb.0:
+    liveins: $x0, $x1, $x2
+
+
+    ; CHECK-LABEL: name: test_inserts_5
+    ; CHECK: [[INS_LO:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 0
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, [[INS_LO]](s32), 32
+    ; CHECK: [[INS_HI:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 32
+    ; This instruction is dead but it was already processed by the legalizer
+    ; and as such it didn't notice. The next pass will delete it.
+    ; CHECK: [[VAL_HI:%[0-9]+]]:_(s64) = G_INSERT %1, [[INS_HI]](s32), 0
+    ; CHECK: $x0 = COPY [[VAL_LO]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = COPY $x1
+    %2:_(s64) = COPY $x2
+    %3:_(s128) = G_MERGE_VALUES %0, %1
+    %4:_(s128) = G_INSERT %3, %2, 32
+    %5:_(s64) = G_TRUNC %4
+    $x0 = COPY %5
+    RET_ReallyLR
+...
+
+---
+name:            test_inserts_6
+body: |
+  bb.0:
+    liveins: $x0, $x1, $x2
+
+
+    ; CHECK-LABEL: name: test_inserts_6
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, %2(s32), 32
+    ; CHECK: $x0 = COPY [[VAL_LO]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = COPY $x1
+    %2:_(s32) = COPY $w2
+    %3:_(s128) = G_MERGE_VALUES %0, %1
+    %4:_(s128) = G_INSERT %3, %2, 32
+    %5:_(s64) = G_TRUNC %4
+    $x0 = COPY %5
+    RET_ReallyLR
+...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=aarch64 -run-pass=legalizer -O0 %s -o - | FileCheck %s
 ---
 name:            test_implicit_def
 body: |
   bb.0.entry:
     liveins:
 
     ; CHECK-LABEL: name: test_implicit_def
     ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
     ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
-    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
-    ; CHECK: $x0 = COPY [[TRUNC]](s64)
+    ; CHECK: $x0 = COPY [[DEF]](s64)
     %0:_(s128) = G_IMPLICIT_DEF
     %1:_(s64) = G_TRUNC %0(s128)
     $x0 = COPY %1(s64)
 ...
 
 ---
 name: test_implicit_def_s3
 body: |

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir

bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
     ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
     ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64)
     ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
     ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
+    ; This instruction is dead but it was already processed by the legalizer
+    ; and as such it didn't notice. The next pass will delete it.
     ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
-    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
-    ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s33) = G_TRUNC %0
     %2:_(s33) = G_CTLZ_ZERO_UNDEF %1
     %3:_(s64) = G_ANYEXT %2
     $vgpr0_vgpr1 = COPY %3
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir

bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
     ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
     ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s64)
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64)
     ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
     ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
+    ; This instruction is dead but it was already processed by the legalizer
+    ; and as such it didn't notice. The next pass will delete it.
     ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
-    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
-    ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]]
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s33) = G_TRUNC %0
     %2:_(s33) = G_CTLZ %1
     %3:_(s64) = G_ANYEXT %2
     $vgpr0_vgpr1 = COPY %3
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

bb.0:
     ; CHECK-LABEL: name: test_unmerge_s1_s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[COPY]](s32)
     ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
     ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
     ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
     ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)
     ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
-    ; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C2]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV1]](s128)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
     ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
     ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
     ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C3]]
     ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC]]
     ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C3]]
     ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C4]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
     ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
     ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB1]](s32)
     ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
     ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB]](s32)
     ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C1]]
     ; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
     ; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV3]], [[SELECT1]]
     ; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
     ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[UV4]], [[SELECT]]
     ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[UV5]], [[SELECT2]]
     ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
-    ; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C5]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV2]](s128)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C5]](s64)
     ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC1]], [[C3]]
     ; CHECK: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC1]]
     ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC1]](s32), [[C3]]
     ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC1]](s32), [[C4]]
     ; CHECK: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32)
     ; CHECK: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32)
     ; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[SUB3]](s32)
     ; CHECK: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
     ; CHECK: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[SUB2]](s32)
     ; CHECK: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C1]]
     ; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR3]], [[SHL5]]
     ; CHECK: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[OR2]], [[SELECT4]]
     ; CHECK: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SELECT3]]
     ; CHECK: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[SELECT5]]
     ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
-    ; CHECK: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C6]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s128)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C6]](s64)
     ; CHECK: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC2]], [[C3]]
     ; CHECK: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC2]]
     ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC2]](s32), [[C3]]
     ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC2]](s32), [[C4]]
     ; CHECK: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32)
     ; CHECK: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32)
     ; CHECK: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[SUB5]](s32)
     ; CHECK: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL7]], [[LSHR2]]
     ; CHECK: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[SUB4]](s32)
     ; CHECK: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL6]], [[C1]]
     ; CHECK: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR6]], [[SHL8]]
     ; CHECK: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[OR5]], [[SELECT7]]
     ; CHECK: [[OR7:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[SELECT6]]
     ; CHECK: [[OR8:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[SELECT8]]
     ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
-    ; CHECK: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C7]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MV4]](s128)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C7]](s64)
     ; CHECK: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[C3]]
     ; CHECK: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC3]]
     ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC3]](s32), [[C3]]
     ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC3]](s32), [[C4]]
     ; CHECK: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32)
     ; CHECK: [[SHL10:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32)
     ; CHECK: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR7]], [[SUB7]](s32)
     ; CHECK: [[OR9:%[0-9]+]]:_(s64) = G_OR [[SHL10]], [[LSHR3]]
     ; CHECK: [[SHL11:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[SUB6]](s32)
     ; CHECK: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL9]], [[C1]]
     ; CHECK: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR9]], [[SHL11]]
     ; CHECK: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[OR8]], [[SELECT10]]
     ; CHECK: [[OR10:%[0-9]+]]:_(s64) = G_OR [[OR7]], [[SELECT9]]
     ; CHECK: [[OR11:%[0-9]+]]:_(s64) = G_OR [[OR8]], [[SELECT11]]
     ; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 75
-    ; CHECK: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C8]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[MV5]](s128)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[C8]](s64)
     ; CHECK: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[TRUNC4]], [[C3]]
     ; CHECK: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC4]]
     ; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC4]](s32), [[C3]]
     ; CHECK: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC4]](s32), [[C4]]
     ; CHECK: [[SHL12:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32)
     ; CHECK: [[SHL13:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32)
     ; CHECK: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR10]], [[SUB9]](s32)
     ; CHECK: [[OR12:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[LSHR4]]
     ; CHECK: [[SHL14:%[0-9]+]]:_(s64) = G_SHL [[OR10]], [[SUB8]](s32)
     ; CHECK: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL12]], [[C1]]
     ; CHECK: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR12]], [[SHL14]]
     ; CHECK: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[OR11]], [[SELECT13]]
     ; CHECK: [[OR13:%[0-9]+]]:_(s64) = G_OR [[OR10]], [[SELECT12]]
     ; CHECK: [[OR14:%[0-9]+]]:_(s64) = G_OR [[OR11]], [[SELECT14]]
     ; CHECK: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 90
-    ; CHECK: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C9]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[MV6]](s128)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[C9]](s64)
     ; CHECK: [[SUB10:%[0-9]+]]:_(s32) = G_SUB [[TRUNC5]], [[C3]]
     ; CHECK: [[SUB11:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC5]]
     ; CHECK: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC5]](s32), [[C3]]
     ; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC5]](s32), [[C4]]
     ; CHECK: [[SHL15:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32)
     ; CHECK: [[SHL16:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32)
     ; CHECK: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR13]], [[SUB11]](s32)
     ; CHECK: [[OR15:%[0-9]+]]:_(s64) = G_OR [[SHL16]], [[LSHR5]]
     ; CHECK: [[SHL17:%[0-9]+]]:_(s64) = G_SHL [[OR13]], [[SUB10]](s32)
     ; CHECK: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[SHL15]], [[C1]]
     ; CHECK: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[OR15]], [[SHL17]]
     ; CHECK: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP11]](s1), [[OR14]], [[SELECT16]]
     ; CHECK: [[OR16:%[0-9]+]]:_(s64) = G_OR [[OR13]], [[SELECT15]]
     ; CHECK: [[OR17:%[0-9]+]]:_(s64) = G_OR [[OR14]], [[SELECT17]]
     ; CHECK: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 105
-    ; CHECK: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C10]](s64), [[C1]](s64)
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[MV7]](s128)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[C10]](s64)
     ; CHECK: [[SUB12:%[0-9]+]]:_(s32) = G_SUB [[TRUNC6]], [[C3]]
     ; CHECK: [[SUB13:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC6]]
     ; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC6]](s32), [[C3]]
     ; CHECK: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC6]](s32), [[C4]]
     ; CHECK: [[SHL18:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32)
     ; CHECK: [[SHL19:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32)
     ; CHECK: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR16]], [[SUB13]](s32)
     ; CHECK: [[OR18:%[0-9]+]]:_(s64) = G_OR [[SHL19]], [[LSHR6]]

llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   ${LLVM_TARGETS_TO_BUILD}
   CodeGen
   Core
   GlobalISel
   MC
   MIRParser
   Support
   Target
   )
 
 add_llvm_unittest(GlobalISelTests
   CSETest.cpp
   LegalizerHelperTest.cpp
   LegalizerInfoTest.cpp
+  LegalizerArtifactCombinerTest.cpp
   MachineIRBuilderTest.cpp
   GISelMITest.cpp
   PatternMatchTest.cpp
   KnownBitsTest.cpp
   )

llvm/unittests/CodeGen/GlobalISel/GISelMITest.h

 ---
 ...
 name: func
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
 body: |
   bb.1:
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = COPY $x2
+    %3(s32) = COPY $w3
+    %4(s32) = COPY $w4
+    %5(s32) = COPY $w5
 )MIR") + Twine(MIRFunc) + Twine("...\n"))
                             .toNullTerminatedStringRef(S);
   std::unique_ptr<MIRParser> MIR;
   auto MMI = make_unique<MachineModuleInfo>(&TM);
   std::unique_ptr<Module> M =
       parseMIR(Context, MIR, TM, MIRString, "func", *MMI);
   return make_pair(std::move(M), std::move(MMI));
 }

llvm/unittests/CodeGen/GlobalISel/LegalizerArtifactCombinerTest.cpp

+//===- LegalizerHelperTest.cpp
+//-----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "GISelMITest.h"
+#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
+
+namespace {
+
+class DummyGISelObserver : public GISelChangeObserver {
+public:
+  void changingInstr(MachineInstr &MI) override {}
+  void changedInstr(MachineInstr &MI) override {}
+  void createdInstr(MachineInstr &MI) override {}
+  void erasingInstr(MachineInstr &MI) override {}
+};
+
+TEST_F(GISelMITest, MergeUnmerge) {
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(A, {});
+  // Build Instr
+  MachineInstr *MI0 = B.buildInstr(TargetOpcode::G_MERGE_VALUES,
+                                   {LLT::scalar(128)}, {Copies[0], Copies[1]});
+  MachineInstr *MI1 = B.buildInstr(TargetOpcode::G_UNMERGE_VALUES,
+                                   {LLT::scalar(64), LLT::scalar(64)},
+                                   {MI0->getOperand(0).getReg()});
+  B.buildInstr(TargetOpcode::COPY,
+               {MRI->getVRegDef(Copies[2])->getOperand(1).getReg()},
+               {MI1->getOperand(0).getReg()});
+
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  ArrayRef<GISelChangeObserver *> Observers = {&Observer};
+  GISelObserverWrapper ObserverWrapper(Observers);
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), Info);
+  // Perform Legalization
+  SmallVector<MachineInstr *, 4> DeadInstructions;
+  EXPECT_TRUE(ArtCombiner.tryCombineInstruction(*MI1, DeadInstructions, ObserverWrapper));
+  EXPECT_TRUE(DeadInstructions.size() == 2);
+  for (auto *DeadMI : DeadInstructions) {
+    LLVM_DEBUG(dbgs() << *DeadMI << "Is dead\n");
+    DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
+  }
+
+  auto CheckStr = R"(
+  CHECK: [[T0:%[0-9]+]]:_(s64) = COPY $x0
+  CHECK: $x2 = COPY [[T0]]
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+TEST_F(GISelMITest, MergeTrunc1) {
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(A, {});
+  // Build Instr
+  MachineInstr *MI0 = B.buildInstr(TargetOpcode::G_MERGE_VALUES,
+                                   {LLT::scalar(128)}, {Copies[0], Copies[1]});
+  MachineInstr *MI1 = B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(64)},
+                                   {MI0->getOperand(0).getReg()});
+  B.buildInstr(TargetOpcode::COPY,
+               {MRI->getVRegDef(Copies[2])->getOperand(1).getReg()},
+               {MI1->getOperand(0).getReg()});
+
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  ArrayRef<GISelChangeObserver *> Observers = {&Observer};
+  GISelObserverWrapper ObserverWrapper(Observers);
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), Info);
+  // Perform Legalization
+  SmallVector<MachineInstr *, 4> DeadInstructions;
+  EXPECT_TRUE(ArtCombiner.tryCombineInstruction(*MI1, DeadInstructions, ObserverWrapper));
+  EXPECT_TRUE(DeadInstructions.size() == 0);
+  for (auto *DeadMI : DeadInstructions) {
+    LLVM_DEBUG(dbgs() << *DeadMI << "Is dead\n");
+    DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
+  }
+
+  auto CheckStr = R"(
+  CHECK: [[T0:%[0-9]+]]:_(s64) = COPY $x0
+  CHECK: $x2 = COPY [[T0]]
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+TEST_F(GISelMITest, MergeTrunc2) {
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(A, {});
+  // Build Instr
+  MachineInstr *MI0 = B.buildInstr(TargetOpcode::G_MERGE_VALUES,
+                                   {LLT::scalar(128)}, {Copies[0], Copies[1]});
+  MachineInstr *MI1 = B.buildInstr(TargetOpcode::G_TRUNC, {LLT::scalar(32)},
+                                   {MI0->getOperand(0).getReg()});
+  B.buildInstr(TargetOpcode::COPY,
+               {MRI->getVRegDef(Copies[3])->getOperand(1).getReg()},
+               {MI1->getOperand(0).getReg()});
+
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  ArrayRef<GISelChangeObserver *> Observers = {&Observer};
+  GISelObserverWrapper ObserverWrapper(Observers);
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), Info);
+  // Perform Legalization
+  SmallVector<MachineInstr *, 4> DeadInstructions;
+  EXPECT_TRUE(ArtCombiner.tryCombineInstruction(*MI1, DeadInstructions, ObserverWrapper));
+  EXPECT_TRUE(DeadInstructions.size() == 0);
+  for (auto *DeadMI : DeadInstructions) {
+    errs() << *DeadMI << "Is dead\n";
+    DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
+  }
+
+  auto CheckStr = R"(
+  CHECK: [[T0:%[0-9]+]]:_(s64) = COPY $x0
+  CHECK: [[T1:%[0-9]+]]:_(s32) = G_TRUNC [[T0]]
+  CHECK: $w3 = COPY [[T1]]
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+} // namespace