[AArch64] Handle ISD::LRINT and ISD::LLRINT

[zatrazz]

Summary

This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.

This patch depends on https://reviews.llvm.org/D62017.

[zatrazz]

Ping now that both D62017 and D62019 have been approved.

[mstorsjo]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3159 ↗

(On Diff #199864)

Please add patterns for returning i32 as well; the original C standard math function, which is turned into the llvm IR intrinsic, returns long, which is 32 bit on windows platforms. See D62108 for a fix for the same for lround.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3159 ↗

(On Diff #199864)

And also a pattern for (lrint f16)?

[zatrazz]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3159 ↗

(On Diff #199864)

I plan to address lrint and lround for f16 in a subsequent patch.

[zatrazz]

Updated patch based on previous comments. Add a pattern to handle i32 return and a testcase for Windows.

[zatrazz]

Is this patch ok with windows support now?

[zatrazz]

Ping.

[mstorsjo]

In D62018#1513546, @zatrazz wrote:

Is this patch ok with windows support now?

Sorry, I was away for a bit. Yes, it looks good wrt Windows now - thanks for taking the time to fix it!

llvm/trunk/include/llvm/Target/TargetSelectionDAG.td

 def ftrunc     : SDNode<"ISD::FTRUNC"     , SDTFPUnaryOp>;
 def fceil      : SDNode<"ISD::FCEIL"      , SDTFPUnaryOp>;
 def ffloor     : SDNode<"ISD::FFLOOR"     , SDTFPUnaryOp>;
 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
 def fround     : SDNode<"ISD::FROUND"     , SDTFPUnaryOp>;
 
 def lround     : SDNode<"ISD::LROUND"     , SDTFPToIntOp>;
 def llround    : SDNode<"ISD::LLROUND"    , SDTFPToIntOp>;
+def lrint      : SDNode<"ISD::LRINT"      , SDTFPToIntOp>;
+def llrint     : SDNode<"ISD::LLRINT"     , SDTFPToIntOp>;
 
 def fpround    : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fpextend   : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
 def fcopysign  : SDNode<"ISD::FCOPYSIGN"  , SDTFPSignOp>;
 
 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

for (MVT Ty : {MVT::f32, MVT::f64}) {
     setOperationAction(ISD::FTRUNC, Ty, Legal);
     setOperationAction(ISD::FROUND, Ty, Legal);
     setOperationAction(ISD::FMINNUM, Ty, Legal);
     setOperationAction(ISD::FMAXNUM, Ty, Legal);
     setOperationAction(ISD::FMINIMUM, Ty, Legal);
     setOperationAction(ISD::FMAXIMUM, Ty, Legal);
     setOperationAction(ISD::LROUND, Ty, Legal);
     setOperationAction(ISD::LLROUND, Ty, Legal);
+    setOperationAction(ISD::LRINT, Ty, Legal);
+    setOperationAction(ISD::LLRINT, Ty, Legal);
   }
 
   if (Subtarget->hasFullFP16()) {
     setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal);
     setOperationAction(ISD::FFLOOR,  MVT::f16, Legal);
     setOperationAction(ISD::FCEIL,   MVT::f16, Legal);
     setOperationAction(ISD::FRINT,   MVT::f16, Legal);
     setOperationAction(ISD::FTRUNC,  MVT::f16, Legal);

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 
 let Predicates = [HasFRInt3264] in {
   defm FRINT32Z : FRIntNNT<0b00, "frint32z">;
   defm FRINT64Z : FRIntNNT<0b10, "frint64z">;
   defm FRINT32X : FRIntNNT<0b01, "frint32x">;
   defm FRINT64X : FRIntNNT<0b11, "frint64x">;
 } // HasFRInt3264
 
+def : Pat<(i32 (lrint f32:$Rn)),
+          (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i32 (lrint f64:$Rn)),
+          (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (lrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (lrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (llrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (llrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+
 //===----------------------------------------------------------------------===//
 // Floating point two operand instructions.
 //===----------------------------------------------------------------------===//
 
 defm FADD   : TwoOperandFPData<0b0010, "fadd", fadd>;
 let SchedRW = [WriteFDiv] in {
 defm FDIV   : TwoOperandFPData<0b0001, "fdiv", fdiv>;
 }

llvm/trunk/test/CodeGen/AArch64/llrint-conv.ll

 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-nEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswl:
 ; CHECK:       bl      llrintl

llvm/trunk/test/CodeGen/AArch64/lrint-conv-win.ll

+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       frintx  [[SREG:s[0-9]+]], s0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT:  sxtw    x0, [[WREG]]
+; CHECK-NEXT:  ret
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK:       frintx  [[SREG:s[0-9]+]], s0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT:  ret
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       frintx  [[DREG:d[0-9]+]], d0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT:  sxtw    x0, [[WREG]]
+; CHECK-NEXT:  ret
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       frintx  [[DREG:d[0-9]+]], d0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT:  ret
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
+declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/lrint-conv.ll

 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
   ret i64 %0
 }
 
 ; CHECK-LABEL: testmswl:
 ; CHECK:       bl      lrintl