[X86] Support .reloc *, R_{386,X86_64}_NONE, *

[MaskRay]

Summary

This can be used to create references among sections. When --gc-sections
is used, the referenced section will be retained if the origin section
is retained.

See R_MIPS_NONE (D13659), R_ARM_NONE (D61992), R_AARCH64_NONE (D61973) for similar changes.

[rnk]

lgtm

This morning I didn't know why this was interesting, but then @inglorion told me about the new .init_array + reloc-none GC sections strategy. I still have concerns about dropping debug info as LLD is doing now, but I'll pass them along separately.

[pcc]

lib/Target/X86/MCTargetDesc/X86FixupKinds.h

17 ↗

(On Diff #199848)

The comment isn't accurate.

Should this be a generic fixup kind (i.e. MCFixupKind)? It seems that both ELF and COFF support it on all targets.

[MaskRay]

.init_array+R_*_NONE is a missed optimization in linkers (ld.bfd+gold+lld) but I'm not sure how useful it is. It may break semantics and I think usually it indicates real bugs, see PR41693 for a recent issue.

This is interesting as I want Android guys to use a better workaround than the current PT_TLS hack in lld ELF ARM/AArch64. (https://reviews.llvm.org/D61824#1500063)

@pcc told me this trick long ago and mentioned .reloc is not supported in llvm:) The trick is also mentioned on https://lwn.net/Articles/741494/

The R_386_NONE support can be used to add tests for a bug in lld that I want to fix https://reviews.llvm.org/D61973#1504227

lib/Target/X86/MCTargetDesc/X86FixupKinds.h

17 ↗

(On Diff #199848)

Thanks for pointing this out.

I'll add a generic fixup in the ARM patch D61992.

[MaskRay]

Use generic FK_NONE

llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-static unsigned getFixupKindLog2Size(unsigned Kind) {
+static unsigned getFixupKindSize(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("invalid fixup kind!");
+  case FK_NONE:
+    return 0;
   case FK_PCRel_1:
   case FK_SecRel_1:
   case FK_Data_1:
-    return 0;
+    return 1;
   case FK_PCRel_2:
   case FK_SecRel_2:
   case FK_Data_2:
-    return 1;
+    return 2;
   case FK_PCRel_4:
   case X86::reloc_riprel_4byte:
   case X86::reloc_riprel_4byte_relax:
   case X86::reloc_riprel_4byte_relax_rex:
   case X86::reloc_riprel_4byte_movq_load:
   case X86::reloc_signed_4byte:
   case X86::reloc_signed_4byte_relax:
   case X86::reloc_global_offset_table:
   case X86::reloc_branch_4byte_pcrel:
   case FK_SecRel_4:
   case FK_Data_4:
-    return 2;
+    return 4;
   case FK_PCRel_8:
   case FK_SecRel_8:
   case FK_Data_8:
   case X86::reloc_global_offset_table8:
-    return 3;
+    return 8;
   }
 }
 
 namespace {
 
 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
                      bool HasRelocationAddend, bool foobar)
     : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
 };
 
 class X86AsmBackend : public MCAsmBackend {
   const MCSubtargetInfo &STI;
 public:
   X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
       : MCAsmBackend(support::little), STI(STI) {}
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
   }
 
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
+
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
         {"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
         {"reloc_riprel_4byte_movq_load", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
         {"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
         {"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
         {"reloc_signed_4byte", 0, 32, 0},
         {"reloc_signed_4byte_relax", 0, 32, 0},
         {"reloc_global_offset_table", 0, 32, 0},
         {"reloc_global_offset_table8", 0, 64, 0},
         {"reloc_branch_4byte_pcrel", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     };
 
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
 
     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
            "Invalid kind!");
     assert(Infos[Kind - FirstTargetFixupKind].Name && "Empty fixup name!");
     return Infos[Kind - FirstTargetFixupKind];
   }
 
+  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
+                             const MCValue &Target) override;
+
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override {
-    unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
+    unsigned Size = getFixupKindSize(Fixup.getKind());
 
     assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!");
 
     // Check that uppper bits are either all zeros or all ones.
     // Specifically ignore overflow/underflow as long as the leakage is
     // limited to the lower bits. This is to remain compatible with
     // other assemblers.
-    assert(isIntN(Size * 8 + 1, Value) &&
+    assert((Size == 0 || isIntN(Size * 8 + 1, Value)) &&
            "Value does not fit in the Fixup field");
 
     for (unsigned i = 0; i != Size; ++i)
       Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
   }
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;

 
 static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode) {
   unsigned R = getRelaxedOpcodeArith(Inst);
   if (R != Inst.getOpcode())
     return R;
   return getRelaxedOpcodeBranch(Inst, is16BitMode);
 }
 
+Optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
+  if (STI.getTargetTriple().isOSBinFormatELF()) {
+    if (STI.getTargetTriple().getArch() == Triple::x86_64) {
+      if (Name == "R_X86_64_NONE")
+        return FK_NONE;
+    } else {
+      if (Name == "R_386_NONE")
+        return FK_NONE;
+    }
+  }
+  return MCAsmBackend::getFixupKind(Name);
+}
+
+bool X86AsmBackend::shouldForceRelocation(const MCAssembler &,
+                                          const MCFixup &Fixup,
+                                          const MCValue &) {
+  return Fixup.getKind() == FK_NONE;
+}
+
 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst,
                                       const MCSubtargetInfo &STI) const {
   // Branches can always be relaxed in either mode.
   if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode())
     return true;
 
   // Check if this instruction is ever relaxable.
   if (getRelaxedOpcodeArith(Inst) == Inst.getOpcode())

llvm/trunk/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp

 X86ELFObjectWriter::X86ELFObjectWriter(bool IsELF64, uint8_t OSABI,
                                        uint16_t EMachine)
     : MCELFObjectTargetWriter(IsELF64, OSABI, EMachine,
                               // Only i386 and IAMCU use Rel instead of RelA.
                               /*HasRelocationAddend*/
                               (EMachine != ELF::EM_386) &&
                                   (EMachine != ELF::EM_IAMCU)) {}
 
-enum X86_64RelType { RT64_64, RT64_32, RT64_32S, RT64_16, RT64_8 };
+enum X86_64RelType { RT64_NONE, RT64_64, RT64_32, RT64_32S, RT64_16, RT64_8 };
 
 static X86_64RelType getType64(unsigned Kind,
                                MCSymbolRefExpr::VariantKind &Modifier,
                                bool &IsPCRel) {
   switch (Kind) {
   default:
     llvm_unreachable("Unimplemented");
+  case FK_NONE:
+    return RT64_NONE;
   case X86::reloc_global_offset_table8:
     Modifier = MCSymbolRefExpr::VK_GOT;
     IsPCRel = true;
     return RT64_64;
   case FK_Data_8:
     return RT64_64;
   case X86::reloc_signed_4byte:
   case X86::reloc_signed_4byte_relax:
static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
                                X86_64RelType Type, bool IsPCRel,
                                unsigned Kind) {
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
   case MCSymbolRefExpr::VK_None:
   case MCSymbolRefExpr::VK_X86_ABS8:
     switch (Type) {
+    case RT64_NONE:
+      if (Modifier == MCSymbolRefExpr::VK_None)
+        return ELF::R_X86_64_NONE;
+      llvm_unreachable("Unimplemented");
     case RT64_64:
       return IsPCRel ? ELF::R_X86_64_PC64 : ELF::R_X86_64_64;
     case RT64_32:
       return IsPCRel ? ELF::R_X86_64_PC32 : ELF::R_X86_64_32;
     case RT64_32S:
       return ELF::R_X86_64_32S;
     case RT64_16:
       return IsPCRel ? ELF::R_X86_64_PC16 : ELF::R_X86_64_16;
     case RT64_8:
       return IsPCRel ? ELF::R_X86_64_PC8 : ELF::R_X86_64_8;
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_GOT:
     switch (Type) {
     case RT64_64:
       return IsPCRel ? ELF::R_X86_64_GOTPC64 : ELF::R_X86_64_GOT64;
     case RT64_32:
       return IsPCRel ? ELF::R_X86_64_GOTPC32 : ELF::R_X86_64_GOT32;
     case RT64_32S:
     case RT64_16:
     case RT64_8:
+    case RT64_NONE:
       llvm_unreachable("Unimplemented");
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_GOTOFF:
     assert(Type == RT64_64);
     assert(!IsPCRel);
     return ELF::R_X86_64_GOTOFF64;
   case MCSymbolRefExpr::VK_TPOFF:
     assert(!IsPCRel);
     switch (Type) {
     case RT64_64:
       return ELF::R_X86_64_TPOFF64;
     case RT64_32:
       return ELF::R_X86_64_TPOFF32;
     case RT64_32S:
     case RT64_16:
     case RT64_8:
+    case RT64_NONE:
       llvm_unreachable("Unimplemented");
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_DTPOFF:
     assert(!IsPCRel);
     switch (Type) {
     case RT64_64:
       return ELF::R_X86_64_DTPOFF64;
     case RT64_32:
       return ELF::R_X86_64_DTPOFF32;
     case RT64_32S:
     case RT64_16:
     case RT64_8:
+    case RT64_NONE:
       llvm_unreachable("Unimplemented");
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_SIZE:
     assert(!IsPCRel);
     switch (Type) {
     case RT64_64:
       return ELF::R_X86_64_SIZE64;
     case RT64_32:
       return ELF::R_X86_64_SIZE32;
     case RT64_32S:
     case RT64_16:
     case RT64_8:
+    case RT64_NONE:
       llvm_unreachable("Unimplemented");
     }
     llvm_unreachable("unexpected relocation type!");
   case MCSymbolRefExpr::VK_TLSCALL:
     return ELF::R_X86_64_TLSDESC_CALL;
   case MCSymbolRefExpr::VK_TLSDESC:
     return ELF::R_X86_64_GOTPC32_TLSDESC;
   case MCSymbolRefExpr::VK_TLSGD:
case MCSymbolRefExpr::VK_GOTPCREL:
     case X86::reloc_riprel_4byte_relax_rex:
     case X86::reloc_riprel_4byte_movq_load:
       return ELF::R_X86_64_REX_GOTPCRELX;
     }
     llvm_unreachable("unexpected relocation type!");
   }
 }
 
-enum X86_32RelType { RT32_32, RT32_16, RT32_8 };
+enum X86_32RelType { RT32_NONE, RT32_32, RT32_16, RT32_8 };
 
 static X86_32RelType getType32(X86_64RelType T) {
   switch (T) {
+  case RT64_NONE:
+    return RT32_NONE;
   case RT64_64:
     llvm_unreachable("Unimplemented");
   case RT64_32:
   case RT64_32S:
     return RT32_32;
   case RT64_16:
     return RT32_16;
   case RT64_8:
     return RT32_8;
   }
   llvm_unreachable("unexpected relocation type!");
 }
 
 static unsigned getRelocType32(MCContext &Ctx,
                                MCSymbolRefExpr::VariantKind Modifier,
                                X86_32RelType Type, bool IsPCRel,
                                unsigned Kind) {
   switch (Modifier) {
   default:
     llvm_unreachable("Unimplemented");
   case MCSymbolRefExpr::VK_None:
   case MCSymbolRefExpr::VK_X86_ABS8:
     switch (Type) {
+    case RT32_NONE:
+      if (Modifier == MCSymbolRefExpr::VK_None)
+        return ELF::R_386_NONE;
+      llvm_unreachable("Unimplemented");
     case RT32_32:
       return IsPCRel ? ELF::R_386_PC32 : ELF::R_386_32;
     case RT32_16:
       return IsPCRel ? ELF::R_386_PC16 : ELF::R_386_16;
     case RT32_8:
       return IsPCRel ? ELF::R_386_PC8 : ELF::R_386_8;
     }
     llvm_unreachable("unexpected relocation type!");

llvm/trunk/test/MC/X86/reloc-directive-elf-32.s

+# RUN: llvm-mc -triple=i386-pc-linux-musl %s | FileCheck --check-prefix=PRINT %s
+
+# RUN: llvm-mc -filetype=obj -triple=i386-pc-linux-musl %s -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+# RUN: llvm-readelf -x .data %t | FileCheck --check-prefix=HEX %s
+
+# PRINT:      .reloc 2, R_386_NONE, .data
+# PRINT-NEXT: .reloc 1, R_386_NONE, foo+4
+# PRINT-NEXT: .reloc 0, R_386_NONE, 8
+
+# X86 relocations use the Elf32_Rel format. Addends are neither stored in the
+# relocation entries nor applied in the referenced locations.
+# CHECK:      0x2 R_386_NONE .data 0x0
+# CHECK-NEXT: 0x1 R_386_NONE foo 0x0
+# CHECK-NEXT: 0x0 R_386_NONE - 0x0
+
+# HEX: 0x00000000 00000000 00000000
+
+.text
+  ret
+  nop
+  nop
+  .reloc 2, R_386_NONE, .data
+  .reloc 1, R_386_NONE, foo+4
+  .reloc 0, R_386_NONE, 8
+
+.data
+.globl foo
+foo:
+  .long 0
+  .long 0

llvm/trunk/test/MC/X86/reloc-directive-elf-64.s

+# RUN: llvm-mc -triple=x86_64-pc-linux-musl %s | FileCheck --check-prefix=PRINT %s
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux-musl %s -o %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# PRINT:      .reloc 2, R_X86_64_NONE, .data
+# PRINT-NEXT: .reloc 1, R_X86_64_NONE, foo+4
+# PRINT-NEXT: .reloc 0, R_X86_64_NONE, 8
+
+# CHECK:      0x2 R_X86_64_NONE .data 0x0
+# CHECK-NEXT: 0x1 R_X86_64_NONE foo 0x4
+# CHECK-NEXT: 0x0 R_X86_64_NONE - 0x8
+
+.text
+  ret
+  nop
+  nop
+  .reloc 2, R_X86_64_NONE, .data
+  .reloc 1, R_X86_64_NONE, foo+4
+  .reloc 0, R_X86_64_NONE, 8
+
+.data
+.globl foo
+foo:
+  .word 0
+  .word 0