[AArch64] Support .reloc *, R_AARCH64_NONE, *

[MaskRay]

Summary

This can be used to create references among sections. When --gc-sections
is used, the referenced section will be retained if the origin section
is retained.

[MaskRay]

Forgot to add test...

[rprichard]

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

[MaskRay]

Discarded unintended lib/Target/ARM changes

[MaskRay]

In D61973#1504185, @rprichard wrote:

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

Sorry, lib/Target/ARM changed were unintended. I am indeed studying how to support R_ARM_NONE :)

[rprichard]

FWIW: I noticed that the binutils assembler's .reloc directive can reference an arbitrary symbol whereas with this patch, a .reloc directive referencing a label turns into a section reference. e.g.:

$ cat test.s
  nop
foo:
  nop
bar:
  .reloc bar, R_AARCH64_NONE, foo
  .reloc bar, R_AARCH64_NONE, .text + 8

$ clang test.s -target aarch64-linux-gnu -c && readelf -r test.o

Relocation section '.rela.text' at offset 0xc0 contains 2 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000008  000400000000 R_AARCH64_NONE    0000000000000000 .text + 4
000000000008  000400000000 R_AARCH64_NONE    0000000000000000 .text + 8

$ clang test.s -target aarch64-linux-gnu -c -fno-integrated-as && readelf -r test.o

Relocation section '.rela.text' at offset 0x100 contains 2 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000008  000500000000 R_AARCH64_NONE    0000000000000004 foo + 0
000000000008  000100000000 R_AARCH64_NONE    0000000000000000 .text + 8

I see the same difference with the MIPS LLVM backend versus /usr/bin/mipsel-linux-gnu-as, so this is probably fine. I think referencing a section would be sufficient for the crtbegin usage described in D61825.

[MaskRay]

Set shouldForceRelocation to allow 0 symbol index, e.g. .reloc 0, R_AARCH64_NONE, 8

[peter.smith]

I have similar comments to D61992

In D61973#1504196, @MaskRay wrote:

In D61973#1504185, @rprichard wrote:

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

Sorry, lib/Target/ARM changed were unintended. I am indeed studying how to support R_ARM_NONE :)

I think Ryan has found a different problem here. My first thought was that R_ARM_NONE and R_AARCH64_NONE are supported in LLD as they map to R_NONE. In general LLD filters these out so they never get to relocateOne. It seems like there is a possibility of this happening with ld -r if the R_ARM_NONE is from a SHF_ALLOC section. In short the unrecognized reloc 0 is coming from relocateOne. The error seems to be specific to ARM, or at least to REL and not RELA as AArch64 and x86_64 -r work.

[peter.smith]

I think the ld -r failure with arm is due to InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) in particular:

if (RelTy::IsRela)
        P->r_addend = Sym.getVA(Addend) - Section->getOutputSection()->Addr;
      else if (Config->Relocatable)
        Sec->Relocations.push_back({R_ABS, Type, Rel.r_offset, Addend, &Sym});

If we add a R_ABS with Type R_ARM_NONE then relocateOne will try to evaluate it and hence we get the unrecognized reloc error. My intuition is to skip adding the R_ABS when the relocation is the None relocation. I'm not going to get a chance to send a patch to fix it today though.

[peter.smith]

To get back to this patch. I think the non-bigendian comments I made on D61992 apply here as well. Generally looks good. Will be worth checking that the format is ELF before accepting R_AARCH64_NONE.

I checked what GNU as does about the ILP32 status as the code R_AARCH64_P32_NONE is also defined to be 0. Having said that it seems like GNU as will only accept R_AARCH64_NONE in both ilp32 and ilp64 modes and won't accept R_AARCH64_P32_NONE so I think what we have here is fine.

[MaskRay]

Improve the tests as peter.smith suggested in the ARM patch.

[peter.smith]

Thanks, looks good to me. Will be worth seeing if there are any further comments from the US Timezone.

[MaskRay]

In D61973#1504710, @peter.smith wrote:

I think the ld -r failure with arm is due to InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) in particular:

if (RelTy::IsRela)
        P->r_addend = Sym.getVA(Addend) - Section->getOutputSection()->Addr;
      else if (Config->Relocatable)
        Sec->Relocations.push_back({R_ABS, Type, Rel.r_offset, Addend, &Sym});

If we add a R_ABS with Type R_ARM_NONE then relocateOne will try to evaluate it and hence we get the unrecognized reloc error. My intuition is to skip adding the R_ABS when the relocation is the None relocation. I'm not going to get a chance to send a patch to fix it today though.

Probably just use

-      else if (Config->Relocatable)
+      else if (Config->Relocatable && Type != Target->NoneRel)

After .reloc *, R_386_NONE, * is supported, probably change relocation-none-i686.test (yaml2obj) to an assembly test and check ld.lld -r doesn't crash...

[MaskRay]

Use generic FK_NONE

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

public:
   AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
       : MCAsmBackend(IsLittleEndian ? support::little : support::big),
         TheTriple(TT) {}
 
   unsigned getNumFixupKinds() const override {
     return AArch64::NumTargetFixupKinds;
   }
 
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
+
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
         // This table *must* be in the order that the fixup_* kinds are defined
         // in AArch64FixupKinds.h.
         //
         // Name                           Offset (bits) Size (bits)     Flags
         {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
         {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},

 } // end anonymous namespace
 
 /// The number of bytes the fixup may change.
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
 
+  case FK_NONE:
   case AArch64::fixup_aarch64_tlsdesc_call:
     return 0;
 
   case FK_Data_1:
     return 1;
 
   case FK_Data_2:
   case FK_SecRel_2:
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
   case AArch64::fixup_aarch64_pcrel_call26:
     // Signed 28-bit immediate
     if (SignedValue > 134217727 || SignedValue < -134217728)
       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
     // Low two bits are not encoded (4-byte alignment assumed).
     if (Value & 0x3)
       Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
     return (Value >> 2) & 0x3ffffff;
+  case FK_NONE:
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
   case FK_SecRel_2:
   case FK_SecRel_4:
     return Value;
   }
 }
 
+Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
+  if (TheTriple.isOSBinFormatELF() && Name == "R_AARCH64_NONE")
+    return FK_NONE;
+  return MCAsmBackend::getFixupKind(Name);
+}
+
 /// getFixupKindContainereSizeInBytes - The number of bytes of the
 /// container involved in big endian or 0 if the item is little endian
 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
   if (Endian == support::little)
     return 0;
 
   switch (Kind) {
   default:
bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
   for (uint64_t i = 0; i != Count; ++i)
     support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
   return true;
 }
 
 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                               const MCFixup &Fixup,
                                               const MCValue &Target) {
+  unsigned Kind = Fixup.getKind();
+  if (Kind == FK_NONE)
+    return true;
+
   // The ADRP instruction adds some multiple of 0x1000 to the current PC &
   // ~0xfff. This means that the required offset to reach a symbol can vary by
   // up to one step depending on where the ADRP is in memory. For example:
   //
   //     ADRP x0, there
   //  there:
   //
   // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
   // we'll need that as an offset. At any other address "there" will be in the
   // same page as the ADRP and the instruction should encode 0x0. Assuming the
   // section isn't 0x1000-aligned, we therefore need to delegate this decision
   // to the linker -- a relocation!
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
+  if (Kind == AArch64::fixup_aarch64_pcrel_adrp_imm21)
     return true;
 
   AArch64MCExpr::VariantKind RefKind =
       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   // LDR GOT relocations need a relocation
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
+  if (Kind == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
       SymLoc == AArch64MCExpr::VK_GOT)
     return true;
   return false;
 }
 
 namespace {
 
 namespace CU {

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

if (IsPCRel) {
     default:
       Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
       return ELF::R_AARCH64_NONE;
     }
   } else {
     if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
       return ELF::R_AARCH64_NONE;
     switch ((unsigned)Fixup.getKind()) {
+    case FK_NONE:
+      return ELF::R_AARCH64_NONE;
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(ABS16);
     case FK_Data_4:
       return R_CLS(ABS32);
     case FK_Data_8:

llvm/trunk/test/MC/AArch64/reloc-directive.s

+# RUN: llvm-mc -triple=aarch64-linux-musl %s | FileCheck --check-prefix=PRINT %s
+
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-musl %s | llvm-readobj -r | FileCheck %s
+
+# PRINT: .reloc 8, R_AARCH64_NONE, .data
+# PRINT: .reloc 4, R_AARCH64_NONE, foo+4
+# PRINT: .reloc 0, R_AARCH64_NONE, 8
+.text
+  ret
+  nop
+  nop
+  .reloc 8, R_AARCH64_NONE, .data
+  .reloc 4, R_AARCH64_NONE, foo+4
+  .reloc 0, R_AARCH64_NONE, 8
+
+.data
+.globl foo
+foo:
+  .word 0
+  .word 0
+  .word 0
+
+# CHECK:      0x8 R_AARCH64_NONE .data 0x0
+# CHECK-NEXT: 0x4 R_AARCH64_NONE foo 0x4
+# CHECK-NEXT: 0x0 R_AARCH64_NONE - 0x8