[AArch64] Support .reloc *, R_AARCH64_NONE, *

[MaskRay]

Summary

This can be used to create references among sections. When --gc-sections
is used, the referenced section will be retained if the origin section
is retained.

[MaskRay]

Forgot to add test...

[rprichard]

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

[MaskRay]

Discarded unintended lib/Target/ARM changes

[MaskRay]

In D61973#1504185, @rprichard wrote:

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

Sorry, lib/Target/ARM changed were unintended. I am indeed studying how to support R_ARM_NONE :)

[rprichard]

FWIW: I noticed that the binutils assembler's .reloc directive can reference an arbitrary symbol whereas with this patch, a .reloc directive referencing a label turns into a section reference. e.g.:

$ cat test.s
  nop
foo:
  nop
bar:
  .reloc bar, R_AARCH64_NONE, foo
  .reloc bar, R_AARCH64_NONE, .text + 8

$ clang test.s -target aarch64-linux-gnu -c && readelf -r test.o

Relocation section '.rela.text' at offset 0xc0 contains 2 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000008  000400000000 R_AARCH64_NONE    0000000000000000 .text + 4
000000000008  000400000000 R_AARCH64_NONE    0000000000000000 .text + 8

$ clang test.s -target aarch64-linux-gnu -c -fno-integrated-as && readelf -r test.o

Relocation section '.rela.text' at offset 0x100 contains 2 entries:
  Offset          Info           Type           Sym. Value    Sym. Name + Addend
000000000008  000500000000 R_AARCH64_NONE    0000000000000004 foo + 0
000000000008  000100000000 R_AARCH64_NONE    0000000000000000 .text + 8

I see the same difference with the MIPS LLVM backend versus /usr/bin/mipsel-linux-gnu-as, so this is probably fine. I think referencing a section would be sufficient for the crtbegin usage described in D61825.

[MaskRay]

Set shouldForceRelocation to allow 0 symbol index, e.g. .reloc 0, R_AARCH64_NONE, 8

[peter.smith]

I have similar comments to D61992

In D61973#1504196, @MaskRay wrote:

In D61973#1504185, @rprichard wrote:

The commit message only mentions AArch64, but the commit appears to also add support for R_ARM_NONE. I tried using R_ARM_NONE, though, and was unsuccessful:

$ clang -target arm-linux-gnu test.s -c -mfloat-abi=soft
test.s:1:3: error: unsupported relocation on symbol
  .reloc 0, R_ARM_NONE, .text
  ^

I was able to use R_ARM_NONE with -fno-integrated-as, but then lld couldn't link the object file into a relobj with -Wl,-r:

$ clang -target armv7a-linux-gnueabi test.o -mfloat-abi=soft -o foo -Wl,-r -fuse-ld=lld -nostdlib
ld.lld: warning: lld uses blx instruction, no object with architecture supporting feature detected
ld.lld: error: test.o:(.rel.text+0x0): unrecognized reloc 0

Sorry, lib/Target/ARM changed were unintended. I am indeed studying how to support R_ARM_NONE :)

I think Ryan has found a different problem here. My first thought was that R_ARM_NONE and R_AARCH64_NONE are supported in LLD as they map to R_NONE. In general LLD filters these out so they never get to relocateOne. It seems like there is a possibility of this happening with ld -r if the R_ARM_NONE is from a SHF_ALLOC section. In short the unrecognized reloc 0 is coming from relocateOne. The error seems to be specific to ARM, or at least to REL and not RELA as AArch64 and x86_64 -r work.

[peter.smith]

I think the ld -r failure with arm is due to InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) in particular:

if (RelTy::IsRela)
        P->r_addend = Sym.getVA(Addend) - Section->getOutputSection()->Addr;
      else if (Config->Relocatable)
        Sec->Relocations.push_back({R_ABS, Type, Rel.r_offset, Addend, &Sym});

If we add a R_ABS with Type R_ARM_NONE then relocateOne will try to evaluate it and hence we get the unrecognized reloc error. My intuition is to skip adding the R_ABS when the relocation is the None relocation. I'm not going to get a chance to send a patch to fix it today though.

[peter.smith]

To get back to this patch. I think the non-bigendian comments I made on D61992 apply here as well. Generally looks good. Will be worth checking that the format is ELF before accepting R_AARCH64_NONE.

I checked what GNU as does about the ILP32 status as the code R_AARCH64_P32_NONE is also defined to be 0. Having said that it seems like GNU as will only accept R_AARCH64_NONE in both ilp32 and ilp64 modes and won't accept R_AARCH64_P32_NONE so I think what we have here is fine.

[MaskRay]

Improve the tests as peter.smith suggested in the ARM patch.

[peter.smith]

Thanks, looks good to me. Will be worth seeing if there are any further comments from the US Timezone.

[MaskRay]

In D61973#1504710, @peter.smith wrote:

I think the ld -r failure with arm is due to InputSection::copyRelocations(uint8_t *Buf, ArrayRef<RelTy> Rels) in particular:

if (RelTy::IsRela)
        P->r_addend = Sym.getVA(Addend) - Section->getOutputSection()->Addr;
      else if (Config->Relocatable)
        Sec->Relocations.push_back({R_ABS, Type, Rel.r_offset, Addend, &Sym});

If we add a R_ABS with Type R_ARM_NONE then relocateOne will try to evaluate it and hence we get the unrecognized reloc error. My intuition is to skip adding the R_ABS when the relocation is the None relocation. I'm not going to get a chance to send a patch to fix it today though.

Probably just use

-      else if (Config->Relocatable)
+      else if (Config->Relocatable && Type != Target->NoneRel)

After .reloc *, R_386_NONE, * is supported, probably change relocation-none-i686.test (yaml2obj) to an assembly test and check ld.lld -r doesn't crash...

[MaskRay]

Use generic FK_NONE

lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

public:
   AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
       : MCAsmBackend(IsLittleEndian ? support::little : support::big),
         TheTriple(TT) {}
 
   unsigned getNumFixupKinds() const override {
     return AArch64::NumTargetFixupKinds;
   }
 
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
+
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
         // This table *must* be in the order that the fixup_* kinds are defined
         // in AArch64FixupKinds.h.
         //
         // Name                           Offset (bits) Size (bits)     Flags
+        {"fixup_aarch64_NONE", 0, 0, 0},
         {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
         {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
         {"fixup_aarch64_add_imm12", 10, 12, 0},
         {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
         {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
         {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
         {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
         {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},

 } // end anonymous namespace
 
 /// The number of bytes the fixup may change.
 static unsigned getFixupKindNumBytes(unsigned Kind) {
   switch (Kind) {
   default:
     llvm_unreachable("Unknown fixup kind!");
 
+  case AArch64::fixup_aarch64_NONE:
   case AArch64::fixup_aarch64_tlsdesc_call:
     return 0;
 
   case FK_Data_1:
     return 1;
 
   case FK_Data_2:
   case FK_SecRel_2:
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
   case AArch64::fixup_aarch64_pcrel_call26:
     // Signed 28-bit immediate
     if (SignedValue > 134217727 || SignedValue < -134217728)
       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
     // Low two bits are not encoded (4-byte alignment assumed).
     if (Value & 0x3)
       Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
     return (Value >> 2) & 0x3ffffff;
+  case AArch64::fixup_aarch64_NONE:
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
   case FK_SecRel_2:
   case FK_SecRel_4:
     return Value;
   }
 }
 
+Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
+  if (Name == "R_AARCH64_NONE")
+    return (MCFixupKind)AArch64::fixup_aarch64_NONE;
+  return MCAsmBackend::getFixupKind(Name);
+}
+
 /// getFixupKindContainereSizeInBytes - The number of bytes of the
 /// container involved in big endian or 0 if the item is little endian
 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
   if (Endian == support::little)
     return 0;
 
   switch (Kind) {
   default:

lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

if (IsPCRel) {
     case FK_Data_8:
       if (IsILP32) {
         Ctx.reportError(Fixup.getLoc(),
                         "ILP32 8 byte absolute data "
                         "relocation not supported (LP64 eqv: ABS64)");
         return ELF::R_AARCH64_NONE;
       } else
         return ELF::R_AARCH64_ABS64;
+    case AArch64::fixup_aarch64_NONE:
+      return ELF::R_AARCH64_NONE;
     case AArch64::fixup_aarch64_add_imm12:
       if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
         return R_CLS(TLSLD_ADD_DTPREL_HI12);
       if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
         return R_CLS(TLSLE_ADD_TPREL_HI12);
       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
         return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)

lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h

 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64FIXUPKINDS_H
 
 #include "llvm/MC/MCFixup.h"
 
 namespace llvm {
 namespace AArch64 {
 
 enum Fixups {
+  // Fixups resulting in R_AARCH64_NONE.
+  fixup_aarch64_NONE = FirstTargetFixupKind,
+
   // A 21-bit pc-relative immediate inserted into an ADR instruction.
-  fixup_aarch64_pcrel_adr_imm21 = FirstTargetFixupKind,
+  fixup_aarch64_pcrel_adr_imm21,
 
   // A 21-bit pc-relative immediate inserted into an ADRP instruction.
   fixup_aarch64_pcrel_adrp_imm21,
 
   // 12-bit fixup for add/sub instructions. No alignment adjustment. All value
   // bits are encoded.
   fixup_aarch64_add_imm12,
 

test/MC/AArch64/reloc-directive.s

+# RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux-gnu %s | llvm-readobj -r | FileCheck %s
+
+  .reloc 4, R_AARCH64_NONE, .text
+  .reloc 0, R_AARCH64_NONE, .text+4
+  nop
+  nop
+
+# CHECK:      0x4 R_AARCH64_NONE .text 0x0
+# CHECK-NEXT: 0x0 R_AARCH64_NONE .text 0x4