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Differential D61792

[PPC] Fix 32-bit build of libunwind
ClosedPublic

Authored by luporl on May 10 2019, 9:28 AM.

Details

Reviewers
mstorsjo
nemanjai
compnerd
MaskRay
mclow.lists
Commits
rZORG875a7caf045c: [PPC] Fix 32-bit build of libunwind
rG2fb27a25fcb6: Merging r360862:
rL363030: Merging r360862:
rG875a7caf045c: [PPC] Fix 32-bit build of libunwind
rUNW360862: [PPC] Fix 32-bit build of libunwind
rG905af40cc6ce: [PPC] Fix 32-bit build of libunwind
rL360862: [PPC] Fix 32-bit build of libunwind
Summary

Clang integrated assembler was unable to build libunwind PPC32 assembly code,
present in functions used to save/restore register context.

This change consists in replacing the assembly style used in libunwind source,
to one that is compatible with both Clang integrated assembler as well as
GNU assembler.

Diff Detail

Event Timeline

luporl created this revision.May 10 2019, 9:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 10 2019, 9:28 AM
Herald added subscribers: libcxx-commits, jsji, christof. · View Herald Transcript
Harbormaster completed remote builds in B31746: Diff 199029.May 10 2019, 9:29 AM
luporl added reviewers: mstorsjo, nemanjai, compnerd.May 10 2019, 9:33 AM
luporl added subscribers: adalava, sfertile, emaste.
luporl added a subscriber: MaskRay.May 10 2019, 9:41 AM
MaskRay added inline comments.May 10 2019, 7:20 PM
libunwind/src/UnwindRegistersSave.S
559

Changing the comment marker seems fine from the perspective of consistency.

566

Nice, if stw r0, 8(r3) is accepted by neither GNU as nor llvm-mc, why was it added in the first place...

Have you considered stw 0, 8(3)? In powerpc assembly, 0 is much more common than %r0.

luporl marked 3 inline comments as done.May 13 2019, 6:57 AM
luporl added inline comments.
libunwind/src/UnwindRegistersSave.S
566

Yes, I also don't know how the older powerpc assembly in this file was supposed to work...

Personally, I find stw %r0, 8(%r3) easier to read and understand than stw 0, 8(3), because it makes the distinction between registers and immediates clear.
This change is also consistent with powerpc64 code, that uses "%r" for registers.

MaskRay accepted this revision.May 13 2019, 7:18 AM
This revision is now accepted and ready to land.May 13 2019, 7:18 AM
compnerd added inline comments.May 13 2019, 11:10 AM
libunwind/src/UnwindRegistersSave.S
566

I believe that these were written against the cctools's assembler, not GNU.

mclow.lists accepted this revision.May 13 2019, 11:11 AM
mclow.lists added a subscriber: mclow.lists.

As far as I can tell, this should have no effects - is that correct?
If so, this looks fine to me.

compnerd added inline comments.May 13 2019, 11:20 AM
libunwind/src/assembly.h
32

Why the removal of this? This is the correct separator IIRC.

luporl marked an inline comment as done.May 13 2019, 11:31 AM
In D61792#1500285, @mclow.lists wrote:

As far as I can tell, this should have no effects - is that correct?
If so, this looks fine to me.

Correct.

luporl marked an inline comment as done.May 13 2019, 11:37 AM
luporl added inline comments.
libunwind/src/assembly.h
32

Because clang's integrated assembler does not recognize '@' as a separator, but both clang and GNU as recognize ';' as a separator.
Maybe this part was also added when cctools were being used?

Bdragon28 marked an inline comment as done.May 14 2019, 2:50 PM
Bdragon28 added a subscriber: Bdragon28.
Bdragon28 added inline comments.
libunwind/src/assembly.h
32

Additionally, @ actually means something in PPC64 asm. It's used for indirect references.

Closed by commit rL360862: [PPC] Fix 32-bit build of libunwind (authored by mstorsjo). · Explain WhyMay 15 2019, 11:48 PM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2019, 11:48 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
libunwind/
src/
238 lines
270 lines
2 lines

Diff 199029

libunwind/src/UnwindRegistersRestore.S

Show First 20 Lines • Show All 389 Lines • ▼ Show 20 LinesLnovec:
PPC64_LR(4) PPC64_LR(4)
PPC64_LR(1) PPC64_LR(1)
PPC64_LR(3) PPC64_LR(3)
bctr bctr
#elif defined(__ppc__) #elif defined(__ppc__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
; //
; void libunwind::Registers_ppc::jumpto() // void libunwind::Registers_ppc::jumpto()
; //
; On entry: // On entry:
; thread_state pointer is in r3 // thread_state pointer is in r3
; //
; restore integral registerrs // restore integral registerrs
; skip r0 for now // skip r0 for now
; skip r1 for now // skip r1 for now
lwz r2, 16(r3) lwz %r2, 16(%r3)
; skip r3 for now // skip r3 for now
; skip r4 for now // skip r4 for now
; skip r5 for now // skip r5 for now
lwz r6, 32(r3) lwz %r6, 32(%r3)
lwz r7, 36(r3) lwz %r7, 36(%r3)
lwz r8, 40(r3) lwz %r8, 40(%r3)
lwz r9, 44(r3) lwz %r9, 44(%r3)
lwz r10, 48(r3) lwz %r10, 48(%r3)
lwz r11, 52(r3) lwz %r11, 52(%r3)
lwz r12, 56(r3) lwz %r12, 56(%r3)
lwz r13, 60(r3) lwz %r13, 60(%r3)
lwz r14, 64(r3) lwz %r14, 64(%r3)
lwz r15, 68(r3) lwz %r15, 68(%r3)
lwz r16, 72(r3) lwz %r16, 72(%r3)
lwz r17, 76(r3) lwz %r17, 76(%r3)
lwz r18, 80(r3) lwz %r18, 80(%r3)
lwz r19, 84(r3) lwz %r19, 84(%r3)
lwz r20, 88(r3) lwz %r20, 88(%r3)
lwz r21, 92(r3) lwz %r21, 92(%r3)
lwz r22, 96(r3) lwz %r22, 96(%r3)
lwz r23,100(r3) lwz %r23,100(%r3)
lwz r24,104(r3) lwz %r24,104(%r3)
lwz r25,108(r3) lwz %r25,108(%r3)
lwz r26,112(r3) lwz %r26,112(%r3)
lwz r27,116(r3) lwz %r27,116(%r3)
lwz r28,120(r3) lwz %r28,120(%r3)
lwz r29,124(r3) lwz %r29,124(%r3)
lwz r30,128(r3) lwz %r30,128(%r3)
lwz r31,132(r3) lwz %r31,132(%r3)
; restore float registers // restore float registers
lfd f0, 160(r3) lfd %f0, 160(%r3)
lfd f1, 168(r3) lfd %f1, 168(%r3)
lfd f2, 176(r3) lfd %f2, 176(%r3)
lfd f3, 184(r3) lfd %f3, 184(%r3)
lfd f4, 192(r3) lfd %f4, 192(%r3)
lfd f5, 200(r3) lfd %f5, 200(%r3)
lfd f6, 208(r3) lfd %f6, 208(%r3)
lfd f7, 216(r3) lfd %f7, 216(%r3)
lfd f8, 224(r3) lfd %f8, 224(%r3)
lfd f9, 232(r3) lfd %f9, 232(%r3)
lfd f10,240(r3) lfd %f10,240(%r3)
lfd f11,248(r3) lfd %f11,248(%r3)
lfd f12,256(r3) lfd %f12,256(%r3)
lfd f13,264(r3) lfd %f13,264(%r3)
lfd f14,272(r3) lfd %f14,272(%r3)
lfd f15,280(r3) lfd %f15,280(%r3)
lfd f16,288(r3) lfd %f16,288(%r3)
lfd f17,296(r3) lfd %f17,296(%r3)
lfd f18,304(r3) lfd %f18,304(%r3)
lfd f19,312(r3) lfd %f19,312(%r3)
lfd f20,320(r3) lfd %f20,320(%r3)
lfd f21,328(r3) lfd %f21,328(%r3)
lfd f22,336(r3) lfd %f22,336(%r3)
lfd f23,344(r3) lfd %f23,344(%r3)
lfd f24,352(r3) lfd %f24,352(%r3)
lfd f25,360(r3) lfd %f25,360(%r3)
lfd f26,368(r3) lfd %f26,368(%r3)
lfd f27,376(r3) lfd %f27,376(%r3)
lfd f28,384(r3) lfd %f28,384(%r3)
lfd f29,392(r3) lfd %f29,392(%r3)
lfd f30,400(r3) lfd %f30,400(%r3)
lfd f31,408(r3) lfd %f31,408(%r3)
; restore vector registers if any are in use // restore vector registers if any are in use
lwz r5,156(r3) ; test VRsave lwz %r5, 156(%r3) // test VRsave
cmpwi r5,0 cmpwi %r5, 0
beq Lnovec beq Lnovec
subi r4,r1,16 subi %r4, %r1, 16
rlwinm r4,r4,0,0,27 ; mask low 4-bits rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
; r4 is now a 16-byte aligned pointer into the red zone // r4 is now a 16-byte aligned pointer into the red zone
; the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer // the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
#define LOAD_VECTOR_UNALIGNEDl(_index) \ #define LOAD_VECTOR_UNALIGNEDl(_index) \
andis. r0,r5,(1<<(15-_index)) @\ andis. %r0, %r5, (1<<(15-_index)) SEPARATOR \
beq Ldone ## _index @\ beq Ldone ## _index SEPARATOR \
lwz r0, 424+_index*16(r3) @\ lwz %r0, 424+_index*16(%r3) SEPARATOR \
stw r0, 0(r4) @\ stw %r0, 0(%r4) SEPARATOR \
lwz r0, 424+_index*16+4(r3) @\ lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
stw r0, 4(r4) @\ stw %r0, 4(%r4) SEPARATOR \
lwz r0, 424+_index*16+8(r3) @\ lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
stw r0, 8(r4) @\ stw %r0, 8(%r4) SEPARATOR \
lwz r0, 424+_index*16+12(r3)@\ lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
stw r0, 12(r4) @\ stw %r0, 12(%r4) SEPARATOR \
lvx v ## _index,0,r4 @\ lvx %v ## _index, 0, %r4 SEPARATOR \
Ldone ## _index: Ldone ## _index:
#define LOAD_VECTOR_UNALIGNEDh(_index) \ #define LOAD_VECTOR_UNALIGNEDh(_index) \
andi. r0,r5,(1<<(31-_index)) @\ andi. %r0, %r5, (1<<(31-_index)) SEPARATOR \
beq Ldone ## _index @\ beq Ldone ## _index SEPARATOR \
lwz r0, 424+_index*16(r3) @\ lwz %r0, 424+_index*16(%r3) SEPARATOR \
stw r0, 0(r4) @\ stw %r0, 0(%r4) SEPARATOR \
lwz r0, 424+_index*16+4(r3) @\ lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
stw r0, 4(r4) @\ stw %r0, 4(%r4) SEPARATOR \
lwz r0, 424+_index*16+8(r3) @\ lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
stw r0, 8(r4) @\ stw %r0, 8(%r4) SEPARATOR \
lwz r0, 424+_index*16+12(r3)@\ lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
stw r0, 12(r4) @\ stw %r0, 12(%r4) SEPARATOR \
lvx v ## _index,0,r4 @\ lvx %v ## _index, 0, %r4 SEPARATOR \
Ldone ## _index: Ldone ## _index:
LOAD_VECTOR_UNALIGNEDl(0) LOAD_VECTOR_UNALIGNEDl(0)
LOAD_VECTOR_UNALIGNEDl(1) LOAD_VECTOR_UNALIGNEDl(1)
LOAD_VECTOR_UNALIGNEDl(2) LOAD_VECTOR_UNALIGNEDl(2)
LOAD_VECTOR_UNALIGNEDl(3) LOAD_VECTOR_UNALIGNEDl(3)
LOAD_VECTOR_UNALIGNEDl(4) LOAD_VECTOR_UNALIGNEDl(4)
LOAD_VECTOR_UNALIGNEDl(5) LOAD_VECTOR_UNALIGNEDl(5)
Show All 20 Lines#define LOAD_VECTOR_UNALIGNEDh(_index) \
LOAD_VECTOR_UNALIGNEDh(26) LOAD_VECTOR_UNALIGNEDh(26)
LOAD_VECTOR_UNALIGNEDh(27) LOAD_VECTOR_UNALIGNEDh(27)
LOAD_VECTOR_UNALIGNEDh(28) LOAD_VECTOR_UNALIGNEDh(28)
LOAD_VECTOR_UNALIGNEDh(29) LOAD_VECTOR_UNALIGNEDh(29)
LOAD_VECTOR_UNALIGNEDh(30) LOAD_VECTOR_UNALIGNEDh(30)
LOAD_VECTOR_UNALIGNEDh(31) LOAD_VECTOR_UNALIGNEDh(31)
Lnovec: Lnovec:
lwz r0, 136(r3) ; __cr lwz %r0, 136(%r3) // __cr
mtocrf 255,r0 mtcr %r0
lwz r0, 148(r3) ; __ctr lwz %r0, 148(%r3) // __ctr
mtctr r0 mtctr %r0
lwz r0, 0(r3) ; __ssr0 lwz %r0, 0(%r3) // __ssr0
mtctr r0 mtctr %r0
lwz r0, 8(r3) ; do r0 now lwz %r0, 8(%r3) // do r0 now
lwz r5,28(r3) ; do r5 now lwz %r5, 28(%r3) // do r5 now
lwz r4,24(r3) ; do r4 now lwz %r4, 24(%r3) // do r4 now
lwz r1,12(r3) ; do sp now lwz %r1, 12(%r3) // do sp now
lwz r3,20(r3) ; do r3 last lwz %r3, 20(%r3) // do r3 last
bctr bctr
#elif defined(__arm64__) || defined(__aarch64__) #elif defined(__arm64__) || defined(__aarch64__)
// //
// void libunwind::Registers_arm64::jumpto() // void libunwind::Registers_arm64::jumpto()
// //
// On entry: // On entry:
▲ Show 20 Lines • Show All 467 Lines • Show Last 20 Lines

libunwind/src/UnwindRegistersSave.S

Show First 20 Lines • Show All 550 Lines • ▼ Show 20 Lines
#endif #endif
li %r3, 0 // return UNW_ESUCCESS li %r3, 0 // return UNW_ESUCCESS
blr blr
#elif defined(__ppc__) #elif defined(__ppc__)
; //
MaskRayUnsubmitted
Done
ReplyInline Actions

Changing the comment marker seems fine from the perspective of consistency.

MaskRay: Changing the comment marker seems fine from the perspective of consistency.
; extern int __unw_getcontext(unw_context_t* thread_state) // extern int unw_getcontext(unw_context_t* thread_state)
; //
; On entry: // On entry:
; thread_state pointer is in r3 // thread_state pointer is in r3
; //
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
stw r0, 8(r3) stw %r0, 8(%r3)
MaskRayUnsubmitted
Done
ReplyInline Actions

Nice, if stw r0, 8(r3) is accepted by neither GNU as nor llvm-mc, why was it added in the first place...

Have you considered stw 0, 8(3)? In powerpc assembly, 0 is much more common than %r0.

MaskRay: Nice, if `stw r0, 8(r3)` is accepted by neither GNU as nor llvm-mc, why was it added in the…
luporlAuthorUnsubmitted
Done
ReplyInline Actions

Yes, I also don't know how the older powerpc assembly in this file was supposed to work...

Personally, I find stw %r0, 8(%r3) easier to read and understand than stw 0, 8(3), because it makes the distinction between registers and immediates clear.
This change is also consistent with powerpc64 code, that uses "%r" for registers.

luporl: Yes, I also don't know how the older powerpc assembly in this file was supposed to work...
compnerdUnsubmitted
Not Done
ReplyInline Actions

I believe that these were written against the cctools's assembler, not GNU.

compnerd: I believe that these were written against the cctools's assembler, not GNU.
mflr r0 mflr %r0
stw r0, 0(r3) ; store lr as ssr0 stw %r0, 0(%r3) // store lr as ssr0
stw r1, 12(r3) stw %r1, 12(%r3)
stw r2, 16(r3) stw %r2, 16(%r3)
stw r3, 20(r3) stw %r3, 20(%r3)
stw r4, 24(r3) stw %r4, 24(%r3)
stw r5, 28(r3) stw %r5, 28(%r3)
stw r6, 32(r3) stw %r6, 32(%r3)
stw r7, 36(r3) stw %r7, 36(%r3)
stw r8, 40(r3) stw %r8, 40(%r3)
stw r9, 44(r3) stw %r9, 44(%r3)
stw r10, 48(r3) stw %r10, 48(%r3)
stw r11, 52(r3) stw %r11, 52(%r3)
stw r12, 56(r3) stw %r12, 56(%r3)
stw r13, 60(r3) stw %r13, 60(%r3)
stw r14, 64(r3) stw %r14, 64(%r3)
stw r15, 68(r3) stw %r15, 68(%r3)
stw r16, 72(r3) stw %r16, 72(%r3)
stw r17, 76(r3) stw %r17, 76(%r3)
stw r18, 80(r3) stw %r18, 80(%r3)
stw r19, 84(r3) stw %r19, 84(%r3)
stw r20, 88(r3) stw %r20, 88(%r3)
stw r21, 92(r3) stw %r21, 92(%r3)
stw r22, 96(r3) stw %r22, 96(%r3)
stw r23,100(r3) stw %r23,100(%r3)
stw r24,104(r3) stw %r24,104(%r3)
stw r25,108(r3) stw %r25,108(%r3)
stw r26,112(r3) stw %r26,112(%r3)
stw r27,116(r3) stw %r27,116(%r3)
stw r28,120(r3) stw %r28,120(%r3)
stw r29,124(r3) stw %r29,124(%r3)
stw r30,128(r3) stw %r30,128(%r3)
stw r31,132(r3) stw %r31,132(%r3)
; save VRSave register // save VRSave register
mfspr r0,256 mfspr %r0, 256
stw r0,156(r3) stw %r0, 156(%r3)
; save CR registers // save CR registers
mfcr r0 mfcr %r0
stw r0,136(r3) stw %r0, 136(%r3)
; save CTR register // save CTR register
mfctr r0 mfctr %r0
stw r0,148(r3) stw %r0, 148(%r3)
; save float registers // save float registers
stfd f0, 160(r3) stfd %f0, 160(%r3)
stfd f1, 168(r3) stfd %f1, 168(%r3)
stfd f2, 176(r3) stfd %f2, 176(%r3)
stfd f3, 184(r3) stfd %f3, 184(%r3)
stfd f4, 192(r3) stfd %f4, 192(%r3)
stfd f5, 200(r3) stfd %f5, 200(%r3)
stfd f6, 208(r3) stfd %f6, 208(%r3)
stfd f7, 216(r3) stfd %f7, 216(%r3)
stfd f8, 224(r3) stfd %f8, 224(%r3)
stfd f9, 232(r3) stfd %f9, 232(%r3)
stfd f10,240(r3) stfd %f10,240(%r3)
stfd f11,248(r3) stfd %f11,248(%r3)
stfd f12,256(r3) stfd %f12,256(%r3)
stfd f13,264(r3) stfd %f13,264(%r3)
stfd f14,272(r3) stfd %f14,272(%r3)
stfd f15,280(r3) stfd %f15,280(%r3)
stfd f16,288(r3) stfd %f16,288(%r3)
stfd f17,296(r3) stfd %f17,296(%r3)
stfd f18,304(r3) stfd %f18,304(%r3)
stfd f19,312(r3) stfd %f19,312(%r3)
stfd f20,320(r3) stfd %f20,320(%r3)
stfd f21,328(r3) stfd %f21,328(%r3)
stfd f22,336(r3) stfd %f22,336(%r3)
stfd f23,344(r3) stfd %f23,344(%r3)
stfd f24,352(r3) stfd %f24,352(%r3)
stfd f25,360(r3) stfd %f25,360(%r3)
stfd f26,368(r3) stfd %f26,368(%r3)
stfd f27,376(r3) stfd %f27,376(%r3)
stfd f28,384(r3) stfd %f28,384(%r3)
stfd f29,392(r3) stfd %f29,392(%r3)
stfd f30,400(r3) stfd %f30,400(%r3)
stfd f31,408(r3) stfd %f31,408(%r3)
; save vector registers // save vector registers
subi r4,r1,16 subi %r4, %r1, 16
rlwinm r4,r4,0,0,27 ; mask low 4-bits rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
; r4 is now a 16-byte aligned pointer into the red zone // r4 is now a 16-byte aligned pointer into the red zone
#define SAVE_VECTOR_UNALIGNED(_vec, _offset) \ #define SAVE_VECTOR_UNALIGNED(_vec, _offset) \
stvx _vec,0,r4 @\ stvx _vec, 0, %r4 SEPARATOR \
lwz r5, 0(r4) @\ lwz %r5, 0(%r4) SEPARATOR \
stw r5, _offset(r3) @\ stw %r5, _offset(%r3) SEPARATOR \
lwz r5, 4(r4) @\ lwz %r5, 4(%r4) SEPARATOR \
stw r5, _offset+4(r3) @\ stw %r5, _offset+4(%r3) SEPARATOR \
lwz r5, 8(r4) @\ lwz %r5, 8(%r4) SEPARATOR \
stw r5, _offset+8(r3) @\ stw %r5, _offset+8(%r3) SEPARATOR \
lwz r5, 12(r4) @\ lwz %r5, 12(%r4) SEPARATOR \
stw r5, _offset+12(r3) stw %r5, _offset+12(%r3)
SAVE_VECTOR_UNALIGNED( v0, 424+0x000) SAVE_VECTOR_UNALIGNED( %v0, 424+0x000)
SAVE_VECTOR_UNALIGNED( v1, 424+0x010) SAVE_VECTOR_UNALIGNED( %v1, 424+0x010)
SAVE_VECTOR_UNALIGNED( v2, 424+0x020) SAVE_VECTOR_UNALIGNED( %v2, 424+0x020)
SAVE_VECTOR_UNALIGNED( v3, 424+0x030) SAVE_VECTOR_UNALIGNED( %v3, 424+0x030)
SAVE_VECTOR_UNALIGNED( v4, 424+0x040) SAVE_VECTOR_UNALIGNED( %v4, 424+0x040)
SAVE_VECTOR_UNALIGNED( v5, 424+0x050) SAVE_VECTOR_UNALIGNED( %v5, 424+0x050)
SAVE_VECTOR_UNALIGNED( v6, 424+0x060) SAVE_VECTOR_UNALIGNED( %v6, 424+0x060)
SAVE_VECTOR_UNALIGNED( v7, 424+0x070) SAVE_VECTOR_UNALIGNED( %v7, 424+0x070)
SAVE_VECTOR_UNALIGNED( v8, 424+0x080) SAVE_VECTOR_UNALIGNED( %v8, 424+0x080)
SAVE_VECTOR_UNALIGNED( v9, 424+0x090) SAVE_VECTOR_UNALIGNED( %v9, 424+0x090)
SAVE_VECTOR_UNALIGNED(v10, 424+0x0A0) SAVE_VECTOR_UNALIGNED(%v10, 424+0x0A0)
SAVE_VECTOR_UNALIGNED(v11, 424+0x0B0) SAVE_VECTOR_UNALIGNED(%v11, 424+0x0B0)
SAVE_VECTOR_UNALIGNED(v12, 424+0x0C0) SAVE_VECTOR_UNALIGNED(%v12, 424+0x0C0)
SAVE_VECTOR_UNALIGNED(v13, 424+0x0D0) SAVE_VECTOR_UNALIGNED(%v13, 424+0x0D0)
SAVE_VECTOR_UNALIGNED(v14, 424+0x0E0) SAVE_VECTOR_UNALIGNED(%v14, 424+0x0E0)
SAVE_VECTOR_UNALIGNED(v15, 424+0x0F0) SAVE_VECTOR_UNALIGNED(%v15, 424+0x0F0)
SAVE_VECTOR_UNALIGNED(v16, 424+0x100) SAVE_VECTOR_UNALIGNED(%v16, 424+0x100)
SAVE_VECTOR_UNALIGNED(v17, 424+0x110) SAVE_VECTOR_UNALIGNED(%v17, 424+0x110)
SAVE_VECTOR_UNALIGNED(v18, 424+0x120) SAVE_VECTOR_UNALIGNED(%v18, 424+0x120)
SAVE_VECTOR_UNALIGNED(v19, 424+0x130) SAVE_VECTOR_UNALIGNED(%v19, 424+0x130)
SAVE_VECTOR_UNALIGNED(v20, 424+0x140) SAVE_VECTOR_UNALIGNED(%v20, 424+0x140)
SAVE_VECTOR_UNALIGNED(v21, 424+0x150) SAVE_VECTOR_UNALIGNED(%v21, 424+0x150)
SAVE_VECTOR_UNALIGNED(v22, 424+0x160) SAVE_VECTOR_UNALIGNED(%v22, 424+0x160)
SAVE_VECTOR_UNALIGNED(v23, 424+0x170) SAVE_VECTOR_UNALIGNED(%v23, 424+0x170)
SAVE_VECTOR_UNALIGNED(v24, 424+0x180) SAVE_VECTOR_UNALIGNED(%v24, 424+0x180)
SAVE_VECTOR_UNALIGNED(v25, 424+0x190) SAVE_VECTOR_UNALIGNED(%v25, 424+0x190)
SAVE_VECTOR_UNALIGNED(v26, 424+0x1A0) SAVE_VECTOR_UNALIGNED(%v26, 424+0x1A0)
SAVE_VECTOR_UNALIGNED(v27, 424+0x1B0) SAVE_VECTOR_UNALIGNED(%v27, 424+0x1B0)
SAVE_VECTOR_UNALIGNED(v28, 424+0x1C0) SAVE_VECTOR_UNALIGNED(%v28, 424+0x1C0)
SAVE_VECTOR_UNALIGNED(v29, 424+0x1D0) SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
SAVE_VECTOR_UNALIGNED(v30, 424+0x1E0) SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
SAVE_VECTOR_UNALIGNED(v31, 424+0x1F0) SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
li r3, 0 ; return UNW_ESUCCESS li %r3, 0 // return UNW_ESUCCESS
blr blr
#elif defined(__arm64__) || defined(__aarch64__) #elif defined(__arm64__) || defined(__aarch64__)
// //
// extern int __unw_getcontext(unw_context_t* thread_state) // extern int __unw_getcontext(unw_context_t* thread_state)
// //
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libunwind/src/assembly.h

Show All 22 Lines
#define PPC64_OFFS_LR 288 #define PPC64_OFFS_LR 288
#define PPC64_OFFS_CTR 296 #define PPC64_OFFS_CTR 296
#define PPC64_OFFS_VRSAVE 304 #define PPC64_OFFS_VRSAVE 304
#define PPC64_OFFS_FP 312 #define PPC64_OFFS_FP 312
#define PPC64_OFFS_V 824 #define PPC64_OFFS_V 824
#ifdef _ARCH_PWR8 #ifdef _ARCH_PWR8
#define PPC64_HAS_VMX #define PPC64_HAS_VMX
#endif #endif
#elif defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__)
#define SEPARATOR @
compnerdUnsubmitted
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Why the removal of this? This is the correct separator IIRC.

compnerd: Why the removal of this? This is the correct separator IIRC.
luporlAuthorUnsubmitted
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Because clang's integrated assembler does not recognize '@' as a separator, but both clang and GNU as recognize ';' as a separator.
Maybe this part was also added when cctools were being used?

luporl: Because clang's integrated assembler does not recognize '@' as a separator, but both clang and…
Bdragon28Unsubmitted
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Additionally, @ actually means something in PPC64 asm. It's used for indirect references.

Bdragon28: Additionally, @ actually means something in PPC64 asm. It's used for indirect references.
#elif defined(__arm64__) #elif defined(__arm64__)
#define SEPARATOR %% #define SEPARATOR %%
#else #else
#define SEPARATOR ; #define SEPARATOR ;
#endif #endif
#define GLUE2(a, b) a ## b #define GLUE2(a, b) a ## b
#define GLUE(a, b) GLUE2(a, b) #define GLUE(a, b) GLUE2(a, b)
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