[ARM] Support inline assembler constraints for MVE.

[simon_tatham]

Summary

"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.

Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.

[t.p.northover]

Is this coordinated with GCC?

[simon_tatham]

Yes, it is.

[t.p.northover]

Excellent, looks good to me then.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[simon_tatham]

Rebased this patch to current trunk, and also fixed a test failure by adding arm_aapcs_vfpcc to the test functions that use MVE vector types (since we can't support passing vector types in GPRs until we get all the operations like build_vector and insert_element fully supported).

[craig.topper]

cfe/trunk/lib/Basic/Targets/ARM.cpp

912 ↗

(On Diff #206472)

Is this supposed to fallthrough from 'T' to 'U'? If so can you add an LLVM_FALLTHROUGH

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

14098 ↗

(On Diff #206472)

Is this supposed to fallthrough from case 1 to case 2?

14113 ↗

(On Diff #206472)

Is this supposed to fallthrough?

[simon_tatham]

cfe/trunk/lib/Basic/Targets/ARM.cpp

912 ↗

(On Diff #206472)

No, it wasn't supposed to; sorry about that. rL364380 has fixed it in a way that looks right to me.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

14098 ↗

(On Diff #206472)

No, and rL364376 looks like the right fix to me.

14113 ↗

(On Diff #206472)

No, and rL364376 looks like the right fix to me.

clang/lib/Basic/Targets/ARM.cpp

bool ARMTargetInfo::validateAsmConstraint(
   case 'K':
   case 'L':
   case 'M':
     // FIXME
     return true;
   case 'Q': // A memory address that is a single base register.
     Info.setAllowsMemory();
     return true;
+  case 'T':
+    switch (Name[1]) {
+    default:
+      break;
+    case 'e': // Even general-purpose register
+    case 'o': // Odd general-purpose register
+      Info.setAllowsRegister();
+      Name++;
+      return true;
+    }
   case 'U': // a memory reference...
     switch (Name[1]) {
     case 'q': // ...ARMV4 ldrsb
     case 'v': // ...VFP load/store (reg+constant offset)
     case 'y': // ...iWMMXt load/store
     case 't': // address valid for load/store opaque types wider
               // than 128-bits
     case 'n': // valid address for Neon doubleword vector load/store
     case 'm': // valid address for Neon element and structure load/store
     case 's': // valid address for non-offset loads/stores of quad-word
               // values in four ARM registers
       Info.setAllowsMemory();
       Name++;
       return true;
     }
   }
   return false;
 }
 
 std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
   std::string R;
   switch (*Constraint) {
   case 'U': // Two-character constraint; add "^" hint for later parsing.
+  case 'T':
     R = std::string("^") + std::string(Constraint, 2);
     Constraint++;
     break;
   case 'p': // 'p' should be translated to 'r' by default.
     R = std::string("r");
     break;
   default:
     return std::string(1, *Constraint);

clang/test/CodeGen/arm-asm.c

 // REQUIRES: arm-registered-target
 // RUN: %clang_cc1 -triple thumb %s -emit-llvm -o - | FileCheck %s
 int t1() {
     static float k = 1.0f;
     // CHECK: flds s15
     __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv" (k) : "s15");
     return 0;
 }
+
+// CHECK-LABEL: @even_reg_constraint_Te
+int even_reg_constraint_Te(void) {
+  int acc = 0;
+  // CHECK: vaddv{{.*\^Te}}
+  asm("vaddv.s8 %0, Q0"
+      : "+Te" (acc));
+  return acc;
+}
+
+// CHECK-LABEL: @odd_reg_constraint_To
+int odd_reg_constraint_To(void) {
+  int eacc = 0, oacc = 0;
+  // CHECK: vaddlv{{.*\^To}}
+  asm("vaddlv.s8 %0, %1, Q0"
+      : "+Te" (eacc), "+To" (oacc));
+  return oacc;
+}

llvm/docs/LangRef.rst

 - ``[0-9]v``: The 32-bit VGPR register, number 0-9.
 - ``[0-9]s``: The 32-bit SGPR register, number 0-9.
 
 
 All ARM modes:
 
 - ``Q``, ``Um``, ``Un``, ``Uq``, ``Us``, ``Ut``, ``Uv``, ``Uy``: Memory address
   operand. Treated the same as operand ``m``, at the moment.
+- ``Te``: An even general-purpose 32-bit integer register: ``r0,r2,...,r12,r14``
+- ``To``: An odd general-purpose 32-bit integer register: ``r1,r3,...,r11``
 
 ARM and ARM's Thumb2 mode:
 
 - ``j``: An immediate integer between 0 and 65535 (valid for ``MOVW``)
 - ``I``: An immediate integer valid for a data-processing instruction.
 - ``J``: An immediate integer between -4095 and 4095.
 - ``K``: An immediate integer whose bitwise inverse is valid for a
   data-processing instruction. (Can be used with template modifier "``B``" to

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (Constraint.size() == 1) {
     case 'j': return C_Other; // Constant for movw.
       // An address with a single base register. Due to the way we
       // currently handle addresses it is the same as an 'r' memory constraint.
     case 'Q': return C_Memory;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
     default: break;
+    case 'T': return C_RegisterClass;
     // All 'U+' constraints are addresses.
     case 'U': return C_Memory;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 /// Examine constraint type and operand type and determine a weight value.
ARMTargetLowering::getSingleConstraintMatchWeight(
   }
   return weight;
 }
 
 using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
 
 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
-  if (Constraint.size() == 1) {
+  switch (Constraint.size()) {
+  case 1:
     // GCC ARM Constraint Letters
     switch (Constraint[0]) {
     case 'l': // Low regs or general regs.
       if (Subtarget->isThumb())
         return RCPair(0U, &ARM::tGPRRegClass);
       return RCPair(0U, &ARM::GPRRegClass);
     case 'h': // High regs or no regs.
       if (Subtarget->isThumb())
case 't':
       if (VT == MVT::f32 || VT == MVT::i32)
         return RCPair(0U, &ARM::SPRRegClass);
       if (VT.getSizeInBits() == 64)
         return RCPair(0U, &ARM::DPR_VFP2RegClass);
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, &ARM::QPR_VFP2RegClass);
       break;
     }
+
+  case 2:
+    switch (Constraint[0]) {
+    case 'T':
+      switch (Constraint[1]) {
+      default:
+        break;
+      case 'e':
+        return RCPair(0U, &ARM::tGPREvenRegClass);
+      case 'o':
+        return RCPair(0U, &ARM::tGPROddRegClass);
+      }
+    default:
+      break;
     }
+
+  default:
+    break;
+  }
+
   if (StringRef("{cc}").equals_lower(Constraint))
     return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 /// vector.  If it is invalid, don't add anything to Ops.

llvm/test/CodeGen/ARM/inlineasm-error-t-toofewregs-mve.ll

+; RUN: not llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s
+
+; CHECK: inline assembly requires more registers than available
+define <4 x i32> @t-constraint-i32-vectors-too-few-regs(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %0 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
+                         <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
+                       asm "",
+             "=t,=t,=t,=t,=t,=t,=t,=t,=t,=t,t,t"(<4 x i32> %a, <4 x i32> %b)
+  %asmresult = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
+                                    <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>,
+                                    <4 x i32>, <4 x i32> } %0, 0
+  ret <4 x i32> %asmresult
+}

llvm/test/CodeGen/ARM/inlineasm-mve.ll

+; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s
+
+define i32 @test1(i32 %tmp54) {
+  %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )
+  ret i32 %tmp56
+}
+
+define void @test2() {
+  tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
+  ret void
+}
+
+define <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>) {
+; CHECK-LABEL: mve-t-constraint-128bit
+; CHECK: vadd.i32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}
+  %ret = tail call <4 x i32>
+         asm "vadd.i32 $0, $1, $2", "=t,t,t"
+         (<4 x i32> %0, <4 x i32> %1)
+  ret <4 x i32> %ret
+}
+
+define i32 @even-GPR-constraint() {
+entry:
+  ; CHECK-LABEL: even-GPR-constraint
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
+  %0 = tail call { i32, i32, i32, i32 }
+             asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"
+             (i32 0, i32 0, i32 0, i32 0)
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  ret i32 %asmresult
+}
+
+define i32 @odd-GPR-constraint() {
+entry:
+  ; CHECK-LABEL: odd-GPR-constraint
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
+  %0 = tail call { i32, i32, i32, i32 }
+             asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"
+             (i32 0, i32 0, i32 0, i32 0)
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  ret i32 %asmresult
+}

llvm/test/CodeGen/ARM/inlineasm.ll

 
 define <4 x float> @t-constraint-float-vector-128bit(<4 x float> %a, <4 x float> %b) {
 entry:
   ; CHECK-LABEL: t-constraint-float-vector-128bit
   ; CHECK: vadd.f32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}
   %0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b)
   ret <4 x float> %0
 }
+
+define i32 @even-GPR-constraint() {
+entry:
+  ; CHECK-LABEL: even-GPR-constraint
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
+  ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
+  %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  ret i32 %asmresult
+}
+
+define i32 @odd-GPR-constraint() {
+entry:
+  ; CHECK-LABEL: odd-GPR-constraint
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
+  ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
+  %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)
+  %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
+  ret i32 %asmresult
+}