[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC

[RKSimon]

Summary

Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behaviour in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.).

This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........

I've gone through these tests best I can, and AFAICT I haven't changed their purposes in any critical way - many are fragile and difficult to reduce from scratch as they are often 5+ years old.... I'd appreciate it if the respective target specialists could check my changes.

While these pre-commit changes are getting approved, I'll start adding constant folding tests so we have proper coverage.

[RKSimon]

I'm seeing issues with arm/fp16-instructions.ll against trunk - I'll update once I've got that fixed.

[kparzysz]

The Hexagon part is ok.

[RKSimon]

rebased - includes arm\fp16-instructions.ll fixes as well.

[uweigand]

The SystemZ test case change is fine with me, thanks!

[atanasyan]

The MIPS test change looks good.

[RKSimon]

rebase

[RKSimon]

rebase with some additional constant folding tests

[RKSimon]

Updated patch to prefer const+undef folding to fcmp setcc commutation

[RKSimon]

ping?

[bogner]

lgtm

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::SETUGE: return getBoolConstant(R!=APFloat::cmpLessThan, dl, VT,
                                              OpVT);
     }
   } else if (N1CFP && OpVT.isSimple()) {
     // Ensure that the constant occurs on the RHS.
     ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond);
     if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT()))
       return SDValue();
     return getSetCC(dl, VT, N2, N1, SwappedCond);
-  } else if (N2CFP && N2CFP->getValueAPF().isNaN()) {
-    // If an operand is known to be a nan, we can fold it.
+  } else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
+             (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) {
+    // If an operand is known to be a nan (or undef that could be a nan), we can
+    // fold it.
+    // Choosing NaN for the undef will always make unordered comparison succeed
+    // and ordered comparison fails.
+    // Matches behavior in llvm::ConstantFoldCompareInstruction.
     switch (ISD::getUnorderedFlavor(Cond)) {
     default:
       llvm_unreachable("Unknown flavor!");
     case 0: // Known false.
       return getBoolConstant(false, dl, VT, OpVT);
     case 1: // Known true.
       return getBoolConstant(true, dl, VT, OpVT);
     case 2: // Undefined.

test/CodeGen/AArch64/half.ll

 ; CHECK-NEXT:    fcvt h0, d0
 ; CHECK-NEXT:    str h0, [x0]
 ; CHECK-NEXT:    ret
   %val16 = fptrunc double %in to half
   store half %val16, half* %addr
   ret void
 }
 
-define i16 @test_fccmp(i1 %a) {
+define i16 @test_fccmp(i1 %a, i16 %in) {
 ; CHECK-LABEL: test_fccmp:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #24576
+; CHECK-NEXT:    fmov s0, w1
 ; CHECK-NEXT:    movk w8, #15974, lsl #16
 ; CHECK-NEXT:    mov w9, #16384
+; CHECK-NEXT:    fcvt s0, h0
 ; CHECK-NEXT:    movk w9, #15428, lsl #16
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fmov s0, w9
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcmp s0, s1
+; CHECK-NEXT:    fmov s1, w9
 ; CHECK-NEXT:    cset w8, pl
-; CHECK-NEXT:    fccmp s0, s0, #8, pl
+; CHECK-NEXT:    fccmp s0, s1, #8, pl
 ; CHECK-NEXT:    mov w9, #4
 ; CHECK-NEXT:    csinc w9, w9, wzr, mi
 ; CHECK-NEXT:    add w0, w8, w9
 ; CHECK-NEXT:    ret
-  %cmp0 = fcmp ogt half 0xH3333, undef
-  %cmp1 = fcmp ogt half 0xH2222, undef
+  %f16 = bitcast i16 %in to half
+  %cmp0 = fcmp ogt half 0xH3333, %f16
+  %cmp1 = fcmp ogt half 0xH2222, %f16
   %x = select i1 %cmp0, i16 0, i16 1
   %or = or i1 %cmp1, %cmp0
   %y = select i1 %or, i16 4, i16 1
   %r = add i16 %x, %y
   ret i16 %r
 }

test/CodeGen/ARM/fcmp-xo.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR
 ; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON
 
-define arm_aapcs_vfpcc float @foo0() local_unnamed_addr {
+define arm_aapcs_vfpcc float @foo0(float %a0) local_unnamed_addr {
 ; CHECK-LABEL: foo0:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.f32 s0, #5.000000e-01
-; CHECK-NEXT:    vmov.f32 s2, #-5.000000e-01
 ; CHECK-NEXT:    vcmpe.f32 s0, #0
+; CHECK-NEXT:    vmov.f32 s2, #5.000000e-01
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    vmov.f32 s4, #-5.000000e-01
 ; CHECK-NEXT:    it mi
-; CHECK-NEXT:    vmovmi.f32 s0, s2
+; CHECK-NEXT:    vmovmi.f32 s2, s4
+; CHECK-NEXT:    vmov.f32 s0, s2
 ; CHECK-NEXT:    bx lr
-  %1 = fcmp nsz olt float undef, 0.000000e+00
+  %1 = fcmp nsz olt float %a0, 0.000000e+00
   %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
   ret float %2
 }
 
-define arm_aapcs_vfpcc float @float1() local_unnamed_addr {
+define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr {
 ; CHECK-LABEL: float1:
 ; CHECK:       @ %bb.0: @ %.end
-; CHECK-NEXT:    vmov.f32 s0, #1.000000e+00
-; CHECK-NEXT:    vmov.f32 s2, #5.000000e-01
-; CHECK-NEXT:    vmov.f32 s4, #-5.000000e-01
-; CHECK-NEXT:    vcmpe.f32 s0, s0
+; CHECK-NEXT:    vmov.f32 s2, #1.000000e+00
+; CHECK-NEXT:    vmov.f32 s4, #5.000000e-01
+; CHECK-NEXT:    vmov.f32 s6, #-5.000000e-01
+; CHECK-NEXT:    vcmpe.f32 s2, s0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-NEXT:    vselgt.f32 s0, s4, s2
+; CHECK-NEXT:    vselgt.f32 s0, s6, s4
 ; CHECK-NEXT:    bx lr
   br i1 undef, label %.end, label %1
 
-  %2 = fcmp nsz olt float undef, 1.000000e+00
+  %2 = fcmp nsz olt float %a0, 1.000000e+00
   %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
   br label %.end
 
 .end:
   %4 = phi float [ undef, %0 ], [ %3, %1]
   ret float %4
 }
 
-define arm_aapcs_vfpcc float @float128() local_unnamed_addr {
+define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
 ; VMOVSR-LABEL: float128:
 ; VMOVSR:       @ %bb.0:
 ; VMOVSR-NEXT:    mov.w r0, #1124073472
-; VMOVSR-NEXT:    vmov.f32 s2, #5.000000e-01
-; VMOVSR-NEXT:    vmov s0, r0
-; VMOVSR-NEXT:    vmov.f32 s4, #-5.000000e-01
-; VMOVSR-NEXT:    vcmpe.f32 s0, s0
+; VMOVSR-NEXT:    vmov.f32 s4, #5.000000e-01
+; VMOVSR-NEXT:    vmov s2, r0
+; VMOVSR-NEXT:    vmov.f32 s6, #-5.000000e-01
+; VMOVSR-NEXT:    vcmpe.f32 s2, s0
 ; VMOVSR-NEXT:    vmrs APSR_nzcv, fpscr
-; VMOVSR-NEXT:    vselgt.f32 s0, s4, s2
+; VMOVSR-NEXT:    vselgt.f32 s0, s6, s4
 ; VMOVSR-NEXT:    bx lr
 ;
 ; NEON-LABEL: float128:
 ; NEON:       @ %bb.0:
-; NEON-NEXT:    vmov.f32 s0, #5.000000e-01
 ; NEON-NEXT:    mov.w r0, #1124073472
-; NEON-NEXT:    vmov d2, r0, r0
-; NEON-NEXT:    vmov.f32 s2, #-5.000000e-01
-; NEON-NEXT:    vcmpe.f32 s4, s0
+; NEON-NEXT:    vmov.f32 s2, #5.000000e-01
+; NEON-NEXT:    vmov d3, r0, r0
+; NEON-NEXT:    vmov.f32 s4, #-5.000000e-01
+; NEON-NEXT:    vcmpe.f32 s6, s0
 ; NEON-NEXT:    vmrs APSR_nzcv, fpscr
-; NEON-NEXT:    vselgt.f32 s0, s2, s0
+; NEON-NEXT:    vselgt.f32 s0, s4, s2
 ; NEON-NEXT:    bx lr
-  %1 = fcmp nsz olt float undef, 128.000000e+00
+  %1 = fcmp nsz olt float %a0, 128.000000e+00
   %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
   ret float %2
 }
 
-define arm_aapcs_vfpcc double @double1() local_unnamed_addr {
+define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr {
 ; CHECK-LABEL: double1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    vmov.f64 d18, #1.000000e+00
-; CHECK-NEXT:    vcmpe.f64 d18, d16
+; CHECK-NEXT:    vcmpe.f64 d18, d0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
+; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
 ; CHECK-NEXT:    vselgt.f64 d0, d17, d16
 ; CHECK-NEXT:    bx lr
-  %1 = fcmp nsz olt double undef, 1.000000e+00
+  %1 = fcmp nsz olt double %a0, 1.000000e+00
   %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
   ret double %2
 }
 
-define arm_aapcs_vfpcc double @double128() local_unnamed_addr {
+define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr {
 ; CHECK-LABEL: double128:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    movs r0, #0
-; CHECK-NEXT:    movt r0, #16480
 ; CHECK-NEXT:    movs r1, #0
+; CHECK-NEXT:    movt r0, #16480
+; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    vmov d18, r1, r0
-; CHECK-NEXT:    vcmpe.f64 d18, d16
+; CHECK-NEXT:    vcmpe.f64 d18, d0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
 ; CHECK-NEXT:    vselgt.f64 d0, d17, d16
 ; CHECK-NEXT:    bx lr
-  %1 = fcmp nsz olt double undef, 128.000000e+00
+  %1 = fcmp nsz olt double %a0, 128.000000e+00
   %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01
   ret double %2
 }

test/CodeGen/ARM/fp16-instructions.ll

 ; 29. VRINTM
 ; 30. VRINTN
 ; 31. VRINTP
 ; 32. VRINTR
 ; 33. VRINTX
 ; 34. VRINTZ
 
 ; 35. VSELEQ
-define half @select_cc1()  {
-  %1 = fcmp nsz oeq half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc1(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz oeq half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc1:
 
-; CHECK-HARDFP-FULLFP16:       vcmp.f16 s0, s0
-; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16:       vcmp.f16 s6, s0
+; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16:       vseleq.f16  s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmp.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmp.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmoveq.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmp.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmp.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32:       vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32:       it eq
 ; CHECK-SOFTFP-FP16-T32:       vmoveq.f32 s{{.}}, s{{.}}
 }
 
 ; FIXME: more tests need to be added for VSELGE and VSELGT.
 ; That is, more combinations of immediate operands that can or can't
 ; be encoded as an FP16 immediate need to be added here.
 ;
 ; 36. VSELGE
-define half @select_cc_ge1()  {
-  %1 = fcmp nsz oge half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_ge1(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz oge half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_ge1:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
-; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s6, s0
+; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselge.f16 s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovge.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it ge
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovge.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_ge2()  {
-  %1 = fcmp nsz ole half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_ge2(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz ole half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_ge2:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s6
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselge.f16 s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovls.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it ls
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovls.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_ge3()  {
-  %1 = fcmp nsz ugt half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_ge3(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz ugt half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_ge3:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s6
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselge.f16 s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovhi.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it hi
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovhi.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_ge4()  {
-  %1 = fcmp nsz ult half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_ge4(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz ult half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_ge4:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s6, s0
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselge.f16 s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovlt.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it lt
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovlt.f32 s{{.}}, s{{.}}
 }
 
 ; 37. VSELGT
-define half @select_cc_gt1()  {
-  %1 = fcmp nsz ogt half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_gt1(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz ogt half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_gt1:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s6, s0
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselgt.f16  s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovgt.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it gt
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovgt.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_gt2()  {
-  %1 = fcmp nsz uge half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_gt2(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz uge half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_gt2:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s6
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs  APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselgt.f16  s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovpl.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it pl
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovpl.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_gt3()  {
-  %1 = fcmp nsz ule half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_gt3(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz ule half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_gt3:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s6, s0
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs  APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselgt.f16  s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovle.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it le
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovle.f32 s{{.}}, s{{.}}
 }
 
-define half @select_cc_gt4()  {
-  %1 = fcmp nsz olt half undef, 0xH0001
-  %2 = select i1 %1, half 0xHC000, half 0xH0002
-  ret half %2
+define half @select_cc_gt4(half* %a0)  {
+  %1 = load half, half* %a0
+  %2 = fcmp nsz olt half %1, 0xH0001
+  %3 = select i1 %2, half 0xHC000, half 0xH0002
+  ret half %3
 
 ; CHECK-LABEL:                 select_cc_gt4:
 
-; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s0
+; CHECK-HARDFP-FULLFP16:       vcmpe.f16 s0, s6
 ; CHECK-HARDFP-FULLFP16-NEXT:  vmrs  APSR_nzcv, fpscr
 ; CHECK-HARDFP-FULLFP16-NEXT:  vselgt.f16  s0, s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-A32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-A32-NEXT:  vmovmi.f32 s{{.}}, s{{.}}
 
-; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s0, s0
+; CHECK-SOFTFP-FP16-T32:       vcmpe.f32 s6, s0
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmrs APSR_nzcv, fpscr
 ; CHECK-SOFTFP-FP16-T32-NEXT:  it mi
 ; CHECK-SOFTFP-FP16-T32-NEXT:  vmovmi.f32 s{{.}}, s{{.}}
 }
 
 ; 38. VSELVS
 define float @select_cc4(float %a.coerce) {
 entry:

test/CodeGen/ARM/vcge.ll

; CHECK-NEXT:    mov pc, lr
   %tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
   ret <8 x i8> %tmp4
 }
 
 ; Radar 8782191
 ; Floating-point comparisons against zero produce results with integer
 ; elements, not floating-point elements.
-define void @test_vclez_fp() nounwind optsize {
+define void @test_vclez_fp(<4 x float>* %A) nounwind optsize {
 ; CHECK-LABEL: test_vclez_fp:
 ; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    vcle.f32 q8, q8, #0
 ; CHECK-NEXT:    vmovn.i32 d16, q8
 ; CHECK-NEXT:    vmov.i8 d17, #0x1
 ; CHECK-NEXT:    vuzp.8 d16, d18
 ; CHECK-NEXT:    vadd.i8 d16, d16, d17
 ; CHECK-NEXT:    vst1.8 {d16}, [r0]
 entry:
-  %0 = fcmp ole <4 x float> undef, zeroinitializer
+  %ld = load <4 x float>, <4 x float>* %A
+  %0 = fcmp ole <4 x float> %ld, zeroinitializer
   %1 = sext <4 x i1> %0 to <4 x i16>
   %2 = add <4 x i16> %1, zeroinitializer
   %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %5 = trunc <8 x i16> %4 to <8 x i8>
   tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %5, i32 1)
   unreachable
 }
 
 declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind

test/CodeGen/SPARC/fp128.ll

 }
 
 ; CHECK-LABEL: f128_compare2:
 ; HARD:        fcmpq
 ; HARD:        fb{{ule|g}}
 ; SOFT:       _Q_cmp
 ; SOFT:       cmp
 
-define i32 @f128_compare2() {
+define i32 @f128_compare2(fp128* byval %f0) {
 entry:
-  %0 = fcmp ogt fp128 undef, 0xL00000000000000000000000000000000
-  br i1 %0, label %"5", label %"7"
+  %0 = load fp128, fp128* %f0, align 8
+  %1 = fcmp ogt fp128 %0, 0xL00000000000000000000000000000000
+  br i1 %1, label %"5", label %"7"
 
 "5":                                              ; preds = %entry
   ret i32 0
 
 "7":                                              ; preds = %entry
   ret i32 1
 }