[InstCombine] Extra null-checking on TFE/LWE support

[hliao]

Summary

Need extra null-checking after ConstantInt dyn_cast.

[lebedev.ri]

1. -U99999
2. Test?

[hliao]

this's early review. test will be added soon.

[hliao]

test case is added

[arsenm]

llvm/test/Transforms/InstCombine/crash.tfe.ll

1 ↗

(On Diff #184771)

This is going to fail if AMDGPU isn't built. This should go in test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll with the others

[hliao]

move to AMDGPU specific test

[hliao]

update with -U9999

[arsenm]

In D57539#1380953, @hliao wrote:

move to AMDGPU specific test

I meant literally in the same file. Can you move it in and follow the same naming scheme as the other functions there?

[hliao]

merge that trivial test case into the originally one.

[arsenm]

LGTM

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Value *InstCombiner::simplifyAMDGCNMemoryIntrinsicDemanded(IntrinsicInst *II,
                                                            APInt DemandedElts,
                                                            int DMaskIdx,
                                                            int TFCIdx) {
   unsigned VWidth = II->getType()->getVectorNumElements();
   if (VWidth == 1)
     return nullptr;
 
   // Need to change to new instruction format
-  ConstantInt *TFC = nullptr;
   bool TFELWEEnabled = false;
   if (TFCIdx > 0) {
-    TFC = dyn_cast<ConstantInt>(II->getArgOperand(TFCIdx));
+    if (ConstantInt *TFC = dyn_cast<ConstantInt>(II->getArgOperand(TFCIdx)))
       TFELWEEnabled =    TFC->getZExtValue() & 0x1  // TFE
                       || TFC->getZExtValue() & 0x2; // LWE
   }
 
   if (TFELWEEnabled)
     return nullptr; // TFE not yet supported
 
   ConstantInt *NewDMask = nullptr;
 
   if (DMaskIdx < 0) {

llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll

 ; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 1, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
 ; CHECK-NEXT: ret float %data
 define amdgpu_ps float @extract_elt0_image_getresinfo_1d_v4f32_i32(i32 %mip, <8 x i32> inreg %sampler) #0 {
   %data = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
   %elt0 = extractelement <4 x float> %data, i32 0
   ret float %elt0
 }
 
+; Verify that we don't creash on non-constant operand.
+define protected <4 x half> @__llvm_amdgcn_image_sample_d_1darray_v4f16_f32_f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1 zeroext, i32, i32) local_unnamed_addr {
+  %tmp = tail call <4 x half> @llvm.amdgcn.image.sample.d.1darray.v4f16.f32.f32(i32 %0, float %1, float %2, float %3, float %4, <8 x i32> %5, <4 x i32> %6, i1 zeroext %7, i32 %8, i32 %9) #1
+  ret <4 x half> %tmp
+}
+
 declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1
+declare <4 x half> @llvm.amdgcn.image.sample.d.1darray.v4f16.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
 
 !0 = !{float 2.500000e+00}