VirtRegMap: Preserve LiveDebugVariables

[arsenm]

Summary

This avoids recomputing it between regalloc runs.

[arsenm]

ping

[qcolombet]

lib/CodeGen/VirtRegMap.cpp

274

DebugVars may be nullptr IIRC what getAnalysisIfAvailable API does.

Make sure to test for it.

[arsenm]

Rebase and fix null check

[qcolombet]

llvm/lib/CodeGen/VirtRegMap.cpp

273 ↗

(On Diff #313459)

I think we should push the test on DebugVars before this block.
Otherwise

1. we won't clear the VRM and MRI when DebugVars are not present.
2. we won't emit the debug values all the time (but maybe that's ok?)

I.e.,

if (DebugVars)
  DebugVars->emitDebugValues(VRM).

if (ClearVirtRegs) {
  VRM->clearAllVirt();
  MRI->clearAllVirt();
}

[qcolombet]

llvm/lib/CodeGen/VirtRegMap.cpp

273 ↗

(On Diff #313459)

2. we won't emit the debug values all the time (but maybe that's ok?)

Looks like it would be okay, since you had:

if (!ClearVirtRegs)
   AU.addPreserved<LiveDebugVariables>();

Still, it is okay to assume ClearVirtRegs will be set eventually. E.g., what happens for WebAssembly?

[arsenm]

llvm/lib/CodeGen/VirtRegMap.cpp

273 ↗

(On Diff #313459)

I think this was to avoid double-emitting the debug values, since this will be run twice

[arsenm]

Add comment and test for double emission

[arsenm]

llvm/lib/CodeGen/VirtRegMap.cpp

273 ↗

(On Diff #313459)

Without this, the debug values end up getting emitted twice. It doesn't matter for webassembly since the allocator passes are never run

[arsenm]

ping

[arsenm]

ping

[arsenm]

808dc6f8663c4c0696fc6eaf998db61a06330266

lib/CodeGen/VirtRegMap.cpp

 class VirtRegRewriter : public MachineFunctionPass {
   MachineFunction *MF;
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
   SlotIndexes *Indexes;
   LiveIntervals *LIS;
   VirtRegMap *VRM;
+  LiveDebugVariables *DebugVars;
   DenseSet<unsigned> RewriteRegs;
   bool ClearVirtRegs;
 
   void rewrite();
   void addMBBLiveIns();
   bool readsUndefSubreg(const MachineOperand &MO) const;
   void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
   void handleIdentityCopy(MachineInstr &MI);
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<LiveIntervals>();
   AU.addPreserved<LiveIntervals>();
   AU.addRequired<SlotIndexes>();
   AU.addPreserved<SlotIndexes>();
   AU.addRequired<LiveDebugVariables>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();
   AU.addRequired<VirtRegMap>();
+
+  if (!ClearVirtRegs)
+    AU.addPreserved<LiveDebugVariables>();
+
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
   MF = &fn;
   TRI = MF->getSubtarget().getRegisterInfo();
   TII = MF->getSubtarget().getInstrInfo();
   MRI = &MF->getRegInfo();
   Indexes = &getAnalysis<SlotIndexes>();
   LIS = &getAnalysis<LiveIntervals>();
   VRM = &getAnalysis<VirtRegMap>();
+  DebugVars = getAnalysisIfAvailable<LiveDebugVariables>();
   LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
                     << "********** Function: " << MF->getName() << '\n');
   LLVM_DEBUG(VRM->dump());
 
   // Add kill flags while we still have virtual registers.
   LIS->addKillFlags(VRM);
 
   // Live-in lists on basic blocks are required for physregs.
   addMBBLiveIns();
 
   // Rewrite virtual registers.
   rewrite();
 
+  if (ClearVirtRegs) {
     // Write out new DBG_VALUE instructions.
-  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
+    DebugVars->emitDebugValues(VRM);
 
-  if (ClearVirtRegs) {
     // All machine operands and other references to virtual registers have been
     // replaced. Remove the virtual registers and release all the transient data.
     VRM->clearAllVirt();
     MRI->clearVirtRegs();
   }
 
   return true;
 }

test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll

 ; RUN: not llc -regalloc=fast -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s
 
 
 ; REGALLOC: -regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc
 
 ; DEFAULT: Greedy Register Allocator
 ; DEFAULT-NEXT: Virtual Register Rewriter
 ; DEFAULT-NEXT: SI lower SGPR spill instructions
-; DEFAULT-NEXT: Debug Variable Analysis
 ; DEFAULT-NEXT: Virtual Register Map
 ; DEFAULT-NEXT: Live Register Matrix
 ; DEFAULT-NEXT: Machine Optimization Remark Emitter
 ; DEFAULT-NEXT: Greedy Register Allocator
 ; DEFAULT-NEXT: Virtual Register Rewriter
 ; DEFAULT-NEXT: Stack Slot Coloring
 
 ; O0: Fast Register Allocator
 ; O0-NEXT: SI lower SGPR spill instructions
 ; O0-NEXT: Fast Register Allocator
 ; O0-NEXT: SI Fix VGPR copies
 
 
 
 
 ; BASIC-DEFAULT: Debug Variable Analysis
 ; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis
 ; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis
 ; BASIC-DEFAULT-NEXT: Virtual Register Map
 ; BASIC-DEFAULT-NEXT: Live Register Matrix
 ; BASIC-DEFAULT-NEXT: Basic Register Allocator
 ; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
 ; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions
-; BASIC-DEFAULT-NEXT: Debug Variable Analysis
 ; BASIC-DEFAULT-NEXT: Virtual Register Map
 ; BASIC-DEFAULT-NEXT: Live Register Matrix
 ; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges
 ; BASIC-DEFAULT-NEXT: Spill Code Placement Analysis
 ; BASIC-DEFAULT-NEXT: Lazy Machine Block Frequency Analysis
 ; BASIC-DEFAULT-NEXT: Machine Optimization Remark Emitter
 ; BASIC-DEFAULT-NEXT: Greedy Register Allocator
 ; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
 ; BASIC-DEFAULT-NEXT: Stack Slot Coloring
 
 
 
 ; DEFAULT-BASIC: Greedy Register Allocator
 ; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
 ; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions
-; DEFAULT-BASIC-NEXT: Debug Variable Analysis
 ; DEFAULT-BASIC-NEXT: Virtual Register Map
 ; DEFAULT-BASIC-NEXT: Live Register Matrix
 ; DEFAULT-BASIC-NEXT: Basic Register Allocator
 ; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
 ; DEFAULT-BASIC-NEXT: Stack Slot Coloring
 
 
 
 ; BASIC-BASIC: Debug Variable Analysis
 ; BASIC-BASIC-NEXT: Live Stack Slot Analysis
 ; BASIC-BASIC-NEXT: Machine Block Frequency Analysis
 ; BASIC-BASIC-NEXT: Virtual Register Map
 ; BASIC-BASIC-NEXT: Live Register Matrix
 ; BASIC-BASIC-NEXT: Basic Register Allocator
 ; BASIC-BASIC-NEXT: Virtual Register Rewriter
 ; BASIC-BASIC-NEXT: SI lower SGPR spill instructions
-; BASIC-BASIC-NEXT: Debug Variable Analysis
 ; BASIC-BASIC-NEXT: Virtual Register Map
 ; BASIC-BASIC-NEXT: Live Register Matrix
 ; BASIC-BASIC-NEXT: Basic Register Allocator
 ; BASIC-BASIC-NEXT: Virtual Register Rewriter
 ; BASIC-BASIC-NEXT: Stack Slot Coloring
 
 
 declare void @bar()