VirtRegMap: Add pass option to not clear virt regs

[arsenm]

Summary

In a future change it will be possible to run register
allocation with a specific set of register classes,
so some of the remaining virtual registers will still
be meaningful.

[arsenm]

ping

[qcolombet]

I would rather that we clean only what has been rewritten instead of passing when we are done with all the rewriting, but let's move forward!

[arsenm]

1cf3d68f9731199b3f753c5a87826c40a4d2168b

include/llvm/CodeGen/Passes.h

/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
   extern char &RAGreedyID;
 
   /// Basic register allocator.
   extern char &RABasicID;
 
   /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
   /// assigned in VirtRegMap.
   extern char &VirtRegRewriterID;
+  FunctionPass *createVirtRegRewriter(bool ClearVirtRegs = true);
 
   /// UnreachableMachineBlockElimination - This pass removes unreachable
   /// machine basic blocks.
   extern char &UnreachableMachineBlockElimID;
 
   /// DeadMachineInstructionElim - This pass removes dead machine instructions.
   extern char &DeadMachineInstructionElimID;
 

lib/CodeGen/VirtRegMap.cpp

 class VirtRegRewriter : public MachineFunctionPass {
   MachineFunction *MF;
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
   SlotIndexes *Indexes;
   LiveIntervals *LIS;
   VirtRegMap *VRM;
+  bool ClearVirtRegs;
 
   void rewrite();
   void addMBBLiveIns();
   bool readsUndefSubreg(const MachineOperand &MO) const;
   void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
   void handleIdentityCopy(MachineInstr &MI) const;
   void expandCopyBundle(MachineInstr &MI) const;
   bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
 
 public:
   static char ID;
-
-  VirtRegRewriter() : MachineFunctionPass(ID) {}
+  VirtRegRewriter(bool ClearVirtRegs_ = true) :
+    MachineFunctionPass(ID),
+    ClearVirtRegs(ClearVirtRegs_) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction&) override;
 
   MachineFunctionProperties getSetProperties() const override {
+    if (ClearVirtRegs) {
       return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
     }
+
+    return MachineFunctionProperties();
+  }
 };
 
 } // end anonymous namespace
 
 char VirtRegRewriter::ID = 0;
 
 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
 
bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
   addMBBLiveIns();
 
   // Rewrite virtual registers.
   rewrite();
 
   // Write out new DBG_VALUE instructions.
   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
 
+  if (ClearVirtRegs) {
     // All machine operands and other references to virtual registers have been
     // replaced. Remove the virtual registers and release all the transient data.
     VRM->clearAllVirt();
     MRI->clearVirtRegs();
+  }
+
   return true;
 }
 
 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
                                              unsigned PhysReg) const {
   assert(!LI.empty());
   assert(LI.hasSubRanges());
 
for (MachineBasicBlock::instr_iterator
 
       expandCopyBundle(*MI);
 
       // We can remove identity copies right now.
       handleIdentityCopy(*MI);
     }
   }
 }
+
+FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
+  return new VirtRegRewriter(ClearVirtRegs);
+}